Using non-isolated cells as drain side select gates for sub-blocks in memory devices

Abstract

The present disclosure relates to using non-isolated cells as drain-side select gates for sub-blocks in a memory device. Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain side of the block to activate the first sub-block, and causes a program signal to be applied to a selected word line of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected word line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to using non-isolated cells as drain-side select gates for sub-blocks in a memory device for a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] One aspect of the present disclosure is directed to a memory device comprising: a memory array; and control logic coupled in operative connection with the memory array to perform operations comprising: receiving a request to program data to a block of the memory array, the block comprising a plurality of sub-blocks; identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data; causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain side of the block to activate the first sub-block; and causing a program signal to be applied to a selected word line of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected word line.

[0004] Another aspect of the present disclosure is directed to a method comprising: receiving a request to program data to a block of a memory array of a memory device, the block comprising a plurality of sub-blocks; identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data; causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain side of the block to activate the first sub-block; and causing a program signal to be applied to a selected word line of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected word line.

[0005] Yet another aspect of the present disclosure is directed to a memory device comprising: a memory array comprising a block, the block comprising a plurality of word lines and a plurality of sub-blocks, each sub-block comprising a plurality of memory cells associated with the plurality of word lines, wherein the memory array further comprises a number of logical select gate layers positioned at a drain side of the block, wherein the number of logical select gate layers in the block is greater than or equal to the number of sub-blocks in the block, and wherein the plurality of logical select gate layers are to selectively activate individual sub-blocks of the plurality of sub-blocks in response to a received control signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will become more fully understood from the detailed description and the accompanying drawings provided below, and various embodiments of the disclosure.

[0007] Figure 1A An example computing system including a memory sub-system according to some embodiments of the disclosure is illustrated.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to some embodiments of the disclosure.

[0009] Figure 2 is a schematic diagram of a portion of a memory cell array that can be used as reference Figure 1B for a memory cell array of the type described according to some embodiments of the disclosure.

[0010] Figure 3 is a schematic diagram of a portion of a memory cell array implementing non-isolated cells as drain-side select gates for sub-blocks according to some embodiments of the disclosure.

[0011] Figure 4 is a flow diagram of an example operational method of a memory array implementing non-isolated cells as drain-side select gates for sub-blocks according to some embodiments of the disclosure.

[0012] Figure 5 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0013] Aspects of the disclosure are directed to using non-isolated cells as drain-side select gates for sub-blocks in a memory device for a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of a storage device and a memory module are described below in connection with FIG. 1. Generally, a host system can utilize a memory sub-system including one or more components (e.g., memory devices) that store data. The host system can provide data to store at the memory sub-system and can request to retrieve data from the memory sub-system.

[0014] Memory sub-systems can include high-density non-volatile memory devices in which the retention of data is required when no power is supplied to the memory devices. For example, NAND memory, such as 3D flash NAND memory, provides storage in the form of a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and has various logical states related to the number of bits stored. The logical states can be represented by binary values such as “0” and “1” or combinations of such values.

[0015] A memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon die in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address for a memory cell. Hereinafter, a block refers to a unit of a memory device used to store data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0016] A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from a host system. The memory cells of a block can be arranged along several separate word lines. Each block can include several sub-blocks, where each sub-block is defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. Because a sub-block can be individually accessed (e.g., to perform a program or read operation), a block can include structures to selectively enable the pillars associated with a particular sub-block while disabling the pillars associated with other sub-blocks. This structure can include one or more select gate devices positioned at either or both ends of each pillar. Depending on the control signals applied, these select gate devices can enable or disable the conduction of signals through the pillar.

[0017] Certain memory devices can implement these select gate devices using core memory cells (e.g., replacement gate transistors with charge trapping structures). Replacement gate transistors are programmable devices, and thus provide the benefit of high versatility when setting the corresponding threshold voltages for the select gate devices. Generally, the select gate devices associated with each pillar in a data block are controlled individually (e.g., by separate control signals), and the select gate devices themselves are physically isolated. Typically, there are cuts or slits in the memory array (e.g., at the drain side of the pillars) to physically demarcate the select gate devices in sub-blocks that are separate from one another. However, core memory cells are relatively large, and when the pillars are formed in a single processing step, the pillars at the drain end are relatively wide, leaving little space between the sub-blocks to form this physical cut or slit. Thus, other memory devices use different transistors (e.g., NMOS transistors) to form the select gate devices. Such transistors are smaller than core memory cells, and can be de-integrated at the drain end of the pillars (i.e., located at a portion of the pillar that is formed as a separate processing step from the rest of the pillar where the core memory cells are located). However, the threshold voltages of NMOS transistors are not programmable, and are fixed at the time of manufacture. This can lead to variations between the select gate devices in different sub-blocks, potentially causing reliability issues for the data stored in those sub-blocks.

[0018] Aspects of the disclosure address the above and other deficiencies by using non-isolated cells as drain-side select gates for sub-blocks in a memory device of a memory sub-system. In one embodiment, a block of a memory device can include a number of sub-blocks (e.g., four sub-blocks) and a same or greater number of layers of logical select gate devices (e.g., four layers) at the drain side of the sub-blocks. Each of the layers of logical select gate devices can include one select gate device associated with each sub-block, and each sub-block can be associated with one select gate device in each of the layers of logical select gate devices. In one embodiment, the select gate devices in each layer are formed using core memory cells (e.g., replacement gate transistors with charge trapping structures), and are non-isolated such that they are each coupled to a shared word line and controlled by a same control signal. In one embodiment, the select gate devices in the layers of logical select gate devices are programmed with a particular pattern of threshold voltages such that applying a control signal with a particular voltage on the word line can selectively activate one of the sub-blocks at a time. For example, each layer of logical select gate devices can have one half of the select gate devices (e.g., two select gate devices) programmed with a high threshold voltage and one half of the select gate devices (e.g., two select gate devices) programmed with a low threshold voltage, while each sub-block has one half of the layers of logical select gate devices programmed with select gate devices of a high threshold voltage and one half of the layers of logical select gate devices programmed with select gate devices of a low threshold voltage. In one embodiment, a block of a memory device can further include a layer of logical select gate control devices that includes select gate devices associated with each sub-block to provide activation control at the block level. The layer of logical select gate control devices can be positioned further from a drain side edge of the memory array than the layers of logical select gate devices, and can include select gate devices with threshold voltages that are more finely tuned than the select gate devices in the layers of logical select gate devices (possibly more coarsely programmed). Additionally, a block of a memory device can further include select gate devices that are isolated at the source side of each sub-block. These source-side select gate devices can be physically isolated by cuts or slices, can be formed using different technology than the core memory cells (e.g., NMOS transistors), and can be de-integrated at the source end of the sub-block pillars (i.e., located at a portion of the pillar that is formed as a separate processing step from the rest of the pillar where the core memory cells are located). The source-side select gate devices can be used to selectively activate different sub-blocks during programming of the drain-side select gate devices in the layers of logical select gate devices to a particular pattern of threshold voltages.

[0019] Advantages of this approach include, but are not limited to, savings in memory devices. Since the select gate devices in the logic select gate layer do not need to be physically isolated, there is no need for cuts or slits between sub-blocks on the drain side of the memory array. As a result, the spacing between sub-blocks can be reduced, leading to a reduced width of each block. In addition, core memory cells can be in the logic select gate layer, which provides the benefit of programmable threshold voltages on smaller NMOS transistors. As a result, the threshold voltages can be tuned more accurately, leading to improved performance in the memory device.

[0020] Figure 1A An example computing system 100 including a memory sub-system 110 is described in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination thereof.

[0021] The memory sub-system 110 can be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

[0023] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1A An example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, e.g., to write data to and read data from the memory sub-system 110.

[0025] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1A The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0027] Some examples of non-volatile memory devices (e.g., memory devices 130) include “NAND” type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory. Cross-point arrays of non-volatile memory can incorporate a stackable cross-grided data access array to store bits based on changes in bulk resistance. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0029] Although non-volatile memory components are described, such as 3D cross-point non-volatile memory cell arrays and NAND type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “NOR” flash memory, electrically erasable programmable read-only memory (EEPROM).

[0030] The memory sub-system controller 115 (controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, a special- purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0032] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 is illustrated as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1A The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0033] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130 as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0034] Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0035] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices, which are original memory devices 130 with control logic (e.g., local controller 135) on the die and a controller (e.g., memory sub-system controller 115) within the same memory device package for media management. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory devices 130 can represent a single die with some control logic (e.g., local media controller 135) embodied thereon. In some embodiments, one or more components of memory sub-system 110 can be omitted.

[0036] In one embodiment, memory sub-system 110 includes a memory interface component 113. Memory interface component 113 is responsible for handling the interaction of memory sub-system controller 115 with the memory devices (e.g., memory devices 130) of memory sub-system 110. For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory devices 130, such as program commands, read commands, or other commands. Additionally, memory interface component 113 can receive data from memory devices 130, such as data retrieved in response to a read command or an acknowledgement of successful execution of a program command. In some embodiments, memory sub-system controller 115 includes at least a portion of memory interface 113. For example, memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory interface component 113 is part of host system 110, an application, or an operating system.

[0037] In one embodiment, memory device 130 includes local media controller 135 and memory array 104. As described herein, memory array 104 can include a number of blocks, where each block includes a number of sub-blocks. In one embodiment, each block includes a number of logical select gate layers (logical SGD) 150 on the drain side of the sub-blocks. The number of logical select gate layers 150 can be greater than or equal to the number of sub-blocks. For example, if a block includes four sub-blocks, there can be four logical select gate layers 150. Similarly, if a block includes eight sub-blocks, there can be eight logical select gate layers 150. Additionally, if a block includes three sub-blocks, there can still be, for example, four logical select gate layers. In one embodiment, the select gate devices in each layer are formed using core memory cells (e.g., replacement gate transistors with charge trapping structures) and are non-isolated such that the select gate devices are each coupled to a shared word line and controlled by the same control signal. In one embodiment, the select gate devices in the logical select gate layers 150 are programmed with threshold voltages in a particular pattern such that applying a control signal from local media controller 135 with a particular voltage on the word line can selectively activate one of the sub-blocks at a time. For example, each logical select gate layer can have half of the select gate devices programmed with a high threshold voltage and half of the select gate devices programmed with a low threshold voltage, while each sub-block has half of the logical select gate layers programmed with select gate devices of a high threshold voltage and half of the logical select gate layers programmed with select gate devices of a low threshold voltage. Further details regarding the structure and operation of logical select gate layers 150 are described below.

[0038] Figure 1B is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory sub-system controller 115 of a memory sub-system (e.g., memory sub-system 110) in accordance with an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile telephones, and the like. Memory sub-system controller 115 (e.g., a controller external to memory device 130) can be a memory controller or other external host device. Figure 1A

[0039] Memory device 130 includes an array of memory cells 104 logically arranged in rows and columns. The memory cells of a logical row are typically connected to the same access line (e.g., word line), while the memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells of at least a portion of memory cell array 104 are typically arranged in a two-dimensional array, although other configurations are possible. For example, the memory cells of at least a portion of memory cell array 104 can be arranged in a three-dimensional array. Figure 1B ​The memory array 104 can be programmed to one of at least two target data states (not shown). In one embodiment, the memory array 104 includes a number of logical select gate layers (logical SGD) 150 at the drain side of each sub-block in the array 104.

[0040] Row decode circuitry 108 and column decode circuitry 109 are provided to decode address signals. Address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes input / output (I / O) control circuitry 160 to manage the input of commands, addresses and data to the memory device 130 and the output of data and status information from the memory device 130. Address registers 114 are in communication with the I / O control circuitry 160 and the row decode circuitry 108 and column decode circuitry 109 to latch address signals prior to decoding. Command registers 124 are in communication with the I / O control circuitry 160 and the local media controller 135 to latch incoming commands.

[0041] The controller (e.g., the local media controller 135 internal to the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local media controller 135 is in communication with the row decode circuitry 108 and column decode circuitry 109 to control the row decode circuitry 108 and column decode circuitry 109 in response to addresses.

[0042] The local media controller 135 is also in communication with a cache register 172. The cache register 172 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data, respectively. During a program operation (e.g., a write operation), data can be transferred from the cache register 172 to the data register 170 for transfer to the memory cell array 104; new data can then be latched from the I / O control circuitry 160 in the cache register 172. During a read operation, data can be transferred from the cache register 172 to the I / O control circuit 160 for output to the memory sub-system controller 115; new data can then be transferred from the data register 170 to the cache register 172. The cache register 172 and / or the data register 170 can form a page buffer (e.g., can form part of) of the memory device 130. The page buffer can further include sensing means (at the Figure 1BThe status register 122 can communicate with the I / O control circuitry 160 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115, for example, by sensing the state of a data line connected to a memory cell of the memory cell array 104 to sense the data state of the memory cell. The status register 122 can communicate with the I / O control circuitry 160 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0043] The memory device 130 receives control signals at the memory subsystem controller 115 from the local media controller 135 over the control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be further received via the control link 132, depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory subsystem controller 115 over a multiplexed input / output (I / O) bus 134 and outputs data to the memory subsystem controller 115 over the I / O bus 134.

[0044] For example, a command can be received via input / output (I / O) pins [7:0] of the I / O bus 134 at the I / O control circuitry 160 and then can be written into the command register 124. An address can be received at the I / O control circuitry 160 via input / output (I / O) pins [7:0] of the I / O bus 134 and then can be written into the address register 114. Data can be received at the I / O control circuitry 160 by input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then can be written into the cache register 172. The data can then be written into the data register 170 for programming the memory cell array 104.

[0045] In an embodiment, the cache register 172 can be omitted and data can be written directly into the data register 170. Data can also be output on input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While reference can be made to I / O pins, these can include any electrically conductive node that enables electrical connection to the memory device 130 by an external device (e.g., the memory subsystem controller 115), such as a commonly used electrically conductive pad or electrically conductive bump.

[0046] It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the foregoing simplifiedFigure 1B of memory device 130. It is recognized that the functionality described with respect to various block components can not necessarily be isolated to different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functionality of more than one block component described. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform the functionality of a single block component described. Furthermore, although specific I / O pins are described in terms of popular convention for receipt and output of various signals, it is noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) can be used in various embodiments. Figure 1B Figure 1B Figure 1B

[0047] Figure 2 is a schematic diagram of a portion of a memory cell array 104 (e.g., a NAND memory array) in a memory as can be used in reference Figure 1B described. The memory array 104 includes access lines such as word lines 2020 to 202 N and data lines such as bit lines 2040 to 204 M . The word lines 202 can be connected in a many-to-one relationship to global access lines (e.g., global word lines) not shown in Figure 2 . For some embodiments, the memory array 104 can be formed over a semiconductor, which can be conductively doped, for example, to have a conductivity type such as p-type conductivity to form, for example, a p-well, or a conductivity type such as n-type conductivity to form, for example, an n-well.

[0048] The memory array 104 can be arranged in rows (each row corresponding to a word line 202) and columns (each column corresponding to a bit line 204). Each column can include a string of memory cells (e.g., non-volatile memory cells) connected in series, such as one of NAND strings 2060 to 206 M . Each NAND string 206 can be connected (e.g., selectively connected) to a common source (SRC) 216 and can include memory cells 2080 to 208 N . The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field effect transistor) such as one of select gates 2100 to 210 M (e.g., which can be a source select transistor, commonly referred to as a select gate source), and a select gate 212 (e.g., a field effect transistor) such as one of select gates 2120 to 212 M ​​​One of them (for example, it could be a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0049] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0050] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 in the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0051] Figure 2 The memory array 104 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 104 in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend in a manner that is substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, and the bit line can be substantially parallel to the plane containing the common source 216.

[0052] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2 As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may also have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0053] Columns of memory cells 208 may be NAND strings 206 or selectively connected to several NAND strings 206 given a positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may often be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0054] Although Figure 2 Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the figure that the bit lines 204 of the memory cell array 104 can be consecutively numbered from bit line 2040 to bit line 204. MThe other groups of memory cells 208 that are collectively connected to a given word line 202 can also define a physical page of memory cells 208. For certain memory devices, all memory cells that are collectively connected to a given word line can be considered a physical page of memory cells. A portion of a physical page of memory cells (which can still be an entire row in some embodiments), such as an upper or lower page of memory cells, that is read during a single read operation or programmed during a single program operation can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as all memory cells connected to word lines 2020 through 202 N Unless explicitly distinguished, a reference to a page of memory cells herein refers to a memory cell of a logical page of memory cells. While examples are discussed in connection with NAND flash memory, Figure 2 The embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND array, NOR array, etc.).

[0055] Figure 3 is a schematic diagram of a portion of a memory cell array implementing non-isolated cells as drain-side select gates for sub-blocks in accordance with some embodiments of the present disclosure. The portion of the memory cell array (e.g., memory array 104) can be, for example, a block 300. In one embodiment, block 300 includes memory cell strings that can be grouped into sub-blocks, such as sub-blocks 3050 through 3053. In other embodiments, other numbers of sub-blocks can be included.

[0056] In particular, in at least some embodiments, block 300 includes bit lines 304, with each sub-block coupled to a bit line 304, and a common source (SRC), such as source voltage line 302. First sub-block 3050 can include first memory cell strings 3060 coupled therebetween. Second sub-block 3051 can include second memory cell strings 3061 coupled therebetween. Third sub-block 3052 can include third memory cell strings 3062 coupled therebetween. Fourth sub-block 3053 can include fourth memory cell strings 3063 coupled therebetween. As an example, first memory cell strings 3060 include a plurality of memory cells 3080,..., 308 N In at least some embodiments, a plurality of word lines (WL) are coupled with gates of memory cells of each memory cell string 3060,..., 3063. Each sub-block also includes a respective source select (SGS) transistor 3100 through 3103. Each SGS transistor can be connected to the common source to provide a voltage to the plurality of memory cells 3080... 308 Nsource. In some embodiments, the source voltage line 302 includes a source plate that supplies the source voltage. In one embodiment, the SGS transistors 3100-3103 can be physically isolated by cuts or slices, which can be formed using the same processing steps as the memory cells 3080...308 N different technology (e.g., NMOS transistors) and can be integrated from the sub-block pillar (i.e., located at a portion of the pillar that is separated from the rest of the pillar where the memory cells 3080...308 N are located). In one embodiment, a first source select gate line (D-SGS0) can be connected to the gate of the first SGS transistor 3100, a second source select gate line (D-SGS1) can be connected to the gate of the second SGS transistor 3101, a third source select gate line (D-SGS2) can be connected to the gate of the third SGS transistor 3102, and a fourth source select gate line (D-SGS3) can be connected to the gate of the fourth SGS transistor 3103.

[0057] In one embodiment, the block 300 includes one or more drain side gate induced drain leakage generator layers 320 having one or more gate induced drain leakage generator devices associated with respective sub-blocks 3050-3053 and coupled to the bit line 304. For example, the gate induced drain leakage generator devices in each layer can be connected to a common gate line GIDL.

[0058] In one embodiment, the block 300 includes a number of logic select gate layers 150 that include select gate devices associated with respective sub-blocks 3050-3053. The number of logic select gate layers 150 can be greater than or equal to the number of sub-blocks 3050-3053. In one embodiment, the select gate devices in each of the logic select gate layers 150 are formed using core memory cells (e.g., replacement gate transistors with charge trapping structures) and are non-isolated, such that the devices in each layer are each coupled to a shared word line and controlled by the same respective control signal (e.g., SGD0, SGD1, SGD2, SGD3).

[0059] In one embodiment, block 300 includes one or more logical select gate control layers 330 with one or more select gate devices associated with respective sub-blocks 3050-3053. For example, the select gate devices in each layer can be connected to a common gate line vSGD control. Logical select gate control layers 330 can be positioned further from the drain side edge of block 300 than the logical select gate layers, and can include select gate devices with threshold voltages that are more finely tuned (possibly more finely programmed) than the select gate devices in the logical select gate layers. In certain implementations, there can be more than one logical select gate control layer in fast 300. Additionally, the logical select gate control layers can alternatively be positioned directly over memory cell strings 3060...3063, or there can be additional logical select gate control layers positioned directly over memory cell strings 3060...3063 (e.g., under dummy word line Dummy_3 344).

[0060] In one embodiment, block 300 includes a plurality of dummy word lines positioned between other layers. For example, dummy word line Dummy_1 340 can be positioned between drain side gate induced drain leakage generator layer 320 and logical select gate layer 150, dummy word line Dummy_2 342 can be positioned between logical select gate layer 150 and logical select gate control layer 330, dummy word line Dummy_3 344 can be positioned between logical select gate control layer 330 and memory cell strings 3060...3063, and dummy word line Dummy_4 346 can be positioned between memory cell strings 3060...3063 and source select transistors 3100-3103. Each dummy word line can include memory cells associated with respective sub-blocks 3050-3053, but these memory cells are generally not used for storing data. Depending on the embodiment, there can be more than one dummy word line at the location of Dummy_1 340, Dummy_2 342, Dummy_3 344, and / or Dummy_4 346.

[0061] In one embodiment, the select gate devices in logical select gate layer 150 are programmed with threshold voltages in a pattern such that applying a control signal (e.g., SGD0, SGD1, SGD2, SGD3) of a local media controller 135 with a particular voltage on a word line can selectively activate one of sub-blocks 3050-3053 at a time. In one embodiment, each of logical select gate layers 150 can have half of the select gate devices programmed with a high threshold voltage and half of the select gate devices programmed with a low threshold voltage, while each of sub-blocks 3050-3053 has half of the logical select gate layers 150 programmed with select gate devices of a high threshold voltage and half of the logical select gate layers 150 programmed with select gate devices of a low threshold voltage. Figure 3An example pattern is illustrated in block 300, however, other patterns are possible.

[0062] As illustrated, one layer of the logic select gate layer 150 (i.e., the layer controlled by SGD0) includes select gate devices 3520-3523, where each device is associated with one of the sub-blocks 3050-3053. In this embodiment, select gate devices 3521 and 3523 are programmed with a high (H) threshold voltage (e.g., 7V), and select gate devices 3520 and 3522 are programmed with a low (L) threshold voltage (e.g., 3V). In other embodiments, the high threshold voltage and the low threshold voltage can have different values. Another layer of the logic select gate layer 150 (i.e., the layer controlled by SGD1) includes select gate devices 3540-3543, where each device is associated with one of the sub-blocks 3050-3053. In this embodiment, select gate devices 3540 and 3542 are programmed with a high (H) threshold voltage (e.g., 7V), and select gate devices 3541 and 3543 are programmed with a low (L) threshold voltage (e.g., 3V). Another layer of the logic select gate layer 150 (i.e., the layer controlled by SGD2) includes select gate devices 3560-3563, where each device is associated with one of the sub-blocks 3050-3053. In this embodiment, select gate devices 3562 and 3563 are programmed with a high (H) threshold voltage (e.g., 7V), and select gate devices 3560 and 3561 are programmed with a low (L) threshold voltage (e.g., 3V). Another layer of the logic select gate layer 150 (i.e., the layer controlled by SGD3) includes select gate devices 3580-3583, where each device is associated with one of the sub-blocks 3050-3053. In this embodiment, select gate devices 3580 and 3581 are programmed with a high (H) threshold voltage (e.g., 7V), and select gate devices 3582 and 3583 are programmed with a low (L) threshold voltage (e.g., 3V). Thus, sub-block 3050 includes select gate devices 3540 and 3580 programmed with a high threshold voltage and select gate devices 3520 and 3560 programmed with a low threshold voltage. Sub-block 3051 includes select gate devices 3521 and 3581 programmed with a high threshold voltage and select gate devices 3541 and 3561 programmed with a low threshold voltage. Sub-block 3052 includes select gate devices 3542 and 3562 programmed with a high threshold voltage and select gate devices 3512 and 3582 programmed with a low threshold voltage. Sub-block 3053 includes select gate devices 3523 and 3563 programmed with a high threshold voltage and select gate devices 3543 and 3583 programmed with a low threshold voltage.

[0063] When the threshold voltages of the select gate devices in the logical select gate layer 150 are programmed in this or a similar pattern, the application of control signals (e.g., SGD0, SGD1, SGD2, SGD3) from the local media controller 135 can selectively activate one of the sub-blocks 3050-3053 at a time. Table 1 illustrates one example of control signals that can be applied to the word lines of the logical select gate layer 150 in order to activate each particular sub-block.

[0064] SGD3 SGD2 SGD1 SGD0 Activated sub-block 7V 3V 7V 3V 3050 7V 3V 3V 7V 3051 3V 7V 7V 3V 3052 3V 7V 3V 7V 3053

[0065] Table 1

[0066] In general, if a control signal applied to a word line has a high voltage (e.g., 7V), then all select gate devices on that word line with threshold voltages at or below the high voltage will turn on. Similarly, if a control signal has a low voltage (e.g., 3V), then only the select gate devices on that word line with threshold voltages at the low voltage will turn on, while those select gate devices with high threshold voltages will remain off. As an example, if sub-block 3050 is to be activated while sub-blocks 3051-3053 remain deactivated, the following set of control signals can be applied to the word lines of the logical select gate layer 150. A high voltage is applied at SGD3, causing select gate device 3580 with a high threshold voltage to turn on, a low voltage is applied at SGD2, causing select gate device 3560 with a low threshold voltage to turn on, a high voltage is applied at SGD1, causing select gate device 3540 with a high threshold voltage to turn on, and a low voltage is applied at SGD0, causing select gate device 3520 with a low threshold voltage to turn on. Thus, all select gate devices in sub-block 3050 are activated. At the same time, however, the low voltage at SGD0 causes select gate device 3521 with a high threshold voltage to remain off, deactivating sub-block 3051, the low voltage at SGD2 causes select gate device 3562 with a high threshold voltage to remain off, deactivating sub-block 3052, and the low voltage at SGD0 causes select gate device 3523 with a high threshold voltage to remain off, deactivating sub-block 3053. Similarly, other sets of control signals can be applied to the word lines of the logical select gate layer 150 to activate other sub-blocks.

[0067] As described above, the select gate devices in the logic select gate layer 150 can be formed using core memory cells (e.g., replacement gate transistors with charge trapping structures), and thus have programmable threshold voltages. In one embodiment, the source select transistors 3100-3103 are used to program the select gate devices in a particular threshold voltage pattern. For example, to program the select gate device 3580 (e.g., to a high threshold voltage), the local media controller 135 can cause a control signal D-SGS0 to be applied at the gate of the first SGS transistor 3100 in the sub-block 3050 to activate the first SGS transistor 3100 and allow the voltage from the source line 302 (e.g., a ground voltage) to fill the channels of the sub-block 3050. The remaining SGS transistors 3101-3103 can remain open, and thus the channels of the sub-blocks 3051-3053 will float (e.g., up to 10V). The local media controller 135 can further cause a program voltage pulse (e.g., 20V) to be applied to the gate of the select gate device 3580 via the control signal SGD3. The gate-channel potential difference at the select gate device 3580 will be large enough to program the select gate device 3580, while other memory devices in the same logic select gate layer but associated with different sub-blocks are not programmed. Depending on the embodiment, a number of program pulses can be applied in order to bring the select gate device 3580 to the desired threshold voltage level (e.g., 7V). A similar process can be repeated for the remaining select gate devices in the sub-block 3050 (i.e., select gate devices 3560, 3540, 3520) with the first SGS transistor 3100 in the sub-block 3050 remaining activated. Once complete, the local media controller can move to the sub-block 3051, activate the first SGS transistor 3101, and proceed similarly. Once all of the select gate transistors in the logic select gate layer 150 have been programmed to the appropriate pattern of threshold voltages, the local media controller can similarly program the devices in the logic select gate control layer 330 and the memory cells on the word lines WLO-WL N

[0068] Figure 4 is a flow diagram of an example method of operation for a memory array to implement non-isolated cells as drain-side select gates for a sub-block in accordance with some embodiments of the present disclosure. The method 400 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1A and Figure 1B ​by the local media controller 135. Although shown in a particular order or sequence, unless otherwise specified, the order or sequence can be modified. Thus, the illustrated embodiments should be understood only as examples, and that the illustrated procedures can be performed in a different order, and that some procedures can be performed in parallel. Additionally, one or more procedures can be omitted in various embodiments. Thus, not all procedures are required in every embodiment. Other procedural flows are also possible.

[0069] At operation 405, a request is received. For example, control logic (e.g., local media controller 135) can receive, from a requester (e.g., memory interface 113 of memory sub-system controller 115), a first request to perform a memory access operation on a block (e.g., block 300 of memory array 104) of a memory array. In one embodiment, the memory access operation comprises a program operation. For example, the request can be to program one or more pages of host data to block 300 of memory array 104.

[0070] At operation 410, a control signal is applied. For example, in response to receiving the request to program data to block 300, control logic can cause a control signal (e.g., vSGD control) to be applied to logical select gate control layer 330 to activate all of the plurality of sub-blocks 3050-3053 of block 300. In one embodiment, logical select gate control layer 330 is disposed between the plurality of logical select gate layers 150 and the selected word line to which at least a portion of the data is to be programmed.

[0071] At operation 415, a sub-block is identified. For example, control logic can identify a first sub-block, e.g., sub-block 3050, of the plurality of sub-blocks 3050-3053 of block 300 to be programmed with at least a portion of the data. Depending on the data to be programmed, any of sub-blocks 3050-3053 can be selected.

[0072] At operation 420, a control signal is applied. For example, control logic can cause a plurality of control signals (e.g., SGD0- SGD3) to be applied to the plurality of logical select gate layers 150 positioned on the drain side of block 300 to activate the first sub-block (e.g., sub-block 3050). In one embodiment, the plurality of logical select gate layers 150 are disposed between the plurality of sub-blocks 3050-3053 and the selected word line (e.g., WL Nbetween shared common bit lines (e.g., bit lines 304). In one embodiment, the number of logic select gate layers 150 in block 300 is equal to the number of sub-blocks 3050-3053 in block 300. In one embodiment, each of the plurality of logic select gate layers 150 includes a respective select gate device associated with each of the plurality of sub-blocks 3050-3053, and the respective select gate device in each layer is controlled by a respective one of a plurality of control signals (e.g., SGD0- SGD3). In one embodiment, the respective select gate devices in each of the plurality of logic select gate layers 150 are programmed in a certain threshold voltage pattern, where a first half of the respective select gate devices in each logic select gate layer 150 are programmed to a high threshold voltage, and a second half of the respective select gate devices in each logic select gate layer 150 are programmed to a low threshold voltage, and where a first half of the select gate devices associated with each sub-block are programmed to a high threshold voltage, and a second half of the select gate devices associated with each sub-block are programmed to a low threshold voltage. In one embodiment, the respective select gate devices in each of the plurality of logic select gate layers 150 are programmed in a threshold voltage pattern using a plurality of de-integrated select gate devices 3100-3103 positioned at a source side of block 300, where the plurality of de-integrated select gate devices 3100-3103 are associated with a respective sub-block and are physically isolated from one another. Thus, applying a control signal (e.g., SGD0, SGD1, SGD2, SGD3) of a local media controller 135 having a certain voltage on a word line can selectively activate one of the sub-blocks 3050-3053 at a time.

[0073] At operation 425, a program signal is applied. For example, the control logic can cause a program signal to be applied to the selected word line WL N to program at least the portion of data to the memory cells in the first sub-block 3050 and associated with the selected word line. Since the channel voltage in sub-block 3050 is at ground voltage, the gate-channel voltage difference (e.g., Vpgm-GND) is large enough to cause the memory cells 308 N to be programmed.

[0074] Figure 5An example machine of computer system 500 is described, within which an instruction set is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., host system 120 of FIG1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of FIG1), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to local media controller 135 of FIG1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0075] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0076] The example computer system 500 includes a processing device 502 that communicates with each other via a bus 530, a main memory 504 (e.g., read-only memory (ROM), flash memory, such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), dynamic random access memory (DRAM), static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518.

[0077] Processing device 502 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 can further include a network interface device 508 to communicate over the network 520.

[0078] The data storage system 518 can include a machine-readable storage medium 524 (also known as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 can also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 can correspond to the memory sub-system 110 of FIG. 1.

[0079] In one embodiment, the instructions 526 include instructions to implement functionality corresponding to the local media controller 135 of FIG. 1. While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0080] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for purposes of

[0081] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0084] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0085] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made to the application without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device, comprising: a memory array; and control logic, operably coupled with the memory array, to perform operations including: receiving a request to program data to a block of the memory array, the block comprising a plurality of sub-blocks; identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data; causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain side of the block to activate the first sub-block, wherein each of the plurality of logical select gate layers comprises a respective select gate device associated with each of the plurality of sub-blocks, wherein the respective select gate device in each layer is controlled by a respective one of the plurality of control signals, wherein the respective select gate devices in each of the plurality of logical select gate layers are programmed in a certain threshold voltage pattern, wherein a first half of the respective select gate devices in each logical select gate layer are programmed to a high threshold voltage and a second half of the respective select gate devices in each logical select gate layer are programmed to a low threshold voltage, and wherein a first half of the select gate devices associated with each sub-block are programmed to the high threshold voltage and a second half of the select gate devices associated with each sub-block are programmed to the low threshold voltage; and causing a program signal to be applied to a selected word line of the block to program at least the portion of the data to memory cells in the first sub-block and associated with the selected word line.

2. The memory device of claim 1, wherein the plurality of logical select gate layers are disposed between a common bit line shared by the plurality of sub-blocks and the selected word line.

3. The memory device of claim 1, wherein a number of logical select gate layers in the block is greater than or equal to a number of sub-blocks in the block.

4. The memory device of claim 1, wherein the respective select gate devices in each of the plurality of logical select gate layers are programmed in the threshold voltage pattern using a plurality of de-integrated select gate devices positioned at a source side of the block, wherein the plurality of de-integrated select gate devices are associated with respective sub-blocks and are physically isolated from one another.

5. The memory device of claim 1, wherein the control logic is to further perform operations including: in response to receiving the request to program the data to the block, causing a control signal to be applied to a logical select gate control layer to activate all of the plurality of sub-blocks of the block, wherein the logical select gate control layer is disposed between the plurality of logical select gate layers and the selected word line.

6. A method, comprising: receiving a request to program data to a block of a memory array of a memory device, the block comprising a plurality of sub-blocks; identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data; causing application of a plurality of control signals to a plurality of logical select gate tiers positioned at a drain side of the block to activate the first sub-block, wherein each of the plurality of logical select gate tiers includes a respective select gate device associated with each of the plurality of sub-blocks, wherein the respective select gate device in each tier is controlled by a respective one of the plurality of control signals, wherein the respective select gate devices in each of the plurality of logical select gate tiers are programmed in a certain threshold voltage pattern, wherein a first half of the respective select gate devices in each logical select gate tier are programmed to a high threshold voltage and a second half of the respective select gate devices in each logical select gate tier are programmed to a low threshold voltage, and wherein a first half of the select gate devices associated with each sub-block are programmed to the high threshold voltage and a second half of the select gate devices associated with each sub-block are programmed to the low threshold voltage; and causing application of a program signal to a selected word line of the block to program at least the portion of the data to memory cells in the first sub-block and associated with the selected word line.

7. The method of claim 6, wherein the plurality of logical select gate tiers are disposed between a common bit line shared by the plurality of sub-blocks and the selected word line.

8. The method of claim 6, wherein a number of logical select gate tiers in the block is greater than or equal to a number of sub-blocks in the block.

9. The method of claim 6, wherein the respective select gate devices in each of the plurality of logical select gate tiers are programmed in the threshold voltage pattern using a plurality of de-integrated select gate devices positioned at a source side of the block, wherein the plurality of de-integrated select gate devices are associated with respective sub-blocks and are physically isolated from each other.

10. The method of claim 6, further comprising: in response to receiving the request to program the data to the block, causing application of a control signal to a logical select gate control tier to activate all of the plurality of sub-blocks of the block, wherein the logical select gate control tier is disposed between the plurality of logical select gate tiers and the selected word line.

11. A memory device, comprising: a memory array comprising a block, the block comprising a plurality of word lines and a plurality of sub-blocks, each sub-block comprising a plurality of memory cells associated with the plurality of word lines, wherein the memory array further comprises a number of logical select gate layers positioned at a drain side of the block, wherein a number of logical select gate layers in the block is greater than or equal to a number of sub-blocks in the block, and wherein the plurality of logical select gate layers selectively activate individual sub-blocks of the plurality of sub-blocks in response to received control signals, wherein each of the plurality of logical select gate layers comprises a respective select gate device associated with each of the plurality of sub-blocks, wherein the respective select gate device in each layer is controlled by a respective one of the received control signals, wherein the respective select gate devices in each of the plurality of logical select gate layers are programmed in a certain threshold voltage pattern, wherein a first half of the respective select gate devices in each logical select gate layer are programmed to a high threshold voltage and a second half of the respective select gate devices in each logical select gate layer are programmed to a low threshold voltage, and wherein a first half of the select gate devices associated with each sub-block are programmed to the high threshold voltage and a second half of the select gate devices associated with each sub-block are programmed to the low threshold voltage.

12. The memory device of claim 11, wherein the plurality of logical select gate layers are disposed between common bit lines shared by the plurality of sub-blocks and the plurality of word lines.

13. The memory device of claim 11, wherein the memory array further comprises a plurality of de-integrated select gate devices positioned at a source side of the block, and wherein the plurality of de-integrated select gate devices are associated with respective sub-blocks and are physically isolated from each other.

14. The memory device of claim 11, wherein the memory array further comprises a logical select gate control layer to activate all of the plurality of sub-blocks of a block in response to received control signals, and wherein the logical select gate control layer is disposed between the plurality of logical select gate layers and the plurality of word lines.

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