Wafer structure and method of manufacturing the same
By designing a double-step PF window in the IGBT process to improve the passivation layer exposure alignment signal, the problem of poor grating alignment mark recognition capability was solved, the recognition capability and production efficiency of the lithography machine were improved, and the consumption of raw materials and production pressure were reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2023-01-13
- Publication Date
- 2026-05-22
Smart Images
Figure CN115954308B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a wafer structure and its fabrication method. Background Technology
[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a Bipolar Junction Transistor (BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). As a hybrid power device, the IGBT combines the advantages of MOSFETs (high input impedance, low power consumption in the drive circuit, simple driving, fast switching speed, and low switching losses) with those of BJTs (high current density, strong current handling capability, and low on-state saturation voltage).
[0003] Current IGBT processes typically involve the following photolithography layers: Alignment Mark Grating (AM), P-type material implantation (DP) in a floating field ring, Active Region (OD), Polysilicon Gate Layer (PS), N-type implantation layer (SN), Contact Hole Layer (CO), Metal Layer (IN), and Passivation Layer (CB). The Primary Field (PF) window is a square area on the primary alignment mark that is selected for clearing exposure.
[0004] In the DP, PS, and IN processes, the photoresist above the PF window is exposed, developed, and then removed. The field oxide layer, polysilicon layer, and metal layer on the grating alignment mark surface are then removed sequentially by etching. The purpose is to enhance the alignment signal at the PS level and improve the alignment signal at subsequent photolithography levels by removing the polysilicon and metal layers, which are high-reflectivity and low-transmittance materials. In the CB process, many wafers fail to expose due to alignment failures, resulting in lithography machine error messages such as "8-micron error" and "No valid transitions found." Engineers typically remove the passivation material at the PF window with acetone before exposure. However, because the spin-coated passivation material is quite thick (up to 17μm), removal is often incomplete, leading to continued exposure failure. In such cases, the wafer must be detached and reworked. However, the passivation material process is complex, and the coating-exposure-development process is time-consuming. This not only increases the consumption of raw materials, but also reduces the utilization rate of equipment, prolongs the production cycle time, and increases the output pressure.
[0005] Therefore, how to improve the exposure alignment signal strength of the passivation layer process at the PF window, enhance the lithography machine's recognition of the grating alignment marks on the wafer, reduce the probability of failure to expose in the passivation layer exposure process, reduce the risk of misalignment of lithographic patterns, reduce rework rate, reduce raw material consumption, ensure equipment utilization, shorten product cycle, ensure product quality, and alleviate production pressure are urgent problems to be solved. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a wafer structure and its fabrication method to improve the exposure alignment signal intensity of the passivation layer process at the PF window.
[0007] To address the aforementioned problems, one embodiment of the present invention provides a wafer structure comprising: a grating alignment mark; a double-stepped PF window formed at a location corresponding to the grating alignment mark and exposing the grating alignment mark, the double-stepped PF window having a first step and a second step, the edge of the first step having a first distance from the grating alignment mark, the edge of the second step having a second distance from the grating alignment mark, the second distance being greater than the first distance; and a passivation layer formed on the side of the double-stepped PF window away from the grating alignment mark, having a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step.
[0008] In some embodiments, the wafer structure further includes: a field oxide layer formed on the grating alignment mark and exposing the grating alignment mark; a polysilicon layer covering the field oxide layer and having a first PF window exposing the grating alignment mark, the first PF window having a first step; a metal layer covering the polysilicon layer and having a second PF window exposing the first PF window, the second PF window having a second step, thereby forming the double-step PF window; the passivation layer covering the metal layer and forming a plane at the location corresponding to the grating alignment mark and forming an arcuate surface with reduced curvature at the step edges corresponding to the first step and the second step.
[0009] To address the aforementioned problems, one embodiment of the present invention also provides a method for fabricating a wafer structure, comprising: providing a wafer on which at least one grating alignment mark is formed; forming a double-stepped PF window at a location corresponding to the grating alignment mark, the double-stepped PF window exposing the grating alignment mark, the double-stepped PF window having a first step and a second step, the edge of the first step having a first distance from the grating alignment mark, the edge of the second step having a second distance from the grating alignment mark, the second distance being greater than the first distance; and forming a passivation layer on the side of the double-stepped PF window away from the grating alignment mark, the passivation layer having a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step.
[0010] In some embodiments, the step of forming a double-stepped PF window at the location corresponding to the grating alignment mark further includes: forming and etching a field oxide layer covering the grating alignment mark on the wafer to expose the grating alignment mark; forming and etching a polysilicon layer on the field oxide layer to form a first PF window exposing the grating alignment mark on the polysilicon layer, the first PF window having the first step; and forming and etching a metal layer on the polysilicon layer to form a second PF window exposing the first PF window on the metal layer, the second PF window having the second step, thereby forming the double-stepped PF window.
[0011] This invention employs a double-stepped PF window at the corresponding grating alignment mark, dividing the existing single high step of the PF window into a first step with its edge closer to the grating alignment mark and a second step with its edge farther away from the grating alignment mark. This improves the flatness of the passivation layer directly above the grating alignment mark, resulting in better consistency of the alignment laser as it passes through the "passivation layer-air" interface. This allows for better acquisition and carrying of grating alignment mark information, enhancing the strength and stability of the alignment signal. Simultaneously, the reduced curvature of the passivation layer's arc surface at the step further reduces reflected light entering the lens group, thereby improving the signal-to-noise ratio. The improved passivation layer process leads to more stable signal strength, significantly reducing the probability of exposure failures during exposure. Therefore, it ensures equipment utilization, reduces raw material consumption, shortens product cycles, guarantees product quality, and alleviates production pressure. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figures 1-3 This is a schematic diagram of the ASML alignment principle;
[0014] Figure 4 This is a cross-sectional view of the film layer of a wafer structure provided in an embodiment of the present invention;
[0015] Figures 5A-5B Top views of wafer structures provided in different embodiments of the present invention;
[0016] Figure 6 A comparative schematic diagram of PF windows for different wafer structures;
[0017] Figure 7 This is a schematic diagram of experimental data provided in an embodiment of the present invention;
[0018] Figure 8 This is a schematic diagram illustrating the steps of a wafer structure fabrication method according to an embodiment of the present invention. Detailed Implementation
[0019] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] This invention relates to an improvement method for the alignment signal strength of the ASML PAS stepper in the IGBT chip manufacturing process in the fabrication workshop. By redesigning the shape of the PF window, the original single vertical step of the PF window is split and expanded into an inner and outer double step. This improves the consistency of the alignment laser beam passing through the "passivation layer-air" interface at the PF window, thereby enhancing the lithography machine's recognition signal for the grating alignment marks on the wafer.
[0021] After removing the passivation material at the PF window, it was found that the PF window was recessed, with colored rings appearing on the surface. Considering that the removal of the field oxide layer, polysilicon layer, and metal layer during the previous process increased the step at the edge of the PF window, and that the spin-coated passivation material was a viscous fluid with high viscosity, forming a recessed arc-shaped structure at the PF window, this reduced the lithography machine's ability to recognize and align the grating alignment marks on the wafer.
[0022] Please refer to the following: Figures 1-3 This is a schematic diagram of the ASML alignment principle. Figure 1 As shown, the alignment laser 11 generated by the ASML stepper projection lithography machine is perpendicularly incident on the arc-shaped interface of the passivation layer (CB) 12 surface, and after refraction through the arc-shaped interface, it is incident on the grating surface of the grating alignment mark 13 on the wafer. Figure 2 As shown, the key dimensions of the grating alignment marks 13 on the wafer are typically a line width (L) of 8.0µm / 8.8µm and a spacing (S) of 8.0µm / 8.8µm. The grating alignment marks 13 diffract under perpendicular illumination by the alignment laser, and the diffracted beam 21 (using + / -1st order diffracted light) reaches the mask through the projection lens group. For example... Figure 3 As shown, the grating alignment marks 31 on the wafer (the line width or spacing in the X and Y directions is different) and the grating alignment marks 32 on the mask (the line width or spacing in the X and Y directions is different) overlap and are detected by the alignment detector. The alignment detector determines the positional deviation between the wafer and the mask by scanning these two grating alignment marks.
[0023] In the actual passivation layer exposure process, when the alignment laser is refracted through the arc-shaped interface on the passivation layer surface and then incident on the grating surface of the grating alignment mark on the wafer, the beam consistency deteriorates. Then, the light carrying the grating information from the grating alignment mark, but with deteriorated beam consistency, passes through the passivation layer surface, resulting in even worse beam consistency and thus an 8-micron error. Even if the grating information of the grating alignment mark on the wafer is identified, it cannot achieve the required alignment with the grating alignment mark on the mask, resulting in "No valid transitions found."
[0024] To improve the exposure alignment signal intensity of the passivation layer process layer at the PF window, enhance the lithography machine's recognition of the grating alignment marks on the wafer, reduce the probability of failure to expose during the passivation layer exposure process, reduce the risk of misalignment of lithographic patterns, reduce rework rate, reduce raw material consumption, ensure equipment utilization, shorten product cycle, ensure product quality, and alleviate production pressure, this invention provides a wafer structure and its fabrication method, which are explained in detail below.
[0025] An embodiment of the present invention provides a wafer structure comprising: a grating alignment mark, a double-stepped PF window, and a passivation layer; the double-stepped PF window is formed at a location corresponding to the grating alignment mark and exposes the grating alignment mark; the double-stepped PF window has a first step and a second step; the edge of the first step has a first distance from the grating alignment mark, and the edge of the second step has a second distance from the grating alignment mark, the second distance being greater than the first distance; the passivation layer is formed on the side of the double-stepped PF window away from the grating alignment mark, and has a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step.
[0026] This embodiment adopts a double-step PF window at the corresponding grating alignment mark, dividing the single high step of the existing PF window into a first step with the step edge close to the grating alignment mark and a second step with the step edge away from the grating alignment mark. This improves the flatness of the passivation layer directly above the grating alignment mark, resulting in better consistency when the alignment laser passes through the "passivation layer-air" interface. This allows for better acquisition and carrying of grating alignment mark information, enhancing the strength and stability of the alignment signal. At the same time, the reduced curvature of the passivation layer arc surface at the step further reduces the amount of reflected light entering the lens group, thereby improving the signal-to-noise ratio.
[0027] Please refer to the following: Figures 4-5B ,in, Figure 4 This is a cross-sectional view of the film layer of a wafer structure provided in an embodiment of the present invention. Figures 5A-5B Top view of the wafer structure provided for different embodiments of the present invention.
[0028] like Figure 4 As shown, the wafer structure described in this embodiment includes: a grating alignment mark 41, a field oxide layer 42, a polysilicon layer 43, a metal layer 44, and a passivation layer 45. The field oxide layer 42 is formed on the grating alignment mark 41 and exposes the grating alignment mark 41; the polysilicon layer 43 covers the field oxide layer 42 and has a first PF window 431 exposing the grating alignment mark 41, the first PF window 431 having a first step 432; the metal layer 44 covers the polysilicon layer 43 and has a second PF window 441 exposing the first PF window 431, the second PF window 441 having a second step 442; wherein, the step edge of the first step 432 has a first distance D1 between it and the grating alignment mark 41, and the step edge of the second step 442 has a second distance D2 between it and the grating alignment mark 41, the second distance D2 being greater than the first distance D1, thereby forming a double-step PF window directly above the grating alignment mark 41. The passivation layer 45 covers the metal layer 44 and forms a plane 451 at the location corresponding to the grating alignment mark 41 and an arcuate surface 452 with reduced curvature at the step edges corresponding to the first step 432 and the second step 442.
[0029] This embodiment employs a double-step PF window at the corresponding grating alignment mark. The existing single high step of the PF window is divided into a first step with its edge closer to the grating alignment mark and a second step with its edge farther away. This double-step PF window improves the flatness of the passivation layer directly above the grating alignment mark, resulting in better consistency of the alignment laser as it passes through the "passivation layer-air" interface. This allows for better acquisition and carrying of grating alignment mark information, enhancing the strength and stability of the alignment signal. Simultaneously, the double-step PF window reduces the step height at the PF window edge, decreasing the curvature of the passivation layer's arc surface at the step. This further reduces the amount of reflected light entering the lens group from the arc surface, thereby improving the signal-to-noise ratio. This embodiment can improve the exposure alignment signal strength at the passivation layer process layer at the PF window, enhance the lithography machine's recognition of the grating alignment mark on the wafer, reduce the probability of exposure failure during the passivation layer exposure process, reduce the risk of misalignment of lithographic patterns, reduce rework rates, reduce raw material consumption, ensure equipment utilization, shorten product cycles, ensure product quality, and alleviate production pressure.
[0030] In some embodiments, the first PF window 431 is square, the second PF window 441 is cross-shaped, and the orthographic projection of the second PF window 441 on the grating alignment mark 41 completely covers the orthographic projection of the first PF window 431 on the grating alignment mark 41; Figure 5A As shown. Specifically, the key dimensions of the first PF window 431 can use the existing key dimensions of the PF window, thus eliminating the need to change the key dimensions of the PF window on the mask; while during the exposure of the metal layer at the process level, an initial PF window with the same size as the first PF window is first formed, and then a cross-shaped second PF window is formed by overlay exposure to extend the four sides of the initial PF window outward; thus forming a square + cross-shaped double-step PF window above the grating alignment mark, which can improve the flatness of the passivation layer above the grating alignment mark, while reducing the curvature of the passivation layer arc surface at the step, and eliminating the need to change the key dimensions of the PF window on the mask, thus avoiding the impact on the layout when editing the process job file.
[0031] In some embodiments, both the first PF window 431 and the second PF window 441 may be square, and the orthographic projection of the second PF window 441 onto the grating alignment mark 41 completely covers the orthographic projection of the first PF window 431 onto the grating alignment mark 41; for example Figure 5B As shown. Specifically, the critical dimensions of the first PF window 431 can use existing PF window critical dimensions, thus eliminating the need to change the critical dimensions of the PF window on the mask. During the exposure at the metal layer process level, an initial PF window with the same size as the first PF window is first formed. Then, through superimposed exposure, the center of the initial PF window is shifted diagonally to the four corners to form a larger square second PF window 441. This forms a double-step PF window with a small square and a large square directly above the grating alignment mark, which improves the flatness of the passivation layer directly above the grating alignment mark and reduces the curvature of the passivation layer arc surface at the step. Furthermore, it eliminates the need to change the critical dimensions of the PF window on the mask, avoiding the impact on the layout when editing the process work file. In other embodiments, both the first PF window 431 and the second PF window 441 can be cross-shaped or other shapes that facilitate etching exposure.
[0032] In some embodiments, the passivation layer 45 is made of polyimide. Polyimide is a viscous fluid with high viscosity, which can be spin-coated onto the metal layer 44 to form a plane 451 at the corresponding grating alignment mark 41 and an arcuate surface 452 with reduced curvature at the step edges corresponding to the first step 432 and the second step 442.
[0033] Please see Figure 6 This is a schematic diagram comparing the PF windows of different wafer structures. Figure 6 Part (a) shows a schematic diagram of the original PF window of the wafer structure. Because the field oxide layer 62, polysilicon layer 63 and metal layer 64 are removed in the previous process, the step 602 at the edge of the original PF window 601 becomes higher. The passivation layer 65 forms a recessed arc-shaped structure at the original PF window 601, which makes the lithography machine's ability to identify and align the grating alignment mark 61 on the wafer worse. Figure 6 Part (b) shows a schematic diagram of a single-step enlarged PF window in a wafer structure. By directly enlarging the PF window, the flatness of the passivation layer 65 directly above the grating alignment mark 61 is improved to a certain extent. However, the height of the step 604 at the edge of the enlarged PF window 603 remains unchanged, and the curvature formed by the passivation layer 65 at the step 604 remains unchanged. Some of the light irradiated by the alignment laser at this curvature will be reflected back to the lens group, causing interference to the effective signal. Furthermore, enlarging the PF window requires directly enlarging the key dimensions of the PF window on the mask, which has a certain impact on the layout when editing the process operation file. Figure 6 Part (c) shows a schematic diagram of a double-step PF window in a wafer structure. A first PF window 691 is formed in the polysilicon layer 63 using the original process layers of the field oxide layer 62 and the polysilicon layer 63. The edge of the step 692 of the first PF window 691 is close to the grating alignment mark 61. During the process layer exposure of the metal layer 64, the four sides of the first PF window 691 are extended outwards to form a cross-shaped second PF window 693 (or the center of the first PF window 691 is shifted diagonally to the four corners and superimposed to form a larger square second PF window 693). The step of the second PF window 693... The edge of 694 is far from the grating alignment mark 61, thus forming a double-stepped PF window directly above the grating alignment mark 61. This improves the flatness of the passivation layer directly above the grating alignment mark, resulting in better consistency when the alignment laser passes through the "passivation layer-air" interface. This allows for better acquisition and carrying of grating alignment mark information, enhancing the strength and stability of the alignment signal. Simultaneously, the reduced curvature of the passivation layer's arc surface at the step further reduces reflected light entering the lens group, thereby improving the signal-to-noise ratio. Furthermore, it eliminates the need to change the critical dimensions of the PF window on the mask, avoiding layout issues when editing process files. The improved passivation layer process results in more stable signal strength, significantly reducing the probability of exposure failures during exposure. Therefore, it ensures equipment utilization, reduces raw material consumption, shortens product cycles, guarantees product quality, and alleviates production pressure.
[0034] Please see Figure 7 This is a schematic diagram of experimental data provided in one embodiment of the present invention. Figure 7The signal strength values marked in the figure represent the function value of the phase difference between the first-order reflected diffracted light from the line width and the first-order reflected diffracted light from the space. Figure 7 To divide a lot of wafers into two groups of 12 wafers each, one group (wafers 1-12) is exposed using a conventional single-step PF window, while the other group (wafers 13-24) is exposed using the double-step PF window provided by this invention. The resulting alignment data is derived from... Figure 7 As can be seen, the signal strength difference before and after exposure using the dual-step PF window provided by this invention is significant. The improved signal strength value is significantly higher than before, and the enhanced signal strength reduces the risk of pattern misalignment. During exposure, the probability of equipment rejection is significantly reduced. Using the solution of this invention for wafer production, the alignment alarm rate is reduced from 20% to <1%, close to 0, significantly ensuring product quality.
[0035] Based on the same inventive concept, the present invention also provides a method for fabricating a wafer structure, the fabricated wafer structure of which can improve the exposure alignment signal intensity of the passivation layer process layer at the PF window.
[0036] Please see Figure 8 This is a schematic diagram illustrating the steps of a wafer structure fabrication method according to an embodiment of the present invention. In this embodiment, the method includes the following steps: S1, providing a wafer on which at least one grating alignment mark is formed; S2, forming a double-stepped PF window at the location corresponding to the grating alignment mark, the double-stepped PF window exposing the grating alignment mark, the double-stepped PF window having a first step and a second step, the edge of the first step having a first distance from the grating alignment mark, the edge of the second step having a second distance from the grating alignment mark, the second distance being greater than the first distance; and S3, forming a passivation layer on the side of the double-stepped PF window away from the grating alignment mark, the passivation layer having a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step.
[0037] In some embodiments, step S2, which involves forming a double-step PF window at the location corresponding to the grating alignment mark, further includes: (1) forming and etching a field oxide layer covering the grating alignment mark on the wafer to expose the grating alignment mark; (2) forming and etching a polysilicon layer on the field oxide layer to form a first PF window exposing the grating alignment mark on the polysilicon layer, the first PF window having the first step; and (3) forming and etching a metal layer on the polysilicon layer to form a second PF window exposing the first PF window on the metal layer, the second PF window having the second step, thereby forming the double-step PF window. Specifically, the first step 432 has a first distance D1 between its step edge and the grating alignment mark 41, and the second step 442 has a second distance D2 between its step edge and the grating alignment mark 41, the second distance D2 being greater than the first distance D1, thereby forming a double-step PF window directly above the grating alignment mark 41, as shown below. Figure 4 As shown.
[0038] Following the above embodiment, the step of forming and etching a metal layer on the polysilicon layer to form a second PF window exposing the first PF window further includes: (31) forming a metal layer on the polysilicon layer; (32) performing initial etching on the metal layer using the same mask as the one used to etch the polysilicon layer to form an initial PF window with the same size as the first PF window; and (33) moving the mask to perform superimposed etching on the metal layer to extend the initial PF window outward to form the second PF window. By forming a double-step PF window directly above the grating alignment mark, the flatness of the passivation layer directly above the grating alignment mark can be improved, while reducing the curvature of the passivation layer arc surface at the step; since there is no need to change the key dimensions of the PF window on the mask, the impact on the layout is avoided when editing the process work file; at the same time, the superimposed exposure method is simple and the alignment error of the superimposed exposure is small.
[0039] In some embodiments, the first PF window is square, the second PF window is cross-shaped, and the orthographic projection of the second PF window onto the grating alignment mark completely covers the orthographic projection of the first PF window onto the grating alignment mark; such as Figure 5AAs shown. Specifically, the key dimensions of the first PF window 431 can use the existing key dimensions of the PF window, thus eliminating the need to change the key dimensions of the PF window on the mask; while during the exposure of the metal layer at the process level, an initial PF window with the same size as the first PF window is first formed, and then the four sides of the initial PF window are extended outward by superimposed exposure to form a cross-shaped second PF window; thus forming a square + cross-shaped double-step PF window above the grating alignment mark, which can improve the flatness of the passivation layer above the grating alignment mark, while reducing the curvature of the passivation layer arc surface at the step, and eliminating the need to change the key dimensions of the PF window on the mask, thus avoiding the impact on the layout when editing the process operation file.
[0040] In some embodiments, both the first PF window and the second PF window can be square, and the orthographic projection of the second PF window onto the raster alignment mark completely covers the orthographic projection of the first PF window onto the raster alignment mark; for example Figure 5B As shown. Specifically, the critical dimensions of the first PF window can use existing PF window critical dimensions, thus eliminating the need to change the critical dimensions of the PF window on the mask. During the exposure at the metal layer process level, an initial PF window with the same size as the first PF window is first formed. Then, by superimposing exposures, the center of the initial PF window is shifted diagonally to the four corners to form a larger square second PF window. This creates a double-step PF window with a small square and a large square directly above the grating alignment mark, improving the flatness of the passivation layer above the grating alignment mark and reducing the curvature of the passivation layer arc surface at the step. Furthermore, this avoids changing the critical dimensions of the PF window on the mask and prevents impact on the layout when editing the process work file. In other embodiments, both the first PF window and the second PF window can be cross-shaped or other shapes that facilitate etching exposure.
[0041] In some embodiments, step S3, which involves forming a passivation layer on the side of the double-stepped PF window away from the grating alignment mark, further includes: spin-coating a passivation material onto the metal layer to form a passivation layer. The passivation layer forms a plane at the location corresponding to the grating alignment mark and an arc-shaped surface with reduced curvature at the edges of the steps corresponding to the first and second steps. Because the passivation layer directly above the grating alignment mark is planar and has good flatness, the alignment laser passes through the "passivation layer-air" interface with better consistency, enabling better acquisition and carrying of grating alignment mark information, and enhancing the strength and stability of the alignment signal. Simultaneously, the reduced curvature of the arc-shaped surface of the passivation layer at the step further reduces the amount of reflected light entering the lens group, thereby improving the signal-to-noise ratio. After the improved passivation layer process, the signal strength is more stable, and the probability of exposure failure during exposure is significantly reduced. Therefore, it can ensure equipment utilization, reduce raw material consumption, shorten product cycle time, ensure product quality, and alleviate production pressure.
[0042] In some embodiments, the passivation layer is made of polyimide. Polyimide is a viscous fluid with high viscosity, which can be spin-coated onto the metal layer to form a plane at the location corresponding to the grating alignment mark and to form an arc-shaped surface with reduced curvature at the step edges corresponding to the first step and the second step, thereby improving the process level of the passivation layer.
[0043] As can be seen from the above, the wafer structure and its fabrication method provided in this embodiment, by adopting a double-step PF window at the corresponding grating alignment mark, divides the single high step of the existing PF window into a first step with the step edge close to the grating alignment mark and a second step with the step edge away from the grating alignment mark. This improves the flatness of the passivation layer directly above the grating alignment mark, resulting in better consistency when the alignment laser passes through the "passivation layer-air" interface. This allows for better acquisition and carrying of grating alignment mark information, enhancing the strength and stability of the alignment signal. Simultaneously, the reduced curvature of the passivation layer's arc surface at the step further reduces the amount of reflected light entering the lens group, thereby improving the signal-to-noise ratio. After the improved passivation layer process, the signal strength is more stable, and the probability of exposure failure during exposure is significantly reduced. Therefore, it ensures equipment utilization, reduces raw material consumption, shortens product cycles, guarantees product quality, and alleviates production pressure.
[0044] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.
[0045] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A wafer structure, characterized in that, include: grating alignment marks; A double-step PF window is formed at the location corresponding to the grating alignment mark and exposes the grating alignment mark. The double-step PF window has a first step and a second step. The edge of the first step has a first distance from the grating alignment mark, and the edge of the second step has a second distance from the grating alignment mark. The second distance is greater than the first distance. as well as A passivation layer is formed on the side of the double-step PF window away from the grating alignment mark, and has a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step. The double-step PF window can reduce the curvature of the arcuate surface of the passivation layer.
2. The wafer structure as described in claim 1, characterized in that, The wafer structure also includes: A field oxide layer is formed on the grating alignment mark and exposes the grating alignment mark; A polycrystalline silicon layer covers the field oxide layer and has a first PF window that exposes the grating alignment mark, the first PF window having the first step; A metal layer covers the polysilicon layer and has a second PF window that exposes the first PF window. The second PF window has a second step, thereby forming the double-step PF window. The passivation layer covers the metal layer and forms a plane at the location corresponding to the grating alignment mark, and forms an arc-shaped surface with reduced curvature at the step edges corresponding to the first step and the second step.
3. The wafer structure as described in claim 2, characterized in that, The first PF window is square, and the second PF window is cross-shaped; or both the first PF window and the second PF window are square; wherein the orthographic projection of the second PF window on the grating alignment mark completely covers the orthographic projection of the first PF window on the grating alignment mark.
4. The wafer structure as described in claim 1, characterized in that, The passivation layer is made of polyimide.
5. A method for preparing a wafer structure, characterized in that, include: A wafer is provided, on which at least one grating alignment mark is formed; A double-step PF window is formed at the location corresponding to the grating alignment mark. The double-step PF window exposes the grating alignment mark. The double-step PF window has a first step and a second step. The edge of the first step has a first distance from the grating alignment mark, and the edge of the second step has a second distance from the grating alignment mark. The second distance is greater than the first distance. as well as A passivation layer is formed on the side of the double-step PF window away from the grating alignment mark. The passivation layer has a plane corresponding to the grating alignment mark and an arcuate surface adapted to the first step and the second step. The double-step PF window can reduce the curvature of the arcuate surface of the passivation layer.
6. The method as described in claim 5, characterized in that, The step of forming a double-stepped PF window at the corresponding grating alignment mark further includes: A field oxide layer covering the grating alignment marks is formed on the wafer and etched to expose the grating alignment marks; A polysilicon layer is formed and etched on the field oxide layer to form a first PF window exposing the grating alignment mark on the polysilicon layer, the first PF window having the first step; and A metal layer is formed and etched on the polysilicon layer to form a second PF window that exposes the first PF window. The second PF window has the second step, thereby forming the double-step PF window.
7. The method as described in claim 6, characterized in that, The step of forming a metal layer on the polysilicon layer and etching thereon to form a second PF window exposing the first PF window further includes: A metal layer is formed on the polycrystalline silicon layer; The metal layer is initially etched using the same mask as the polysilicon layer to form an initial PF window with the same size as the first PF window; and The mask is moved to perform superimposed etching on the metal layer to extend the initial PF window outward to form the second PF window.
8. The method as described in claim 6, characterized in that, The first PF window is square, and the second PF window is cross-shaped; or both the first PF window and the second PF window are square; wherein the orthographic projection of the second PF window on the grating alignment mark completely covers the orthographic projection of the first PF window on the grating alignment mark.
9. The method as described in claim 6, characterized in that, The step of forming a passivation layer on the side of the double-step PF window away from the grating alignment mark further includes: spin-coating a passivation material onto the metal layer to form a passivation layer, wherein the passivation layer forms a plane at the location corresponding to the grating alignment mark and an arc-shaped surface with reduced curvature at the step edges corresponding to the first step and the second step.
10. The method as described in claim 6, characterized in that, The passivation layer is made of polyimide.