A signal processing circuit, a touch panel, and a display device

Abstract

The present disclosure provides a signal processing circuit, a touch panel and a display device, and belongs to the technical field of touch display. The signal processing circuit comprises m analog front-end units, m common-mode level preset units, M first data selectors and M analog-digital converters; the m analog front-end units and the m common-mode level preset units are one-to-one corresponding; the analog front-end unit is configured to process a first electrical signal to obtain a group of first differential signals; a group of first transmission gates and second transmission gates in the first data selector are configured to process the group of first differential signals and output a group of second differential signals; the i-th common-mode level preset unit is configured to process the group of first differential signals and output a preset common-mode voltage, and is configured to the analog-digital converter; the analog-digital converter is configured to convert the group of second differential signals output by the group of first transmission gates and second transmission gates to generate a digital signal.

Description

Technical Field

[0001] This disclosure belongs to the field of touch display technology, specifically relating to a signal processing circuit, a touch panel, and a display device. Background Technology

[0002] Touchscreen displays convert touch information from fingers into recognizable digital information for display and response processing. Typically, the integrated chip for touch display is integrated inside the touch panel. This integrated chip is usually elongated, with a low height and a long length. The integrated chip contains multiple analog front-end circuits (AFEs). The internal analog-to-digital converter (ADC) processes a set of differential signals (VOP and VON signals) output from each AFE in a time-division multiplexing manner, converting them into recognizable digital information. Due to the limitations of the chip's structural design (i.e., its elongated shape), the multiple AFEs are arranged side-by-side inside the chip. Therefore, there are AFEs farther from the ADC and AFEs closer to the ADC. This means there are at least one set of VOP and VON signals at the farther end of the traces, and at least one set of VOP and VON signals at the closer end of the traces. Because the parasitic capacitance generated at the farthest and nearest ends of the traces differs greatly, the level of the received differential signal floats when the analog-to-digital converter (ADC) first starts working. The common-mode voltages of the VOP and VON signals are not controlled by the circuit and may float to any potential, thereby reducing the accuracy of the ADC's analog-to-digital conversion. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a signal processing circuit, a touch panel, and a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a signal processing circuit configured to read a first electrical signal on a touch panel; the touch panel includes a plurality of touch electrodes arranged in an array, the number of touch electrodes in each column is m, and the m touch electrodes are divided into M groups, m>1, M≥1, and M and m are both integers; wherein, the signal processing circuit includes m analog front-end units, m common-mode level preset units, M first data selectors, and M analog-to-digital converters; the m analog front-end units and the m common-mode level preset units are configured in a one-to-one correspondence;

[0005] The i-th analog front-end unit is configured to read the first electrical signal output by the i-th touch electrode in each column of the touch electrodes in the touch panel in a time-division manner, and process the first electrical signal to obtain a set of first differential signals; i takes the range 1 to m, and i is an integer;

[0006] A set of first transmission gates and second transmission gates in one of the first data selectors are configured to process a set of first differential signals output by one of the analog front-end units and output a set of second differential signals; different sets of first transmission gates and second transmission gates process different sets of first differential signals output by the analog front-end units.

[0007] The i-th common-mode level preset unit is configured to process a set of first differential signals output by the i-th analog front-end unit, output a preset common-mode voltage, and configure it to the analog-to-digital converter.

[0008] An analog-to-digital converter is configured to convert a set of second differential signals output from a set of first transmission gates and second transmission gates to generate a digital signal.

[0009] In some embodiments, the common-mode level preset unit includes a first switch and a second switch, wherein a first terminal of the first switch is a first terminal of the common-mode level preset unit, a first terminal of the second switch is a second terminal of the common-mode level preset unit, and is configured to receive a set of the first differential signals; the second terminals of the first switch and the second terminals of the second switch are electrically connected as a third terminal of the common-mode level preset unit, and are configured to output the preset common-mode voltage.

[0010] In some embodiments, the number of a set of first transmission gates and second transmission gates is the same in each of the M first data selectors; there are a total of m sets of first transmission gates and second transmission gates in the M first data selectors.

[0011] The signal processing circuit further includes a first timing control unit; while the first and second transmission gates in the i-th group are disconnected, the first and second switches in the (i+1)-th common-mode level preset unit are turned on, and while the first and second switches in the (i+1)-th common-mode level preset unit are disconnected, the first and second transmission gates in the (i+1)-th group are turned on simultaneously.

[0012] In some embodiments, each of the analog front-end units includes a charge conversion unit, an integrator, and a sampling unit;

[0013] The charge conversion unit is configured to receive an excitation signal and a first electrical signal, and convert the first electrical signal into a second electrical signal and output it according to the excitation signal;

[0014] The integrator is configured to perform analog integration on the second electrical signal and output a third electrical signal;

[0015] The sampling unit is configured to process the third electrical signal, generate a set of the first differential signals, and output them.

[0016] In some embodiments, the charge conversion unit includes a charge amplifier, a reset capacitor, a reset control switch, and a first capacitor;

[0017] The first terminal of the charge amplifier is configured to receive the first electrical signal, and the second terminal of the charge amplifier is configured to receive the excitation signal; the third terminal of the charge amplifier is electrically connected to the first terminal of the integrator.

[0018] The first and second terminals of the reset capacitor are electrically connected to the first and third terminals of the charge amplifier, respectively; the first and second terminals of the reset control switch are electrically connected to the first and third terminals of the charge amplifier, respectively.

[0019] The first terminal of the first capacitor is electrically connected to the first terminal of the charge amplifier; the second terminal of the first capacitor is used to receive the fourth electrical signal.

[0020] In some embodiments, the sampling unit includes a first control switch, a second control switch, a third control switch, a fourth control switch, a first sampling capacitor, a second sampling capacitor, an operational amplifier, a first holding capacitor, and a second holding capacitor;

[0021] The first terminal of the first control switch is configured to receive a first reference signal; the first segment of the fourth control switch is configured to receive a second reference signal; the first terminals of the second control switch and the third control switch are both electrically connected to the second terminal of the integrator; the second terminals of the first control switch and the second control switch are both electrically connected to the first terminal of the first sampling capacitor; the second terminals of the third control switch and the fourth control switch are both electrically connected to the first terminal of the second sampling capacitor.

[0022] The second end of the first sampling capacitor and the first end of the first holding capacitor are both electrically connected to the first end of the operational amplifier; the second end of the second sampling capacitor and the first end of the second holding capacitor are both electrically connected to the second end of the operational amplifier.

[0023] The second end of the first holding capacitor is electrically connected to the third end of the operational amplifier; the second end of the second holding capacitor is electrically connected to the fourth end of the operational amplifier; the third and fourth ends of the operational amplifier are configured to output a first differential signal.

[0024] In some embodiments, the signal processing circuit further includes a control unit; the control unit is configured to control the first control switch and the third control switch to be turned on and the second control switch and the fourth control switch to be turned off when the third electrical signal is at a second level; and to control the second control switch and the fourth control switch to be turned on and the first control switch and the third control switch to be turned off when the third electrical signal is at a first level.

[0025] Secondly, embodiments of this disclosure also provide a touch panel, which includes, for example, a substrate, a plurality of touch electrodes disposed on the substrate and arranged in an array, and a signal processing circuit as described in any one of the above embodiments; the touch electrodes are electrically connected to the signal processing circuit.

[0026] In some embodiments, the invention further includes an interlayer insulating layer disposed on the side of the array of touch electrodes facing away from the substrate, and a plurality of touch signal lines disposed on the side of the interlayer insulating layer facing away from the substrate.

[0027] Each of the touch signal lines is electrically connected to a touch electrode through a connection via penetrating the interlayer insulating layer, and different touch signal lines are connected to different touch electrodes;

[0028] For the touch electrodes located in the same column, the connection lines of the connection vias that electrically connect each touch electrode to the touch signal line are not on the same straight line.

[0029] In some embodiments, for any column of the multiple touch electrodes arranged in an array, the touch electrodes are divided into multiple groups of touch electrodes arranged side by side along the column direction;

[0030] The connection lines of the multiple touch electrodes in each group of touch electrodes that are electrically connected to the touch signal lines are located on the same straight line.

[0031] In some embodiments, for different groups of the touch electrode groups, the connection lines of the connection vias that electrically connect the multiple touch electrodes to the touch signal lines are parallel to each other.

[0032] In some embodiments, the number of touch electrodes in each group of touch electrodes is equal.

[0033] In some embodiments, for any column of the multiple touch electrodes arranged in an array, the touch electrodes are divided into K groups of touch electrodes arranged side by side along the column direction; K is a positive integer greater than 1.

[0034] Each of the touch electrodes includes a first side and a second side disposed opposite to each other along the row direction; each group of the touch electrodes includes N touch electrodes, and the N touch electrodes are arranged sequentially along the column direction; N≥1, and N is rounded down;

[0035] For the touch electrode group p and the touch electrode group K-p+1 located in the same column, where,

[0036] The distance between the orthographic projection of the first side of the qth touch electrode in the p-th group of touch electrodes on the substrate and the orthographic projection of the connecting via corresponding to the qth touch electrode on the substrate is denoted as the first distance; p takes values ​​from 1 to K, and p is an integer; q takes values ​​from 1 to N, and q is an integer;

[0037] The distance between the orth projection of the second side of the N-q+1th touch electrode in the K-p+1th touch electrode group on the substrate and the orth projection of the connection via corresponding to the N-q+1th touch electrode on the substrate is denoted as the second distance;

[0038] The first distance is equal to the second distance.

[0039] In some embodiments, for any column of the arrayed touch electrodes, the spacing between any two adjacent touch signal lines connecting the touch electrodes is equal.

[0040] In some embodiments, the array of multiple touch electrodes comprises m rows and n columns; the signal processing circuit further comprises n second data selectors, with each of the n columns of touch electrodes corresponding to one of the n columns of second data selectors; each of the second data selectors comprises m third transmission gates, with each of the m third transmission gates corresponding to one of the m columns of touch electrodes; n > 1, and n is an integer;

[0041] For the touch electrodes located in the same column, one of the touch electrodes is electrically connected to a third transmission gate in a second data selector via a touch signal line, and different touch electrodes are electrically connected to different third transmission gates in a second data selector via a touch signal line.

[0042] The i-th third transmission gate in each of the second data selectors is electrically connected to the i-th analog front-end unit.

[0043] In some embodiments, the touch panel further includes a plurality of pixels disposed on the side of the array of touch electrodes near the substrate; the plurality of pixels are divided into a plurality of pixel groups; the pixels in each pixel group are arranged in an array; and the pixel groups are configured in a one-to-one correspondence with the touch electrodes.

[0044] Thirdly, embodiments of this disclosure also provide a display device, which includes a touch panel as described in any of the above embodiments.

[0045] For a description of the effects of the aforementioned touch panel and display device, please refer to the description of the signal processing circuit; it will not be repeated here.

[0046] This disclosure provides a signal processing circuit, a touch panel, and a display device. The signal processing circuit is configured to read a first electrical signal from the touch panel. The touch panel includes a plurality of touch electrodes arranged in an array, with m touch electrodes in each column, and the m touch electrodes are divided into M groups, where m > 1, M ≥ 1, and both M and m are integers. The signal processing circuit includes m analog front-end units and m common-mode level preset units, which are configured in a one-to-one correspondence. The i-th common-mode level preset unit processes a group of first differential signals output by the i-th analog front-end unit, outputs a preset common-mode voltage, and configures it to the analog-to-digital converter (ADC). That is, the output preset common-mode voltage serves as the common-mode voltage of the ADC. When the analog-to-digital converter (ADC) processes the second differential signal, the input second differential signal will no longer be in a floating state, but will be set to a preset common-mode voltage. This ensures that the input second differential signal changes from the corresponding preset common-mode voltage every time the ADC performs analog-to-digital conversion, improving the reverse symmetry of the second differential signal and the accuracy of the ADC's analog-to-digital conversion, thereby improving the accuracy of the chip's touch sampling. Attached Figure Description

[0047] Figure 1 A schematic diagram of a signal processing circuit provided in an embodiment of this disclosure;

[0048] Figure 2 This is a schematic diagram of the structure of a first data selector provided in an embodiment of the present disclosure;

[0049] Figure 3 A schematic diagram of the common-mode level preset unit provided in the embodiments of this disclosure;

[0050] Figure 4 Timing control circuit diagram of the common-mode level preset unit and the first data selector provided in the embodiments of this disclosure;

[0051] Figure 5 A schematic diagram of a simulated front-end unit provided in an embodiment of this disclosure;

[0052] Figure 6 A schematic diagram of the circuit structure of the charge conversion unit provided in an embodiment of this disclosure;

[0053] Figure 7A schematic diagram of the circuit structure of the sampling unit provided in the embodiments of this disclosure;

[0054] Figure 8 A film layer diagram of a touch panel provided in an embodiment of this disclosure;

[0055] Figure 9 This is a schematic diagram of the structure of a touch panel provided in an embodiment of the present disclosure;

[0056] Figure 10 This is a schematic diagram of a signal processing circuit coupled to a touch electrode, provided in an embodiment of the present disclosure.

[0057] The attached figures are labeled as follows: 100, signal processing circuit; 101, analog front-end unit; 102, common-mode level preset unit; 103, first data selector; 104, analog-to-digital converter; 105, digital front-end unit; 106, first timing control unit; 107, second timing control unit; 108, control unit; 109, second data selector; 1011, charge conversion unit; 1012, integrator; 1013, sampling unit; 1021, first switch; 1022, second switch; 111, charge amplifier; 112, reset capacitor; 113, reset control switch; 114. 131. First control switch; 132. Second control switch; 133. Third control switch; 134. Fourth control switch; 135. First sampling capacitor; 136. Second sampling capacitor; 137. Operational amplifier; 138. First holding capacitor; 139. Second holding capacitor; 200. Touch panel; 10. Substrate; 20. Touch electrode; 30. Interlayer insulating layer; 40. Touch signal line; 50. Light-emitting layer; 31. Connecting via; 21. First side of touch electrode; 22. Second side of touch electrode; 23. Third side of touch electrode; 24. Fourth side of touch electrode. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0060] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0061] In related technologies, the integrated chip in a touch panel integrates multiple analog front-end circuits (AFEs). The analog-to-digital converter (ADC) inside the chip processes a set of differential signals, namely VOP and VON signals, output by each AFE in a time-division multiplexing manner, converting them into recognizable digital information. Due to the limitations of the chip structure design (i.e., its elongated shape), the multiple AFEs are arranged side by side inside the chip. Therefore, there are AFEs that are farther away from the ADC and AFEs that are closer to the ADC. This means that there are at least one set of VOP and VON signals at the farther end of the traces, and at least one set of VOP and VON signals at the closer end of the traces. Because the parasitic capacitances generated at the farthest and nearest ends of the traces differ significantly, the received differential signal levels float when the analog-to-digital converter (ADC) first starts operating. The common-mode voltages of the VOP and VON signals are not controlled by the circuit and may float to any potential. For example, in a set of differential signals at the farthest end, the VOP signal may float at the power supply voltage of 3.3V, and the VON signal may float at ground voltage of 0V. In a set of differential signals at the nearthest end, the VOP signal may float at 3V, and the VON signal may float at 0.5V. Assuming the common-mode voltage of the analog-to-digital converter (ADC) is 0.8V, when the ADC starts working, the VOP signal requires more time than the VON signal to establish the common-mode voltage of the differential signal. The VOP signal at the far end needs to drop from 3.3V to 0.8V, while the VON signal needs to rise from 0V to 0.8V. The VOP signal at the near end needs to drop from 3V to 0.8V, while the VON signal needs to rise from 0.5V to 0.8V. This results in lower accuracy of the ADC's analog-to-digital conversion at the beginning of the conversion, thus affecting the touch sampling accuracy.

[0062] Based on this, the present disclosure provides a signal processing circuit that substantially eliminates one or more problems caused by limitations and defects in related technologies. Specifically, the signal processing circuit is configured to read a first electrical signal on a touch panel; the touch panel includes a plurality of touch electrodes arranged in an array, each column containing m touch electrodes, and the m touch electrodes are divided into M groups, where m > 1, M ≥ 1, and M and m are both integers; wherein the signal processing circuit includes m analog front-end units, m common-mode level preset units, M first data selectors, and M analog-to-digital converters; the m analog front-end units and the m common-mode level preset units are configured in a one-to-one correspondence; the i-th analog front-end unit is configured to read the first electrical signal output by the i-th touch electrode in each column of touch electrodes in the touch panel in a time-division multiplexing manner, and process the first electrical signal to obtain a set of first differential signals. Signal; i ranges from 1 to m, and i is an integer; a set of first and second transmission gates in a first data selector are configured to process a set of first differential signals output by an analog front-end unit and output a set of second differential signals; different sets of first and second transmission gates process different sets of first differential signals output by analog front-end units; the i-th common-mode level preset unit is configured to process a set of first differential signals output by the i-th analog front-end unit, output a preset common-mode voltage, and configure it to be sent to the analog-to-digital converter; an analog-to-digital converter is configured to convert a set of second differential signals output by a set of first and second transmission gates to generate a digital signal.

[0063] The signal processing circuit provided in this embodiment has m common-mode level preset units, and these m common-mode level preset units correspond one-to-one with the m analog front-end units in the signal processing circuit. Taking one of the common-mode level preset units as an example, the i-th common-mode level preset unit processes a set of first differential signals output by the i-th analog front-end unit, outputs a preset common-mode voltage, and configures it to the analog-to-digital converter (ADC). That is, the output preset common-mode voltage serves as the common-mode voltage of the ADC. When the ADC processes the second differential signal (which can be understood as a set of second differential signals output by the i-th analog front-end unit after processing by the first data selector), the input second differential signal will no longer be in a floating state, but will be set to the preset common-mode voltage. Therefore, the present invention provides a common-mode level preset unit for each analog front-end unit, ensuring that the second differential signal input always changes from the corresponding preset common-mode voltage each time the analog-to-digital converter performs analog-to-digital conversion. This improves the reverse symmetry of the second differential signal, enhances the accuracy of the analog-to-digital converter's analog-to-digital conversion, and thus improves the accuracy of the chip's touch sampling.

[0064] The following is a detailed description of a signal processing circuit provided in an embodiment of this disclosure. The signal processing circuit is configured to read a first electrical signal on a touch panel; the touch panel is provided with m rows and n columns of touch electrodes arranged in an array; for any column of the m rows and n columns of touch electrodes arranged in an array, the touch electrodes are divided into M groups of touch electrodes arranged side by side along the column direction, each group of touch electrodes including N touch electrodes; m > 1, n > 1, and m and n are both integers; M ≥ 1, N > 1, and M and N are both integers.

[0065] Figure 1 This is a schematic diagram of a signal processing circuit provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the signal processing circuit 100 includes m analog front-end units 101, m common-mode level preset units 102, M first data selectors 103, and M analog-to-digital converters 104; the m analog front-end units 101 and the m common-mode level preset units 102 are configured in a one-to-one correspondence. The first data selector 103 can be a multiplexer (MUX). The analog front-end units 101 can be analog front-end circuits (AFE), and the analog-to-digital converters 104 can be analog-to-digital converters (ADC).

[0066] The i-th analog front-end unit 101 is configured to time-division multiplex the first electrical signal output by the i-th touch electrode in each column of touch electrodes in the touch panel, and process the first electrical signal to obtain a set of first differential signals; i ranges from 1 to m, and i is an integer. The set of first differential signals includes a first signal VOP and a second signal VON. The first electrical signal can be obtained based on the charge generated by the touch signal on the touch panel display screen collected by the touch electrodes, and the first electrical signal can be a voltage. For example, the i-th analog front-end unit 101 is configured to read the first electrical signal output by the i-th touch electrode in the first column of touch electrodes for the first time, read the first electrical signal output by the i-th touch electrode in the second column of touch electrodes for the second time, and so on, reading the first electrical signal output by the i-th touch electrode in the n-th column of touch electrodes for the nth time. n can be the number of columns of multiple touch electrodes arranged in an array, n>1, and n is an integer.

[0067] Figure 2 This is a schematic diagram of the structure of the first data selector provided in an embodiment of the present disclosure, as shown below. Figure 2As shown, a set of first transmission gates and second transmission gates in a first data selector 103 are configured to process a set of first differential signals output by an analog front-end unit 101 and output a set of second differential signals; different sets of first transmission gates and second transmission gates process different sets of first differential signals output by analog front-end units 101. The first data selector 103 includes a first data selection unit AMUX_1 and a second data selection unit AMUX_2. The first data selection unit AMUX_1 includes N first transmission gates, and the second data selection unit AMUX_2 includes N second transmission gates, that is, the number of first transmission gates and the number of second transmission gates are the same as the number of touch electrodes in each group of touch electrodes. The N first transmission gates and N second transmission gates are configured one-to-one, and the corresponding first transmission gates and second transmission gates form a group. The first data selection unit AMUX_1 includes N first transmission gates, namely the first first transmission gate amux_11, the second first transmission gate amux_21, ..., the Nth first transmission gate amux_N1; the second data selection unit AMUX_2 includes N second transmission gates, namely the first second transmission gate amux_12, the second second transmission gate amux_22, ..., the Nth second transmission gate amux_N2.

[0068] Figure 3 This is a schematic diagram of the common-mode level preset unit provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the i-th common-mode level preset unit 102 is configured to process a set of first differential signals output by the i-th analog front-end unit 101, output a preset common-mode voltage VCOM, and configure it to the analog-to-digital converter 104. Exemplarily, the common-mode level preset unit 102 includes a first switch 1021 and a second switch 1022, configured to receive a set of first differential signals. The first terminal of the first switch 1021 can be configured to receive a first signal VOP in the first differential signals, and the second switch 1022 can be configured to receive a second signal VON in the first differential signals. The second terminals of the first switch 1021 and the second terminals of the second switch 1022 are electrically connected and serve as the third terminal of the common-mode level preset unit 102. The third terminal of the common-mode level preset unit 102 is configured to output the preset common-mode voltage VCOM.

[0069] An analog-to-digital converter 104 is configured to convert a set of second differential signals output from a set of first and second transmission gates to generate digital signals. The analog-to-digital converter includes multiple digital signal output ports.

[0070] Taking an analog front-end unit 101, a common-mode level preset unit 102, a set of first and second transmission gates in a first data selector 103, and an analog-to-digital converter 104 as an example, a first electrical signal received by the analog front-end unit 101 is processed. Specifically, the analog front-end unit 101 reads the first electrical signal output by a touch electrode and processes the first electrical signal to obtain a set of first differential signals. The common-mode level preset unit 102, which is set corresponding to the analog front-end unit 101, receives the set of first differential signals and outputs a preset common-mode voltage VCOM. The first data selector 103 receives a set of first differential signals from a set of first transmission gates and second transmission gates, and the first and second transmission gates are turned on to output a set of second differential signals. The analog-to-digital converter 104 receives a preset common-mode voltage VCOM and a set of second differential signals output from a set of first transmission gates and second transmission gates in the first data selector 103. At this time, the common-mode voltage of the second differential signal is set to the preset common-mode voltage VCOM. The analog-to-digital converter 104 performs analog-to-digital conversion on the set of second differential signals to generate digital signals.

[0071] In some embodiments, each of the M first data selectors 103 has the same number of first transmission gates and second transmission gates; the M first data selectors 103 have a total of m sets of first transmission gates and second transmission gates, and each first data selector 103 has N sets of first transmission gates and second transmission gates.

[0072] Figure 4 The timing control circuit diagram of the common-mode level preset unit and the first data selector provided in the embodiments of this disclosure is as follows: Figure 4 As shown, the signal processing circuit 100 further includes a first timing control unit 106; while the first and second transmission gates of the i-th group are open, it controls the first switch 1021 and the second switch 1022 in the (i+1)-th common-mode level preset unit 102 to be turned on, and while the first switch 1021 and the second switch 1022 in the (i+1)-th common-mode level preset unit 102 are open, it controls the first and second transmission gates of the (i+1)-th group to be turned on simultaneously. Figure 4 As shown, when the first and second transmission gates of the current group are disconnected (or turned on) in the m-group first and second transmission gates, the first switch 1021 and the second switch 1022 of the common-mode level preset unit 102 corresponding to the next group of first and second transmission gates are simultaneously turned on (or turned off). That is to say, when the analog-to-digital converter 104 processes the second differential signal each time, the second differential signal has been preset to the common-mode voltage VCOM in advance and is no longer in a floating state. This improves the reverse symmetry of the second differential signal, improves the accuracy of analog-to-digital conversion of the analog-to-digital converter 104, and thus improves the accuracy of chip touch sampling.

[0073] In some embodiments, each analog front-end unit 101 includes a charge conversion unit 1011, an integrator 1012, and a sampling unit 1013. Figure 5 A schematic diagram of the simulated front-end unit provided in the embodiments of this disclosure, as shown below. Figure 5 As shown, the analog front-end unit 101 includes a charge conversion unit 1011, an integrator 1012, and a sampling unit 1013. The charge conversion unit 1011 and the integrator 1012 are electrically connected, and the integrator 1012 and the sampling unit 1013 are electrically connected. Specifically, the charge conversion unit 1011 is configured to receive an excitation signal and a first electrical signal, and convert the first electrical signal into a second electrical signal based on the excitation signal and output it. The integrator 1012 is configured to perform analog integration on the second electrical signal and output a third electrical signal. The sampling unit 1013 is configured to process the third electrical signal, generate a set of first differential signals, and output them.

[0074] The first terminal of the charge conversion unit 1011 is the first terminal of the analog front-end unit 101 and is configured to read a first electrical signal. The second terminal of the charge conversion unit 1011 is the second terminal of the analog front-end unit 101 and is configured to receive an excitation signal. The third terminal of the charge conversion unit 1011 is electrically connected to the first terminal of the integrator 1012; the second terminal of the integrator 1012 is electrically connected to the first terminal of the sampling unit 1013.

[0075] In some embodiments, Figure 6 This is a schematic diagram of the circuit structure of the charge conversion unit provided in the embodiments of this disclosure, such as... Figure 6 As shown, V I V represents the first electrical signal, Vex represents the excitation signal, Vcancle represents the fourth electrical signal, and V... CA This represents the second electrical signal, CA represents charge amplifier 111, and Ccancle represents the first capacitor.

[0076] The charge conversion unit 1011 includes a charge amplifier 111, a reset capacitor 112, a reset control switch 113, and a first capacitor 114. The first terminal of the charge amplifier 111 is configured to receive a first electrical signal V. I The second terminal of charge amplifier 111 is configured to receive the excitation signal Vex; the third terminal of charge amplifier 111 is electrically connected to the first terminal of integrator 1012. The first terminal of charge amplifier 111 serves as the first terminal of charge conversion unit 1011, the second terminal of charge amplifier 111 serves as the second terminal of charge conversion unit 1011, and the third terminal of charge amplifier 111 serves as the third terminal of charge conversion unit 1011, outputting a second electrical signal V. CA .

[0077] The first and second terminals of the reset capacitor 112 are electrically connected to the first and third terminals of the charge amplifier 111, respectively; the first and second terminals of the reset control switch 113 are electrically connected to the first and third terminals of the charge amplifier 111, respectively.

[0078] The first terminal of the first capacitor 114 is electrically connected to the first terminal of the charge amplifier 111; the second terminal of the first capacitor 114 is used to receive the fourth electrical signal Vcancle. The fourth electrical signal Vcancle can be an excitation signal Vex. The excitation signal Vex is a series of electrical signals input into the circuit to observe the characteristics of a circuit system. The excitation signal Vex is also called a guard signal, which can effectively eliminate the negative impact of parasitic capacitance on the size of the touch capacitor.

[0079] In some embodiments, Figure 7 This is a schematic diagram of the circuit structure of the sampling unit provided in the embodiments of this disclosure, as shown below. Figure 7 As shown, V INT The third electrical signal is represented by REFL or GND, the first reference signal by REFL, and the second reference signal by REFL or VDD. The first and second reference signals REFL and REFL can be adjusted according to actual needs and circuit structure. The first reference signal REFL is low, and the second reference signal REFL is high. Csp represents the first sampling capacitor 135, Csn represents the second sampling capacitor 136, SHA represents operational amplifier 137, Chp represents the first holding capacitor 138, Chn represents the second holding capacitor 139, VIN represents the signal output from the inverting input terminal (i.e., the first terminal of operational amplifier 137), and VIP represents the signal output from the non-inverting input terminal (i.e., the second terminal of operational amplifier 137). VOP represents the signal output from the non-inverting output terminal (i.e., the third terminal of operational amplifier 137), and VON represents the signal output from the inverting output terminal (i.e., the fourth terminal of operational amplifier 137). VOP and VON form a differential signal.

[0080] The sampling unit 1013 includes a first control switch 131, a second control switch 132, a third control switch 133, a fourth control switch 134, a first sampling capacitor 135, a second sampling capacitor 136, an operational amplifier 137, a first holding capacitor 138, and a second holding capacitor 139. Specifically, the first terminal of the first control switch 131 is configured to receive a first reference signal REFL; the first terminal of the fourth control switch 134 is configured to receive a second reference signal REFD; the first terminals of the second control switch 132 and the third control switch 133 are both electrically connected to the second terminal of the integrator 1012; the second terminals of the first control switch 131 and the second control switch 132 are both electrically connected to the first terminal of the first sampling capacitor 135; and the second terminals of the third control switch 133 and the fourth control switch 134 are both electrically connected to the first terminal of the second sampling capacitor 136. The second terminal of the first sampling capacitor 135 and the first terminal of the first holding capacitor 138 are both electrically connected to the first terminal of the operational amplifier 137; the second terminal of the second sampling capacitor 136 and the first terminal of the second holding capacitor 139 are both electrically connected to the second terminal of the operational amplifier 137. The second terminal of the first holding capacitor 138 is electrically connected to the third terminal of the operational amplifier 137; the second terminal of the second holding capacitor 139 is electrically connected to the fourth terminal of the operational amplifier 137; the third and fourth terminals of the operational amplifier 137 are configured to output a first differential signal.

[0081] Optionally, combined Figure 6 As shown, the voltage value of REFH is the voltage value during the high-level phase of the excitation signal Vex, and the voltage value of REFL is the voltage value during the low-level phase of the excitation signal Vex. Selecting the high-level phase signal of the excitation signal Vex as the second reference signal REFH and the low-level phase signal of the excitation signal Vex as the first reference signal REFH can avoid the influence of other voltages on the sampling unit 1013, such as reducing parasitic capacitance and improving the sensitivity and stability of the sampling unit 1013.

[0082] Optionally, the second reference signal REFH and the first reference signal REFL can be replaced with VDD and GND respectively to adapt to the maximum and minimum values ​​of the excitation signal Vex and to maximize the use of the input voltage range of the excitation signal Vex.

[0083] This disclosure embodiment can utilize a third electrical signal V at a high potential. INT When comparing with the high-potential second reference signal REFH, the second reference signal REFH is replaced with VDD, while when comparing with the low-potential third electrical signal VDD... INT When comparing with the low-level first reference signal REFL, REFL is replaced with GND to further accommodate a wider input voltage range of the sample-and-hold amplifier.

[0084] Optionally, such as Figure 7 As shown, in the first sampling phase, the third electrical signal V INT When the signal is low, the second sampling capacitor 136 and the second holding capacitor 139 are activated according to the third electrical signal V. INT The changes are stored and sampled. The charges at the second terminals of the second sampling capacitor 136 and the first sampling capacitor 135 are different, so that the third and fourth terminals of the operational amplifier 137 can output a set of first differential signals. In the second sampling stage, the third electrical signal V INT When the signal is low, the first sampling capacitor 135 and the first holding capacitor 138 are activated according to the third electrical signal V. INT The changes are stored and sampled. The charges at the second terminals of the first sampling capacitor 135 and the second sampling capacitor 136 are different, so that the third and fourth terminals of the operational amplifier 137 can output a set of first differential signals.

[0085] In some embodiments, the signal processing circuit 100 further includes a control unit 108; the control unit 108 is configured to respond to a third electrical signal V. INT When the signal is at the second level, the first control switch 131 and the third control switch 133 are turned on, while the second control switch 132 and the fourth control switch 134 are turned off; when the third electrical signal V... INT When the first level is active, the second control switch and the fourth control switch 134 are turned on, while the first control switch 131 and the third control switch 133 are turned off. The first level can be high, and the second level can be low.

[0086] Specifically, such as Figure 7 As shown, in the first sampling phase, the third electrical signal V INT When the signal is low, both the first control switch 131 and the third control switch 133 are turned on, while both the second control switch 132 and the fourth control switch 134 are turned off. The third electrical signal V... INT The second sampling capacitor 136 is connected to the positive input terminal of the operational amplifier 137, and VIP is input to the operational amplifier 137. The first reference signal REFL is connected to the inverting input terminal of the operational amplifier 137 via the first sampling capacitor 135, and the VIN signal is input to the operational amplifier 137, making the third electrical signal V, with DC at a low potential, a function of this capacitor. iNT The first reference signal REFL passes through the first sampling capacitor 135, the operational amplifier 137, and the first holding capacitor 138 to output a set of first differential signals VOP and VON.

[0087] like Figure 7 As shown, in the second sampling phase, the third electrical signal V INTWhen the signal is high, both the second control switch 132 and the fourth control switch 134 are turned on, while both the first control switch 131 and the third control switch 133 are turned off, and the third electrical signal V... INT The first sampling capacitor 135 is connected to the inverting input of the sampling amplifier, inputting the VIN signal into the operational amplifier 137. The second reference signal REFH is connected to the inverting input of the operational amplifier 137 via the second sampling capacitor 136, inputting the VIP signal into the operational amplifier 137, thus making the third electrical signal V high at DC potential. INT The second reference signal REFH passes through the second sampling capacitor 136, the operational amplifier 137, and the second holding capacitor 139 to output a set of first differential signals VOP and VON.

[0088] In this embodiment, the capacitor area of ​​the first sampling capacitor 135, the second sampling capacitor 136, the first holding capacitor 138, and the second holding capacitor 139 can be halved. At the same time, since only one operational amplifier 137 is used, the power consumption of the entire sampling unit 1013 can also be reduced by half.

[0089] The embodiments disclosed herein achieve secondary multiplexing of operational amplifier 137 by different combinations of opening and closing control switches within one excitation signal Vex cycle. This includes, but is not limited to, changes in switch combination logic control, all of which are within the scope of protection of this patent.

[0090] In some embodiments, the signal processing circuit 100 further includes a digital front-end unit 105, which is configured to process the digital signal output by the analog-to-digital converter 104 to generate touch instruction information. This touch instruction information represents an instruction to touch the display screen of the touch panel. The digital front-end unit 105 may be a digital front-end circuit (DFE).

[0091] This disclosure also provides a touch panel, which includes a substrate, a plurality of touch electrodes disposed on the substrate and arranged in an array, and a signal processing circuit 100 as described in any of the above embodiments; the touch electrodes are electrically connected to the signal processing circuit 100. The signal processing circuit 100 processes the first electrical signal output by each touch electrode on the touch panel. Each analog front-end unit 101 in the signal processing circuit 100 is provided with a common-mode level preset unit 102, which ensures that the second differential signal input to the analog-to-digital converter 104 changes from the corresponding preset common-mode voltage VCOM each time the analog-to-digital converter 104 performs analog-to-digital conversion, thereby improving the reverse symmetry of the second differential signal and improving the accuracy of the analog-to-digital conversion of the analog-to-digital converter 104, and thus improving the accuracy of chip touch sampling.

[0092] In some embodiments, Figure 8A film layer diagram of a touch panel provided in an embodiment of this disclosure, such as... Figure 8 As shown, the touch panel 200 also includes an interlayer insulating layer 30 disposed on the side of a plurality of touch electrodes 20 arranged in an array away from the substrate, and a plurality of touch signal lines 40 disposed on the side of the interlayer insulating layer 30 away from the substrate.

[0093] Figure 9 This is a schematic diagram of the structure of a touch panel provided in an embodiment of the present disclosure, such as... Figure 9 As shown, a touch signal line 40 is electrically connected to a touch electrode 20 through a connection via 31 penetrating the interlayer insulating layer 30, and different touch signal lines 40 are connected to different touch electrodes 20. For touch electrodes 20 located in the same column, the lines connecting each touch electrode 20 to the connection via 31 electrically connected to the touch signal line 40 are not on the same straight line. Here, the lines connecting the connection vias 31 are not on the same straight line, meaning that the lines connecting the centers of the orthographic projections of the connection vias 31 on the substrate 10 are not on the same straight line. In one possible embodiment, one touch electrode 20 corresponds to multiple connection vias 31 penetrating the interlayer insulating layer 30, and the multiple connection vias 31 are arranged side by side along the column direction. One touch signal line 40 has multiple ends, and each end of the touch signal line 40 is electrically connected to different positions of the touch electrode 20 through different connection vias 31 penetrating the interlayer insulating layer 30.

[0094] In some embodiments, for any column of touch electrodes 20 arranged in an array, the column direction is divided into multiple groups of touch electrodes arranged side by side; the connection lines of the multiple touch electrodes 20 in each group of touch electrodes and the connection vias 31 that are electrically connected to the touch signal lines 40 are located on the same straight line.

[0095] For any column of touch electrodes 20 arranged in an array, taking as an example two groups of touch electrodes arranged side by side along the column direction, such as... Figure 9 As shown, Figure 9 The diagram shows 18 columns and 32 rows of touch electrodes 20 arranged in an array. For the 32 touch electrodes 20 in the same column, the connection lines of the connecting vias 31 that electrically connect each touch electrode 20 in rows 1 to 16 to the touch signal line 40 form a short line A (as shown by the dotted line in the diagram). The connection lines of the connecting vias 31 that electrically connect each touch electrode 20 in rows 17 to 32 to the touch signal line 40 form another short line B. Short lines A and B are not on the same straight line, and both short lines A and B are short diagonal lines formed by the connecting vias 31 that connect the 16 touch electrodes 20 in the same column to the touch signal line 40. They are invisible to the naked eye and can effectively improve the uniformity of the display screen.

[0096] For multiple touch electrodes 20 arranged in an array, when setting more rows of touch electrodes 20, more groups of touch electrodes can also be set up in parallel along the column direction to meet the condition that the short oblique lines formed by the connection vias 31 connecting each touch electrode 20 in a group of touch electrodes to the touch signal line 40 are not visible to the naked eye. For example, for any column of multiple touch electrodes 20 arranged in an array, taking three groups of touch electrodes arranged side by side along the column direction as an example, the connection lines of each touch electrode 20 in the first group of touch electrodes and the connection vias 31 electrically connected to the touch signal lines 40 form a short line A; the connection lines of each touch electrode 20 in the second group of touch electrodes and the connection vias 31 electrically connected to the touch signal lines 40 form a short line B; and the connection lines of each touch electrode 20 in the third group of touch electrodes and the connection vias 31 electrically connected to the touch signal lines 40 form a short line C. Short lines A, B, and C are not on a straight line, which can effectively improve the uniformity of the display screen.

[0097] In some embodiments, for different groups of touch electrode groups, the lines connecting the multiple touch electrodes 20 to the connection vias 31 that electrically connect to the touch signal lines 40 are parallel to each other. For example Figure 9 Short lines A and B are parallel to each other.

[0098] In some embodiments, the number of touch electrodes 20 in each group of touch electrodes is equal. For example... Figure 9 As shown, the first group of touch electrodes includes 16 touch electrodes 20 arranged in sequence, and the second group of touch electrodes includes 16 touch electrodes 20 arranged in sequence. The number of touch electrodes 20 in the two groups of touch electrodes is equal.

[0099] In some embodiments, for any column of touch electrodes 20 arranged in an array, the array is divided into K groups of touch electrodes arranged side by side along the column direction; K is a positive integer greater than 1. Each touch electrode 20 includes a first side 21 and a second side 22 arranged opposite to each other along the row direction; each group of touch electrodes includes N touch electrodes 20, and the N touch electrodes 20 are arranged sequentially along the column direction; N≥1, and N is an integer. For the p-th group of touch electrodes and the (K-p+1)-th group of touch electrodes located in the same column, the distance between the orth projection of the first side 21 of the q-th touch electrode 20 in the p-th group of touch electrodes on the substrate 10 and the orth projection of the connection via 31 corresponding to the q-th touch electrode 20 on the substrate 10 is denoted as the first distance; p takes values ​​from 1 to K, and p is an integer; q takes values ​​from 1 to N, and q is an integer; the distance between the orth projection of the second side 22 of the (N-q+1)-th touch electrode 20 in the (K-p+1)-th group of touch electrodes on the substrate 10 and the orth projection of the connection via 31 corresponding to the (N-q+1)-th touch electrode 20 on the substrate 10 is denoted as the second distance; the first distance and the second distance are equal.

[0100] like Figure 9 As shown, K = 2. When p = 1, K - p + 1 = 2; when p = 2, K - p + 1 = 1. q ranges from 1 to 16. Taking the first and second touch electrode groups in the first column, with p = 1 as an example, the distance between the orthographic projection of the first side 21 of the first touch electrode 20 in the first touch electrode group onto the substrate 10 and the orthographic projection of the corresponding connecting via 31 onto the substrate 10 is denoted as the first distance h1. The distance between the orthographic projection of the second side 22 of the 16th touch electrode 20 in the second touch electrode group onto the substrate 10 and the orthographic projection of the corresponding connecting via 31 onto the substrate 10 is denoted as the second distance h2; the first distance h1 and the second distance h2 are equal.

[0101] In this embodiment, the configuration of the connecting vias 31 determines the unique position of each connecting via 31 in the column direction.

[0102] In some embodiments, each touch electrode 20 includes a third side 23 and a fourth side 24 disposed opposite to each other along the column direction; the distance between the orthographic projection of a connection via 31 electrically connected to a touch signal line 40 on the substrate 10 and the orthographic projection of the fourth side 24 of that touch electrode 20 on the substrate 10 is denoted as the third distance h3. The third distance h3 between the orthographic projections of the connection vias 31 electrically connected to different touch electrodes 20 and touch signal lines 40 on the substrate 10 and the orthographic projections of the fourth side 24 of their respective touch electrodes 20 on the substrate 10 is equal. This arrangement determines the unique position of each connection via 31 corresponding to each touch electrode 20 in the row direction. For example, for any column of touch electrodes 20 arranged in an array, they are divided into K groups of touch electrodes arranged side by side along the column direction; K is a positive integer greater than 1. Each touch electrode 20 includes a third side 23 and a fourth side 24 arranged opposite to each other along the column direction; each group of touch electrodes includes N touch electrodes 20, and the N touch electrodes 20 are arranged sequentially along the column direction; N≥1, and N is rounded down. For any two touch electrode groups located in the same column, the distance between the orthographic projection of the connection via 31 corresponding to the q-th touch electrode 20 in one group of touch electrodes on the substrate 10 and the orthographic projection of the fourth side 24 of the N-th touch electrode 20 on the substrate 10 is denoted as the fourth distance h4; the distance between the orthographic projection of the connection via 31 corresponding to the q-th touch electrode 20 in another group of touch electrodes on the substrate 10 and the orthographic projection of the fourth side 24 of the N-th touch electrode 20 on the substrate 10 is denoted as the fifth distance h5. The fourth distance h4 and the fifth distance h5 are equal.

[0103] In some embodiments, for any column of touch electrodes 20 arranged in an array, the spacing between any two adjacent touch signal lines 40 connecting the touch electrodes 20 is equal.

[0104] In the above embodiments, for the multiple touch electrodes 20 arranged in an array, the routing layout of each touch signal line 40 and the perforation in the interlayer insulating layer 30 will generate parasitic capacitance, and the touch signal lines 40 themselves will also generate parasitic resistance, thereby affecting the sampling of the touch signal. Figure 9 As shown, since the fourth distance h4 and the fifth distance h5 are equal, the difference in length between the touch signal line 40 connected to the q-th touch electrode 20 in one group of touch electrode groups and the touch signal line 40 connected to the q-th touch electrode 20 in the adjacent group of touch electrode groups is the same. This facilitates subsequent compensation for the parasitic resistance of each touch signal line 40, for example... Figure 3 Each touch electrode 20 in the second group of touch electrodes compensates for parasitic resistance based on the difference in length between the touch signal line 40 connected to the qth touch electrode 20 in the first group of touch electrodes and the touch signal line 40 connected to the qth touch electrode 20 in the second group of touch electrodes. This aims to minimize the influence of parasitic capacitance and resistance caused by the wiring layout and improve the accuracy of subsequent signal processing.

[0105] In some embodiments, Figure 10 This is a schematic diagram of a signal processing circuit coupled to a touch electrode, provided in an embodiment of the present disclosure. Figure 10 As shown, the multiple touch electrodes 20 arranged in an array comprise m rows and n columns. The signal processing circuit 100 also includes n second data selectors 109, with each of the n columns of touch electrodes corresponding to one of the n columns of second data selectors 109, where n > 1 and n is an integer. The n second data selectors 109 are also the first second data selector TMUX_1, the second second data selector TMUX_2, ..., the nth second data selector TMUX_n. The second data selector 109 can be a multiplexer (MUX). The second data selector 109 includes m third transmission gates, each of which corresponds to one of the m columns of touch electrodes 20. The m third transmission gates are also the first third transmission gate tmux_1, the second third transmission gate tmux_2, ..., the mth third transmission gate tmux_m.

[0106] like Figure 10As shown, for touch electrodes 20 located in the same column, one touch electrode 20 is electrically connected to a third transmission gate in a second data selector 109 via a touch signal line 40, and different touch electrodes 20 are electrically connected to different third transmission gates in a second data selector 109 via a touch signal line 40. The i-th third transmission gate in each second data selector 109 is electrically connected to the i-th analog front-end unit 101.

[0107] like Figure 10 As shown, a third transmission gate in a second data selector 109 is configured to read a first electrical signal V output by a touch electrode 20. I And output to the analog front-end unit 101 corresponding to the third transmission gate. First electrical signal V I It can be obtained from the charge generated by the touch signal on the display screen of the touch panel 200 collected by the touch electrode 20. Each third transmission gate in the second data selector 109 is controlled by the same control signal. The third transmission gate in the second data selector 109 can be, but is not limited to, a single Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or multiple transmission gates connected in parallel, or variations in the transmission gate size, etc. For example, the third transmission gate is composed of a PMOS switch and an NMOS switch connected in parallel.

[0108] The i-th analog front-end unit 101 is configured to time-division multiplex the first electrical signal V output by the i-th touch electrode 20 in each column of touch electrodes 20 in the touch panel 200. I and the first electrical signal V I The first differential signal is obtained through processing.

[0109] The i-th analog front-end unit 101 is configured to time-division multiplex the first electrical signal V output by the i-th third transmission gate in each of the second data selectors 109. I and the first electrical signal V I The processing yields a first differential signal. The i-th analog front-end unit 101 is configured to read the first electrical signal V output by the i-th third transmission gate in each second data selector 109 in a time-division multiplexing manner according to the timing control signal. I For example, the first electrical signal V output by the i-th third transmission gate in the first second data selector TMUX_1 is read for the first time. I The second time, the first electrical signal V output by the i-th third transmission gate in the second second data selector TMUX_2 is read. I..., the first electrical signal V output by the i-th third transmission gate in the n-th second data selector TMUX_n is read for the nth time. I The timing control signal can be a signal that controls whether the third transmission gate is turned on or off.

[0110] In some embodiments, the signal processing circuit 100 further includes a second timing control unit 107. The second timing control unit 107 is configured to generate timing control signals to control the m third transmission gates of a selected second data selector to be simultaneously turned on or off. For example, if the second timing control unit 107 determines that the first column of touch electrodes 20 is being scanned at the current time, it controls the m third transmission gates of the first second data selector 109 to be simultaneously turned on; if the second timing control unit 107 determines that the first column of touch electrodes 20 has been scanned and the second column of touch electrodes 20 has started scanning at the current time, it controls the m third transmission gates of the first second data selector 109 to be simultaneously turned off and controls the m third transmission gates of the second second data selector 109 to be simultaneously turned on.

[0111] In some embodiments, such as Figure 8 As shown, the touch panel 200 also includes multiple pixels disposed on the side of the multiple touch electrodes 20 arranged in an array near the substrate 10, and the multiple pixels are located in the light-emitting layer 50; the multiple pixels are divided into multiple pixel groups; the pixels in each pixel group are arranged in an array; the pixel groups are configured one-to-one with the touch electrodes.

[0112] This disclosure also provides a display device including the touch panel of any of the above embodiments. The display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0113] The circuits or sub-circuits described in the embodiments of this disclosure can be implemented in software or hardware. The described circuits or sub-circuits can also be housed in a processor; for example, it can be described as: a processor including: a receiving circuit and a processing circuit, the processing module including a writing sub-circuit and a reading sub-circuit. The names of these circuits or sub-circuits do not necessarily constitute a limitation on the circuit or sub-circuit itself; for example, a receiving circuit can also be described as "receiving video signals".

[0114] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A signal processing circuit configured to read a first electrical signal from a touch panel; the touch panel comprising a plurality of touch electrodes arranged in an array, wherein the number of touch electrodes in each column is m, and the m touch electrodes are divided into M groups, m > 1, M ≥ 1, and M and m are both integers; wherein, The signal processing circuit includes m analog front-end units, m common-mode level preset units, M first data selectors, and M analog-to-digital converters; the m analog front-end units and the m common-mode level preset units are configured in a one-to-one correspondence. The i-th analog front-end unit is configured to read the first electrical signal output by the i-th touch electrode in each column of the touch electrodes in the touch panel in a time-division manner, and process the first electrical signal to obtain a set of first differential signals; i can be 1 to m, and i is an integer; A set of first transmission gates and second transmission gates in one of the first data selectors are configured to process a set of first differential signals output by one of the analog front-end units and output a set of second differential signals. The first and second transmission gates of different groups process different sets of first differential signals output by the analog front-end units; The i-th common-mode level preset unit is configured to process a set of first differential signals output by the i-th analog front-end unit, output a preset common-mode voltage, and configure it to the analog-to-digital converter. One of the analog-to-digital converters is configured to convert a set of second differential signals output from a set of first transmission gates and second transmission gates to generate a digital signal; The common-mode level preset unit includes a first switch and a second switch, wherein the first terminal of the first switch is the first terminal of the common-mode level preset unit, the first terminal of the second switch is the second terminal of the common-mode level preset unit, and is configured to receive a set of the first differential signals; The second terminal of the first switch and the second terminal of the second switch are electrically connected, serving as the third terminal of the common-mode level preset unit, and are configured to output the preset common-mode voltage.

2. The signal processing circuit according to claim 1, wherein, In each of the M first data selectors, the number of one set of first transmission gates and second transmission gates is the same; there are a total of m sets of first transmission gates and second transmission gates in the M first data selectors. The signal processing circuit further includes a first timing control unit; while the first and second transmission gates in the i-th group are disconnected, the first and second switches in the (i+1)-th common-mode level preset unit are turned on, and while the first and second switches in the (i+1)-th common-mode level preset unit are disconnected, the first and second transmission gates in the (i+1)-th group are turned on simultaneously.

3. The signal processing circuit according to claim 1, wherein, Each of the aforementioned analog front-end units includes a charge conversion unit, an integrator, and a sampling unit; The charge conversion unit is configured to receive an excitation signal and a first electrical signal, and convert the first electrical signal into a second electrical signal and output it according to the excitation signal; The integrator is configured to perform analog integration on the second electrical signal and output a third electrical signal; The sampling unit is configured to process the third electrical signal, generate a set of the first differential signals, and output them.

4. The signal processing circuit according to claim 3, wherein, The charge conversion unit includes a charge amplifier, a reset capacitor, a reset control switch, and a first capacitor; The first terminal of the charge amplifier is configured to receive the first electrical signal, and the second terminal of the charge amplifier is configured to receive the excitation signal; the third terminal of the charge amplifier is electrically connected to the first terminal of the integrator. The first and second terminals of the reset capacitor are electrically connected to the first and third terminals of the charge amplifier, respectively; the first and second terminals of the reset control switch are electrically connected to the first and third terminals of the charge amplifier, respectively. The first terminal of the first capacitor is electrically connected to the first terminal of the charge amplifier; the second terminal of the first capacitor is used to receive the fourth electrical signal.

5. The signal processing circuit according to claim 3, wherein, The sampling unit includes a first control switch, a second control switch, a third control switch, a fourth control switch, a first sampling capacitor, a second sampling capacitor, an operational amplifier, a first holding capacitor, and a second holding capacitor; The first terminal of the first control switch is configured to receive a first reference signal; the first segment of the fourth control switch is configured to receive a second reference signal; the first terminals of the second control switch and the third control switch are both electrically connected to the second terminal of the integrator; the second terminals of the first control switch and the second control switch are both electrically connected to the first terminal of the first sampling capacitor; the second terminals of the third control switch and the fourth control switch are both electrically connected to the first terminal of the second sampling capacitor. The second end of the first sampling capacitor and the first end of the first holding capacitor are both electrically connected to the first end of the operational amplifier; the second end of the second sampling capacitor and the first end of the second holding capacitor are both electrically connected to the second end of the operational amplifier. The second end of the first holding capacitor is electrically connected to the third end of the operational amplifier; the second end of the second holding capacitor is electrically connected to the fourth end of the operational amplifier; the third and fourth ends of the operational amplifier are configured to output a first differential signal.

6. The signal processing circuit according to claim 5, wherein, The signal processing circuit further includes a control unit; the control unit is configured to control the first control switch and the third control switch to be turned on, and the second control switch and the fourth control switch to be turned off when the third electrical signal is at the second level; When the third electrical signal is at the first level, the second control switch and the fourth control switch are turned on, while the first control switch and the third control switch are turned off.

7. A touch panel, comprising, for example, a substrate, a plurality of touch electrodes disposed on the substrate and arranged in an array, and a signal processing circuit as claimed in any one of claims 1 to 6; wherein the touch electrodes are electrically connected to the signal processing circuit.

8. The touch panel according to claim 7, wherein, It also includes an interlayer insulating layer disposed on the side of the array of multiple touch electrodes facing away from the substrate, and multiple touch signal lines disposed on the side of the interlayer insulating layer facing away from the substrate. Each of the touch signal lines is electrically connected to a touch electrode through a connection via penetrating the interlayer insulating layer, and different touch signal lines are connected to different touch electrodes; For the touch electrodes located in the same column, the connection lines of the connection vias that electrically connect each touch electrode to the touch signal line are not on the same straight line.

9. The touch panel according to claim 8, wherein, For any column of the multiple touch electrodes arranged in an array, the columns are divided into multiple groups of touch electrodes arranged side by side along the column direction; The connection lines of the multiple touch electrodes in each group of touch electrodes that are electrically connected to the touch signal lines are located on the same straight line.

10. The touch panel according to claim 9, wherein, For different groups of touch electrode groups, the connection lines of the connection vias that electrically connect multiple touch electrodes to the touch signal lines are parallel to each other.

11. The touch panel according to claim 10, wherein, The number of touch electrodes in each group of touch electrodes is equal.

12. The touch panel according to claim 10, wherein, For any column of the multiple touch electrodes arranged in an array, the columns are divided into K groups of touch electrodes arranged side by side along the column direction; K is a positive integer greater than 1. Each of the touch electrodes includes a first side and a second side disposed opposite to each other along the row direction; each group of the touch electrodes includes N touch electrodes, and the N touch electrodes are arranged sequentially along the column direction; N≥1, and N is rounded down; For the touch electrode group p and the touch electrode group K-p+1 located in the same column, where, The distance between the orthographic projection of the first side of the qth touch electrode in the p-th group of touch electrodes on the substrate and the orthographic projection of the connecting via corresponding to the qth touch electrode on the substrate is denoted as the first distance; p takes values ​​from 1 to K, and p is an integer; q takes values ​​from 1 to N, and q is an integer; The distance between the orth projection of the second side of the N-q+1th touch electrode in the K-p+1th touch electrode group on the substrate and the orth projection of the connection via corresponding to the N-q+1th touch electrode on the substrate is denoted as the second distance; The first distance is equal to the second distance.

13. The touch panel according to claim 12, wherein, For any column of the multiple touch electrodes arranged in an array, the spacing between any two adjacent touch signal lines connecting the touch electrodes is equal.

14. The touch panel according to claim 8, wherein, The array of multiple touch electrodes comprises m rows and n columns; the signal processing circuit further comprises n second data selectors, with each of the n columns of touch electrodes corresponding to one of the n columns of second data selectors; each of the second data selectors comprises m third transmission gates, with each of the m third transmission gates corresponding to one of the m columns of touch electrodes; n > 1, and n is an integer; For the touch electrodes located in the same column, one of the touch electrodes is electrically connected to a third transmission gate in a second data selector via a touch signal line, and different touch electrodes are electrically connected to different third transmission gates in a second data selector via a touch signal line. The i-th third transmission gate in each of the second data selectors is electrically connected to the i-th analog front-end unit.

15. The touch panel according to claim 8, wherein, It also includes a plurality of pixels disposed on the side of the array of touch electrodes near the substrate; the plurality of pixels are divided into a plurality of pixel groups; the pixels in each pixel group are arranged in an array; and the pixel groups are configured in a one-to-one correspondence with the touch electrodes.

16. A display device comprising a touch panel as claimed in any one of claims 7 to 15.

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