Response protection monotonic counter, counting method, and storage medium

Abstract

The application relates to the technical field of semiconductors, and discloses a response protection monotonic counter, a counting method and a storage medium, wherein the counter comprises a first storage counting data module, a second storage counting data module and a data recording module; the two storage counting data modules are respectively used for storing the low bits and the high bits of a counting value of the counter, and are both provided with parity check bits, counting mark bits and counting data bits; the application can quickly determine the operation state of the current counter; when abnormal power-off or other conditions cause counting interruption, after power-on reset, data can be written in the data bits of the storage counting data module again through the data of the counting mark bits and the data of the parity check bits; reading errors caused by the inaccuracy of counting due to abnormal power-off during the switching of the two storage blocks are solved; the accuracy and the reliability of the counting data of the monotonic counter are greatly improved; and the application has practical value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a response protection monotonic counter, a counting method and a storage medium. BACKGROUND

[0002] The monotonic counter is a kind of counter that provides a monotonically increasing value, never repeating, and the purpose is to add a never-repeating part to the data sent by the user in the information interaction process to prevent the attacker from stealing the user data and impersonating the user identity, that is, to prevent the replay attack.

[0003] The response protection monotonic counter refers to a counter with a monotonic counting function, which monotonically increases with the change of the counting value after the data is counted in the response protection monotonic counter. Usually, the response protection monotonic counter is combined with the memory to ensure the confidentiality and integrity of the data in the data storage process.

[0004] However, the existing response protection monotonic counter needs to write a data in the high storage block for carry-over and erase the low storage block after the low storage block is full of data, and then continue counting in the low storage block after the carry-over operation is completed. In this process, switching between the two storage blocks is required, and if an abnormal power failure or other abnormal conditions are encountered, the counter will not be able to continue the unfinished counting steps or repeat the data writing operation, which will cause the counting value of the counter to be disordered or even lost, thus it is urgent to solve. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a response protection monotonic counter, a counting method and a storage medium, which can effectively solve the reading error caused by inaccurate counting due to abnormal power failure when switching between two storage blocks, and ensure the reliability and security of the counting value of the monotonic counter.

[0006] The technical problem solved by the present application adopts the following technical solutions:

[0007] The present application provides a response protection monotonic counter, comprising a first storage counting data module, a second storage counting data module and a data recording module, wherein,

[0008] The first storage counting data module and the second storage counting data module are matched with each other and are respectively used to store the low bits and the high bits of the counting value of the counter;

[0009] The first storage counting data module and the second storage counting data module are each provided with a parity check bit, a counting flag bit and a counting data bit, the parity check bit is used to identify whether the data of the corresponding counting data module is successfully written, and the counting flag bit is used to identify the operation state of the counter at present;

[0010] The data recording module is configured to store the count value of the counter in the high bit storage count data module when the counter switches the storage count data module.

[0011] Preferably, the count indication bit is configured by two data bits to distinguish and identify four different operating states of the counter.

[0012] The parity check bit is configured by one data bit to distinguish and identify the parity of the data bit currently written in the count data module.

[0013] Preferably, the four different operating states are:

[0014] The count operation state of the first storage count data module;

[0015] The data recording state of the second storage count data module and the update of the parity check bit;

[0016] The count operation state of the second storage count data module;

[0017] The update of the parity check bit to match the data of the second storage count data module and the erase operation state of the first storage count data module.

[0018] Preferably, the response protection monotonic counter further comprises a logic control circuit module and a plurality of input / output interface modules, wherein,

[0019] The logic control circuit module is configured to issue control instructions to the first storage count data module, the second storage count data module and the data recording module to control the counter to perform corresponding count and read operations;

[0020] The input / output interface module is configured to provide data input and output when counting and reading the count value.

[0021] The present application also provides a counting method of a monotonic counter, which is applied to the response protection monotonic counter as described above, and the counting method comprises:

[0022] Receiving a count instruction and judging the data storage state of the first storage count data module:

[0023] If the first storage count data module is not full of data, performing a program count operation on the first data bit of the first storage count data module which has not been written, and synchronously updating the count indication bit to match the current operating state;

[0024] Otherwise, recording the data of the second storage count data module and updating the parity check bit, and synchronously updating the count indication bit to match the current operating state;

[0025] sequentially performing a program count operation on the first unwritten data bit of the second storage count data module and synchronously updating the count indicator bit to match the current operation state;

[0026] sequentially updating the parity bit of the second storage count data module to match the data stored in the module and performing an erase operation on the first storage count data module and synchronously updating the count indicator bit to match the current operation state.

[0027] Preferably, the counting method further comprises an abnormal interruption recovery step, specifically comprising:

[0028] powering on and reading the count carry flag bit;

[0029] if the count carry flag bit indicates that the counter is in the state of performing a count operation on the first storage count data module, performing a program count operation on the first unwritten data bit of the first storage count data module;

[0030] if the count carry flag bit indicates that the counter is in the state of recording data of the second storage count data module and updating the parity bit, verifying whether the data in the data recording module is consistent with the data recorded in the second storage count data module, if not, recording the count data of the second storage count data module, if yes, updating the parity bit of the second storage count data module and sequentially performing a subsequent carry count operation;

[0031] if the count carry flag bit indicates that the counter is in the state of performing a count operation on the second storage count data module, verifying whether the parity bit of the second storage count data module is consistent with the data bit of the second storage count data module, if not, re-performing a program count operation on the first unwritten data bit of the second storage count data module, otherwise sequentially performing a subsequent carry count operation;

[0032] if the count carry flag bit indicates that the counter is in the state of updating the parity bit to match the data of the second storage count data module and performing an erase operation on the first storage count data module, verifying whether the data bit of the first storage count data module is all 1, if not, performing an erase operation on the first storage count data module, otherwise performing a subsequent low-bit count operation.

[0033] Preferably, before the step of recording data of the second storage count data module and updating the parity bit, the following steps are further performed, specifically comprising:

[0034] judging whether the data bit of the second storage count data module is full, if the data bit of the second storage count data module is full, ending the count operation, otherwise sequentially performing a subsequent carry count operation.

[0035] Preferably, the erasing operation is also synchronously performed on the first storage count data module:

[0036] The data in the data record module is erased.

[0037] The application also provides a chip comprising the circuit structure of the response protection monotonic counter as described above.

[0038] The application also provides a non-transient computer readable storage medium storing computer instructions for causing the computer to perform the steps in the count method as described above.

[0039] Compared with the prior art, the application has the following beneficial effects:

[0040] The response protection monotonic counter provided by the application determines the operation state of the current counter of the storage count data by the data of the count mark bit and the data of the parity check bit arranged in the storage count data module, and through the design of the first storage count data module, the second storage count data module and the data record module, and the matching application of the count method, when the count is interrupted due to abnormal power failure or other conditions, the data can be written again in the data bit of the storage count data module through the data of the count mark bit and the data of the parity check bit after power reset, thereby ensuring the reliability, strictness and integrity of the count value of the counter.

[0041] Other outstanding substantive features and significant progress of the application relative to the prior art are further described in detail in the embodiment part. BRIEF DESCRIPTION OF DRAWINGS

[0042] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings:

[0043] Figure 1 A structure schematic diagram of the monotonic counter provided by Example 1 is shown.

[0044] Figure 2 A flow schematic diagram of the count method of the monotonic counter provided by Example 2 is shown.

[0045] Figure 3 A detailed flow schematic diagram of the count method of the monotonic counter provided by Example 2 is shown. DETAILED DESCRIPTION

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that those skilled in the art may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on substantial differences in function. As used in this specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "comprising but not limited to" or "including but not limited to". The embodiments described in the Detailed Description section are preferred embodiments of the present invention and are not intended to limit the scope of the invention.

[0048] Furthermore, those skilled in the art will recognize that various aspects of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the present invention can be specifically implemented in a combination of hardware and software, collectively referred to herein as a "circuit," "module," or "system." Additionally, in some embodiments, various aspects of the present invention can also be implemented as a computer program product contained in one or more microcontroller-readable media, the microcontroller-readable medium containing microcontroller-readable program code.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a response protection monotonic counter, including a first storage counting data module 120, a second storage counting data module 130, and a data recording module 110. In this embodiment, the counting data in the monotonic counter increases monotonically to ensure the confidentiality and integrity of the read and write data. Since the counting data bit 123 of the first storage counting data module 120 in the monotonic counter can record a limited number of values, when the count value of the first storage counting data module 120 in the monotonic counter 100 reaches the upper limit, a carry operation will be performed to carry over to the second storage counting data module 130 in the monotonic counter 100. The data of the second storage counting data module 130 will be recorded, and then the first storage counting data module 120 will be erased.

[0051] Specifically, in this embodiment, the storage blocks of the first storage counting data module 120 and the second storage counting data module 130 are matched and configured to store the low and high bits of the counter count value, respectively.

[0052] The first storage count data module 120 and the second storage count data module 130 are each provided with a parity check bit 121, a count flag bit 122 and a count data bit 123, wherein the parity check bit 121 is used to identify whether the data of the corresponding count data module is successfully written, and the count flag bit 122 is used to identify the current operation state of the counter;

[0053] The count flag bit 122 in the embodiment is configured by two data bits, which are used to distinguish and identify four different operation states of the counter; the four different operation states in the embodiment are as follows:

[0054] The count operation state of the first storage count data module;

[0055] The data recording and parity check bit updating operation state of the second storage count data module;

[0056] The count operation state of the second storage count data module;

[0057] The parity check bit updating operation state for matching the data of the second storage count data module, and the erase operation state of the first storage count data module;

[0058] The count flag bit 122 and the corresponding operation states of the counter are further explained by taking an example, wherein the data recorded in the count flag bit 122 is used to determine the operation state of the monotonic counter when the monotonic counter is abnormally interrupted, for example, the count flag bit 122 has four data states, the first data state 01 represents that the first storage count data module 120 is not full and can normally perform a programming operation, the second data state 00 represents that the first storage count data module 120 is full, the current data of the second storage count data module 130 is recorded and the parity check bit 121 is updated, the third data state 10 represents that the second storage count data module 130 is programmed once, and the fourth data state 11 represents that the first storage count data module 120 is erased;

[0059] The parity check bit in the embodiment is configured by one data bit, which is used to distinguish and identify the parity of the data bit currently written in the corresponding count data module, and the parity check bit 121 is used to determine whether the second storage count data module 130 successfully counts the data, specifically, in the embodiment, when the first storage count data module 120 is full and the count is transferred to the second storage count data module 130, the parity check bit information is updated once; generally, when the data of the parity check bit is 0, it represents that the data bit currently written in the second storage count data module is an even bit, and when the data of the parity check bit is 1, it represents that the data bit currently written in the second storage count data module is an odd bit, which will not be described here;

[0060] The count data bit data bit 123 is a unit for storing count data, for example, when the storage unit is 0, it means that one data is programmed in, which is not described here;

[0061] The data recording module 110 in this embodiment is configured to store the count value in the high bit storage count data module (the second storage count data module 130) when the counter switches the storage count data module.

[0062] The monotonic counter in this embodiment also includes a logic control circuit module and a plurality of input and output interface modules, wherein,

[0063] The logic control circuit module is configured to issue control instructions to the first storage count data module, the second storage count data module, and the data recording module, to control the counter to perform corresponding counting and reading operations;

[0064] The input and output interface modules are configured to provide data input and output when counting and reading the count value.

[0065] Embodiment 2

[0066] As shown in Figure 2 and 3 The embodiment provides a counting method of a monotonic counter, which is applied to the response protection monotonic counter described in Embodiment 1. In general, the overall process followed by the technical method in this embodiment is as follows:

[0067] When all the data bits 123 of the first storage count data module 120 are full, the count is carried out to the second storage count data module 130, and then all the data of the first storage count data module 120 is erased, and the counting starts from the first data bit 123 again. When all the data bits 124 of the first storage count data module 120 are full again, the count is carried out to the second storage count data module 130, and so on until all the first storage count data module 120 and the second storage count data module 130 are full.

[0068] The counting method in this embodiment includes:

[0069] Receiving a counting instruction, and judging the data storage state of the first storage count data module:

[0070] If the first storage count data module is not full, the programming counting operation is performed on the first data bit of the first storage count data module which has not been written, and the count mark bit is updated synchronously to match the current operation state;

[0071] Otherwise, the data of the second storage count data module is recorded and the parity check bit is updated, and the count mark bit is updated synchronously to match the current operation state;

[0072] sequentially performing a program count operation on the first data bit of the second storage count data module which has not been written, and synchronously updating the count mark bit to match the current operation state;

[0073] sequentially updating the parity bit of the second storage count data module to match the data stored in the module, and performing an erase operation on the first storage count data module, and synchronously updating the count mark bit to match the current operation state.

[0074] The foregoing is the flow of the normal counting method. The counting method in the embodiment further includes an abnormal interruption recovery step. When the answer protection monotonic counter is interrupted abnormally, the storage block in which the counting operation is performed internally can have several situations: the first storage count data module in which the counting is being performed is not full; the first storage count data module in which the counting is being performed is full, but the count has not been carried to the second storage count data module; the count has been carried to the second storage count data module, but the erase of the full first storage count data module has not been started; and the count has been carried to the second storage count data module, and the full first storage count data module is being erased.

[0075] Therefore, the counting method in the embodiment includes an abnormal interruption recovery step according to the above situations, and specifically includes:

[0076] powering on and reading the count carry mark bit;

[0077] if the count carry mark bit indicates that the counter is in the state of performing the counting operation on the first storage count data module, performing a program count operation on the first data bit of the first storage count data module which has not been written;

[0078] if the count carry mark bit indicates that the counter is in the state of recording the data of the second storage count data module and updating the parity bit, verifying whether the data in the data recording module is consistent with the data recorded in the second storage count data module, recording the count data of the second storage count data module if they are not consistent, updating the parity bit of the second storage count data module if they are consistent, and sequentially performing the subsequent carry count operation;

[0079] if the count carry mark bit indicates that the counter is in the state of performing the counting operation on the second storage count data module, verifying whether the parity bit of the second storage count data module is consistent with the data bit of the second storage count data module, performing a program count operation on the first data bit of the second storage count data module which has not been written if they are not consistent, and sequentially performing the subsequent carry count operation if they are consistent;

[0080] If the count carry flag bit indicates that the counter is in the updating parity bit state to match the data of the second storage count data module, and the first storage count data module is in the erasing operation state, then the data bits of the first storage count data module are verified to be all 1s, if not, the first storage count data module is executed to erase operation, otherwise, the subsequent low bit counting operation is executed.

[0081] The above-mentioned steps of recovering the abnormal interruption are further illustrated by examples, Figure 2 is the specific process of recovering the abnormal interruption:

[0082] The detection step S101: it is detected that the monotonic counter has an interruption.

[0083] Specifically, the abnormal interruption of the monotonic counter includes the occurrence of power failure, reset and the like, which causes the monotonic counter 1 to generate an interruption.

[0084] The reading step S102: reading the count mark bit data.

[0085] The judgment step S103: judging the operation state of the counter when the interruption occurs;

[0086] The counting step S104: the counter counts.

[0087] The judgment step S103 in the embodiment can ensure that when the monotonic counter generates an interruption, the data state recorded in the count mark bit 122 is read, for example, it can be agreed that when the data state is 01, it represents that the first storage count data module 120 is not full, and the counter operation will write data in the first storage count data module 120 to count the first storage count data module 120.

[0088] Similarly, for the abnormal interruption, in order to ensure that the read and write operation of the monotonic counter will not be abnormal after the monotonic counter is powered on, the data state recorded in the data mark bit 122 is read, for example, when the data state is 00, it represents that the first storage count data module 120 is full, at this time, only the data in the data recording module 110 is verified whether it is consistent with the data recorded in the second storage count data module 130 when the first storage count data module 120 is full, if not, the data of the second storage count data module 130 when the first storage count data module 120 is full is recorded, if consistent, the parity bit 121 is updated and the next operation is performed.

[0089] Similarly, for the abnormal interruption occurs, to ensure that the monotonic counter power-on, the read-write operation of the monotonic counter will not appear abnormal, read the data state recorded in the data mark bit 122, when the data state is 10, in the embodiment of the state is characterized by the second storage count data module 130 programming count, at this time only need to verify the parity check bit 121 and the second storage count data module 130 into the data bit 123 is consistent, if not consistent then re-programming count of the second storage count data module 130, if consistent then the next step operation.

[0090] Similarly, for the abnormal interruption occurs, to ensure that the monotonic counter power-on, the read-write operation of the monotonic counter will not appear abnormal, read the data state recorded in the data mark bit 122, when the data state is 11, in the embodiment of the state is characterized by the first storage count data module 120 erase, at this time only need to verify the first storage count data module 120 data bit 123 is all 1, if not all 1 then erase operation, if all 1 indicates a switch is completed can continue to write data in the first bit data bit 123 count.

[0091] In order to further clarify the relationship between the steps of abnormal interruption recovery, please refer to Figure 3 , Figure 3is a detailed flowchart of the counting method in this embodiment. First, the counting mark bit 122 is read. If the data state of the counting mark bit 122 is 01, because the result of the first judging step S203 includes two cases of the data bit 123 of the first storage counting data module 120 being full and not full, the steps after the first judging step S203 can also include counting at the first data bit 123 of the first storage counting data module 120 not storing data and the second judging step S205. When the result of the first judging step S203 indicates that the data bit 123 of the first storage counting data module 120 is full, the second judging step S205 is executed to judge whether the data bit 123 of the second storage counting data module 130 is full. If the data bit 123 of the second storage counting data module 130 is full, the counting operation is ended. If the data bit 123 of the second storage counting data module 130 is not full, the next step S206 is performed to record the data of the second storage counting data module 130 into the data recording module 110 and update the data information of the parity check bit 121. Further, the counting step S207 is executed to program and count at the first data bit 123 of the second storage counting data module 130 not storing data. Further, the third judging step S208 is executed to judge whether the counting data of the second storage counting data module 130 matches the information of the parity check bit 121. If the counting data of the second storage counting data module 130 does not match the information of the parity check bit 121, it indicates that the previous counting step S207 is not successful and the first data bit 123 of the second storage counting data module 130 not storing data needs to be programmed and counted again. If the counting data of the second storage counting data module 130 matches the information of the parity check bit 121, the erasing step S209 is executed to erase all the data bits 123 of the first storage counting data module 120. Further, the fourth judging step S210 is executed to check whether the data bits 123 of the first storage counting data module 120 are all 1. If the condition is not satisfied, the erasing step S209 is executed again. If the condition is satisfied, the next programming and counting of the first storage counting data module 120 can be performed. The above steps are repeated.

[0092] For example Figure 3As shown, for the abnormal interruption, to ensure that the read and write operations of the monotonic counter 100 will not be abnormal after the monotonic counter is powered on, the data state recorded in the data recording module 122 is read, and when the data state is 01, it indicates that the first storage counting data module 120 being counted is not full, the first judging step S203 is executed; the counting recording module 122 is read, and when the data state of the counting recording module 122 is 00, it indicates that the first storage counting data module 120 being counted is full, but the count has not been incremented to the second storage counting data module 130, the recording data step S206 is executed; the counting recording module 122 is read, and when the data state of the counting recording module 122 is 10, it indicates that the count has been incremented to the second storage counting data module 130, but the erasing of the full first storage counting data module 120 has not been started, the third judging step S208 is executed; the counting recording module 122 is read, and when the data state of the counting recording module 122 is 11, it indicates that the count has been incremented to the second storage counting data module 130, and the full first storage counting data module 120 is being erased, the fourth judging step S210 is executed.

[0093] In the embodiment, before recording the data of the second storage counting data module and updating the parity bit, the following steps are further executed, which specifically include:

[0094] It is judged whether the data bit of the second storage counting data module is full, and if the data bit of the second storage counting data module is full, the counting operation is ended, otherwise, the subsequent counting operation is executed.

[0095] In the embodiment, when the erasing operation is executed on the first storage counting data module, the following steps are further executed synchronously:

[0096] The data in the data recording module is erased.

[0097] Embodiment 3

[0098] The embodiment provides a chip, which comprises the circuit structure of the response protection monotonic counter as described in Embodiment 1.

[0099] Embodiment 4

[0100] The embodiment provides a non-transient computer readable storage medium storing computer instructions, the computer instructions being used for causing the computer to execute the steps of the counting method as described in Embodiment 2.

[0101] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0102] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A response-protected monotonic counter, characterized by It comprises a first storage count data module, a second storage count data module and a data record module, wherein, The first storage count data module and the second storage count data module are arranged in a matched manner and are used for storing the low bits and the high bits of the count value of the counter respectively; The first storage count data module and the second storage count data module are provided with a parity check bit, a count flag bit and a count data bit, the parity check bit is used for identifying whether the data of the count data module is successfully written, and the count flag bit is used for identifying the current operation state of the counter; The data record module is configured to store the count value in the high bit storage count data module when the counter switches the storage count data module; The count flag bit is configured by two data bits and is used for distinguishing and identifying four different operation states of the counter; The parity check bit is configured by one data bit and is used for distinguishing and identifying the parity of the data bit currently written in the count data module; The four different operation states are: The count operation state of the first storage count data module; The operation state of recording the data of the second storage count data module and updating the parity check bit; The count operation state of the second storage count data module; The operation state of updating the parity check bit to match the data of the second storage count data module and erasing the first storage count data module.

2. A response-protected monotonic counter according to claim 1, wherein, It further comprises a logic control circuit module and a plurality of input and output interface modules, wherein, The logic control circuit module is configured to send control instructions to the first storage count data module, the second storage count data module and the data record module, and control the counter to perform corresponding count and read operations; The input and output interface modules are configured to provide the input and output of data when counting and reading the count value.

3. A method of counting for a monotonic counter, applied to a response-protected monotonic counter according to any one of claims 1-2, characterized by, The counting method comprises: Receiving a count instruction and judging the data storage state of the first storage count data module: If the first storage count data module is not full of data, performing a programming count operation on the first data bit of the first storage count data module which is not written, and synchronously updating the count flag bit to match the current operation state; Otherwise, recording the data of the second storage count data module and updating the parity check bit, and synchronously updating the count flag bit to match the current operation state; Sequentially performing a programming count operation on the first data bit of the second storage count data module which is not written, and synchronously updating the count flag bit to match the current operation state; Sequentially updating the parity check bit of the second storage count data module to match the data stored in the module, and performing an erasing operation on the first storage count data module, and synchronously updating the count flag bit to match the current operation state.

4. The counting method of a monotonic counter according to claim 3, wherein, The counting method further comprises an abnormal interruption recovery step, which specifically comprises: Powering on and reading the count carry flag bit; If the count carry flag bit identifies that the counter is in the count operation state of the first storage count data module, performing a programming count operation on the first data bit of the first storage count data module which is not written. If the count carry flag indicates that the counter is in the state of recording data of the second storage count data module and updating the parity bit, the data in the data recording module is verified to be consistent with the data recorded in the second storage count data module, if not consistent, the count data recorded in the second storage count data module is recorded, if consistent, the parity bit of the second storage count data module is updated, and the subsequent carry count operation is sequentially performed; If the count carry flag indicates that the counter is in the state of performing count operation on the second storage count data module, the parity bit of the second storage count data module is verified to be consistent with the data bit of the second storage count data module, if not consistent, the programming count operation is performed on the first data bit of the second storage count data module which has not been written, otherwise the subsequent carry count operation is sequentially performed; If the count carry flag indicates that the counter is in the state of updating the parity bit to be consistent with the data of the second storage count data module and performing erase operation on the first storage count data module, the data bit of the first storage count data module is verified to be all 1, if not all 1, the erase operation is performed on the first storage count data module, otherwise the subsequent low bit count operation is performed.

5. The method of claim 3, wherein, Before the step of recording the data of the second storage count data module and updating the parity bit, the following steps are further performed, specifically comprising: If the data bit of the second storage count data module is full, the count operation is ended, otherwise the subsequent carry count operation is sequentially performed.

6. The method of claim 3, wherein, When the erase operation is performed on the first storage count data module, the following steps are further synchronously performed: The data in the data recording module is erased.

7. A chip, characterized by The circuit structure of the response protection monotonic counter.

8. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to make the computer perform the steps in the count method of any one of claims 3-6. The computer instructions are used to make the computer perform the steps in the count method of any one of claims 3-6.

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