Window-based dynamic erasure scheduling method

Abstract

The present invention discloses a window-based dynamic erase scheduling method. The present invention proposes a novel window-based dynamic erase scheduling algorithm. By dynamically scheduling user tasks and erase tasks, the algorithm disclosed by the present invention can reduce the erase conflicts of the FPGA erase module and erase each user task as much as possible in a timely manner. Compared with the current method, the method proposed by the present invention greatly reduces the area and energy consumption of the hardware circuit and improves the reliability of the system. The present invention proposes an erase scheduling algorithm based on negotiation drive and ILP-based optimization drive. By utilizing global conflict information, the algorithm of the present invention can erase more user tasks and improve system reliability. The present invention ensures the reliability of a mixed critical task set system. The present invention proposes a multi-ICAP port allocation algorithm based on DVFS, which can explore the impact of FPGA architecture support on system reliability to further optimize system reliability.

Description

Technical Field

[0001] The present invention relates to a novel window-based dynamic erase scheduling algorithm, which is used to reduce erase conflicts of FPGA erase modules and improve the reliability of SRAM-based FPGAs in high radiation environments. Background Art

[0002] Field Programmable Gate Arrays (FPGAs) based on static RAM (SRAM) are energy-efficient computing platforms for applications such as smart cars. SRAM-based FPGAs have powerful computing capabilities and the flexibility to reconfigure circuits. However, in terms of system reliability, when FPGAs are placed in high-intensity radiation environments such as space, they are susceptible to single-event upsets (SEUs). In this case, due to charged particles hitting the chip, the state of the chip's configuration memory (Configuration Memory) and on-chip memory (BRAM, Flip-flop) may be flipped [1], which may change the hardware's functionality and lead to incorrect operating results.

[0003] There are currently two mainstream methods for ensuring the reliability of FPGA systems. The first uses spatial redundancy, such as triple modular redundancy (TMR) [2,3], dual modular redundancy (DMR) [4], or interconnect redundancy [5], to detect and mitigate errors. Spatial redundancy-based methods achieve high reliability by replicating the user design multiple times. Therefore, spatial redundancy-based methods have high circuit area and energy overhead. Some methods also try to balance reliability and resource overhead by replicating part of the design or strengthening specific design units [6]. Although spatial redundancy-based methods have high reliability, these methods all face the problems of high FPGA circuit area efficiency and area overhead and long mean time to repair faults.

[0004] To address these issues, the second category of approaches improves system reliability by employing schedule-based erasure techniques instead of expensive spatial redundancy techniques [1,7,8]. These approaches attempt to re-erase the configuration memory of each task before executing each user task to ensure hardware correctness before each task is executed. Because they do not use system redundancy, these approaches have much lower area and power consumption overhead. However, when there are many parallel or large tasks, numerous erase requests may occur frequently, causing the system erase port (ICAP) to be busy, thereby reducing system reliability.

[0005] References

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[0009] [4]R.Balasubramanian and K.Sankaralingam.Virtually-aged samplingdmr:Unifying circuit failure prediction and circuit failure detection.In2013 46thAnnual IEEE / ACM International Symposium on Microarchi-tecture(MICRO),pages123–135,2013.

[0010] [5]N.Jing,J.Zhou,J.Jiang,X.Chen,W.He,and Z.Mao.Redundancybasedinterconnect duplication to mitigate soft errors in sram-basedfpgas.In2015IEEE / ACM International Conference on Computer-AidedDesign(ICCAD),pages764–769,2015.

[0011] [6]A.Ramos,R.G.Toral,P.Reviriego,and J.A.Maestro.Analuprotectionmethodology for soft processors on sram-basedfpgas.IEEETransactions on Computers,68(9):1404–1410,2019.

[0012] [7]R.Santos,S.Venkataraman,and A.Kumar,“Dynamically adaptivescrubbing mechanism for improved reliability in reconfigurable embeddedsystems,”in2015 52nd ACM / EDAC / IEEE Design Automation Conference(DAC),June2015,pp.1–6.

[0013] [8] R.Li, H.Yu, W.Jiang, and Y.Ha.Dvfs-based scrubbing scheduling forreliability maximization on parallel tasks in sram-based fpgas.In2020 57thACM / IEEE Design Automation Conference(DAC), pages 1–6, 2020. Summary of the Invention

[0014] The technical problem to be solved by the present invention is that an SRAM-based FPGA is unreliable in a high radiation environment.

[0015] In order to solve the above technical problems, the technical solution of the present invention is to provide a window-based dynamic erasure scheduling method, which is characterized by comprising the following steps:

[0016] Step 1: Generate candidate erase jobs in each erase cycle by using linear integer programming and using the utilization ubound of the ICAP module in the FPGA system to control the scheduling congestion between erase jobs;

[0017] Step 2: Schedule the erase jobs proposed in step 1 while minimizing the erase port conflicts between different erase jobs. A negotiation-driven scheduling heuristic algorithm or an optimization-driven scheduling method based on integer linear programming is used to resolve the erase conflicts. Then:

[0018] The negotiation-driven scheduling heuristic algorithm converts the erasure scheduling into an integer linear programming problem for solution;

[0019] The NDS scheduling algorithm is an iterative algorithm. Each iteration includes the following steps:

[0020] Step 201: Path through the formula cost Calculate the shortest path from the erasure task node to its maximum feasible scheduling interval:

[0021]

[0022] In formula (4): conflict cost Indicates the total number of ICAP ports required by the system during the erasure period of the current erasure operation minus the total number of ICAP ports available in the system; cost Indicates the time interval between the current erase job and the corresponding user job, c n is the congestion degree of time node n, SI is the minimum unit of time discretization, is the maximum feasible scheduling interval of the kth erasure job of the i-th erasure task, SW i is the running time of the i-th erasure task, m is the time node of the current investigation, ξ i is the importance of the i-th user task;

[0023] Step 202: Schedule the erasure job to the first time node passed by the minimum path, and obtain the optimal schedule of the current scheduled job;

[0024] Step 203: Update the congestion degree c of the time node where the erase scheduling job is scheduled n ;

[0025] Step 204: Continue scheduling the remaining erasure jobs until there is no conflict between the erasure tasks or the set maximum number of iterations is reached;

[0026] Step 3: Identify the conflicting erase jobs that cannot be resolved in step 2 and dynamically delete some of them so that the erase job scheduling after legalization is conflict-free. If there are multiple ICAP erase ports in the FPGA system, use the redundant ICAP ports to dynamically assign erase ports to each erase task through graph coloring.

[0027] Step 4: Iteratively optimize the erasure schedule generated in step 3 according to the local optimal scheduling condition, and the erasure schedule finally generated is executed by the erasure module.

[0028] Preferably, the step 1 comprises the following steps:

[0029] Step 101: Adjust the erasure period ST of each user task by solving the integer linear programming problem in the following formula: i :

[0030] Target:

[0031] Where SW i is the erasure time of the erasure task corresponding to the i-th user task, T i is the operating cycle of the i-th user task, ST i is the running period of the erasure task corresponding to the i-th user task, ξ i is the importance of the i-th user task, |SΛ| is the number of erase tasks in the FPGA system, and ubound is the utilization rate of the ICAP module in the FPGA system;

[0032] Step 102: Based on the erase cycle of the generated erase task, a candidate erase job is generated in each erase cycle for scheduling in subsequent steps. If there are multiple ICAP erase ports in the FPGA system, redundant ICAP ports are used to dynamically allocate an erase port to each erase task through a graph coloring method.

[0033] Preferably, in step 2, the ODS scheduling algorithm model is composed of three groups of 0-1 decision variables, X, Y, Z = {x lt ,y lt ,z lt ; l=0,1,…,|SE|-1,t=0,1,2,…,N-1}, where SE is the set of jobs containing all erasure jobs in the schedule, || is the length of this set, and N is the time length of the current scheduling window. When the negotiation-driven scheduling heuristic algorithm is used to resolve erasure conflicts, the start time of each erasure task is obtained by solving the integer programming system composed of the objective function shown in formula (1) and the constraints shown in formula (2), that is, the erasure task scheduling

[0034] Minimize {X,Y,Z} κ1×relialibity+κ2×conflict (1)

[0035] In formula (2): the relialibity function describes the time interval between the erasure task and the user task, The purpose of optimizing system reliability is achieved by minimizing the reliability function, where ∑ t ty lt Describes the start time of each erasure task, SI is the minimum unit of time discretization, slmax l is the maximum feasible scheduling interval for erasing task l; conflict = ∑ t z t , the conflict between erasure tasks is optimized by minimizing the conflict function, where z t is the port conflict at each time node; κ1 and κ2 represent the weights of the two objective functions;

[0036]

[0037] In formula (2), slmin l Indicates the minimum value of the feasible scheduling interval for the erase operation, SW l Indicates the running time required for the erase job.

[0038] Preferably, in step 3, dynamically deleting part of the erasure task includes the following steps:

[0039] Check the congestion of each time node in turn: if the required ICAP ports at the current time point exceed the total ICAP ports of the system, then the current time node is considered an illegal scheduling node, and some erase jobs are deleted to meet the ICAP port number requirement;

[0040] If the congestion degree of the current time node is greater than 0, calculate the probability of each erasure job at the time node being erased and delete the first n erasure jobs, where n is the number of ICAP ports required for the time node minus the total number of ICAP ports available in the system;

[0041] Iterate through each time node of the current scheduling window until all conflicts are resolved.

[0042] Preferably, the deletion probability of each erasure operation is calculated as follows:

[0043]

[0044] Where: represents the probability of deletion of the kth erasure job of the i-th erasure task at the n-th time node; w1, w2, and w3 represent: the time since the i-th user task was last erased, the total number of conflicts between the k-th erasure job and other erasure jobs, and the importance of the kth erasure job of the i-th erasure task, respectively; θ1 and θ2 are user-defined weights. Secondly, if there are multiple ICAP erasure ports in the system, the legalization step can fully utilize these redundant ICAP ports and dynamically assign erasure ports to each erasure task through graph coloring.

[0045] Preferably, in step 3, dynamically allocating an erasure port for each erasure task includes the following steps:

[0046] Step 301: In a scheduling window, all erase jobs in the window are arranged in ascending order according to their start time.

[0047] Step 302: Allocate an ICAP port to each erase operation in sequence according to the order of arrangement. The ICAP port allocation strategy for each erase operation is as follows: if other erase operations at the time node where the erase operation is located have not yet allocated an ICAP port, then randomly select any ICAP port in the FPGA system; if other erase operations at the time node have already allocated an ICAP port, then randomly select an unused ICAP port from the system.

[0048] Preferably, in step 4, iteratively optimizing the erasure schedule generated in step 3 according to the local optimal scheduling condition includes the following steps:

[0049] Step 401: Within a scheduling window, all erasing jobs within the window are arranged in descending order according to their start time;

[0050] Step 402: Optimize two adjacent erasing operations in sequence according to the arrangement order:

[0051] For two adjacent erasure operations, the compact operator is first run. If there is a time gap between the two erasure operations, the erasure operation with the earlier start time is rescheduled to be next to the other erasure operation to eliminate the time gap.

[0052] For two adjacent erasure operations, the swap operator is run. If the erasure times of the two erasure operations are different, the erasure operation with the longer erasure time is swapped with the operation with the shorter erasure time to ensure that the operation with the shorter erasure time is always run later.

[0053] This paper proposes a novel window-based dynamic erase scheduling algorithm. By dynamically scheduling user tasks and erase tasks, the algorithm disclosed in this paper can reduce erase conflicts in the FPGA erase module and erase as many user tasks as possible in a timely manner. Compared with existing methods, the method proposed in this paper significantly reduces the area and energy consumption of the hardware circuit and improves system reliability. Compared with existing technical solutions, the innovation of this invention lies in:

[0054] (1) A negotiation-driven and ILP-based optimization-driven erasure scheduling algorithm is proposed. By utilizing global conflict information, the algorithm of the present invention can erase more user tasks and improve system reliability.

[0055] (2) A dynamic scheduling legalization algorithm based on a logical probability model is proposed to ensure the reliability of mixed critical task set systems.

[0056] (3) A DVFS-based multi-ICAP port allocation algorithm is proposed to explore the impact of FPGA architecture support on system reliability and further optimize system reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is an overall block diagram of the present invention;

[0058] Figure 2 Pseudo code for the negotiation-based erasure scheduling algorithm (NDS);

[0059] Figure 3 Pseudo code for the ICAP port allocation algorithm;

[0060] Figure 4 Pseudocode for the local improvement algorithm for scheduling. DETAILED DESCRIPTION

[0061] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0062] like Figure 1 As shown, the present invention discloses a window-based dynamic erasure scheduling method comprising the following steps:

[0063] Step 1: Erasure job candidate set generation, which proposes candidate erasure jobs. By using linear integer programming, our approach ensures that critical tasks have more candidate erasure jobs. To alleviate scheduling pressure in subsequent steps, we use ICAP utilization constraints in step 1 to control scheduling congestion between erasure jobs, facilitating subsequent erasure job scheduling.

[0064] Step 1 specifically includes the following steps:

[0065] First, we adjust the erasure period ST of each user task by solving the integer linear programming problem in formula (1) i :

[0066] Target:

[0067] In formula (1), SW i is the erasure time of the erasure task corresponding to the i-th user task, T i is the operating cycle of the i-th user task, ST i is the running period of the erasure task corresponding to the i-th user task, ξ i is the importance of the i-th user task, |SΛ| is the number of erase tasks in the FPGA system, and ubound is the utilization rate of the ICAP module in the FPGA system.

[0068] By solving the integer programming problem in equation (1), we obtain the erasure period of each erasure task. By minimizing equation (1), we can obtain that important user tasks have smaller erasure periods, and secondary user tasks have even smaller erasure periods. Note that in equation (1), we also constrain the ICAP utilization (ubound) in the system so that the generated candidate erasure jobs do not exceed the total ICAP utilization of the system, which effectively controls the congestion between the generated erasure jobs. Based on the erasure period of the generated erasure task, we generate candidate erasure jobs in each erasure period for scheduling in subsequent steps.

[0069] Step 2: Resolve erasure job conflicts. In this step, we schedule the erasure jobs proposed in Step 1 while minimizing erasure port conflicts between different erasure jobs. The conflict resolution capability of this step directly impacts the quality of the final erasure schedule. We propose two methods for resolving erasure conflicts: the first is the Neogtiation-Driven Schedule (NDS) heuristic algorithm, which iteratively reduces erasure conflicts based on global conflict information; the second is the Optimization-Driven Schedule (ODS) method based on integer linear programming (ILP), which provides an optimal erasure conflict resolution solution and can estimate the gap between the NDS and the optimal solution. The following describes the ODS and NDS scheduling algorithms in detail.

[0070] (1) ODS scheduling algorithm:

[0071] The ODS scheduling algorithm solves the erasure scheduling problem by converting it into an integer linear programming problem. The ODS scheduling algorithm model consists of three groups of 0-1 decision variables, X, Y, Z = {x lt ,y lt ,z lt ; l = 0, 1, …, |SE|-1, t = 0, 1, 2, …, N-1}, where SE is the set of jobs containing all erase jobs in the schedule, |SE| is the length of this set, and N is the time length of the current scheduling window.

[0072] Minimize {X,Y,z} κ1×relialibity+κ2×conflict (2)

[0073] In formula (2), the reliability function describes the time interval between the erasure task and the user task. By minimizing this function, we achieve the goal of optimizing system reliability. Among them, ∑ t ty lt Describes the start time of each erasure task, SI is the minimum unit of time discretization, slmax l is the maximum feasible scheduling interval for erasing task l; conflict = ∑ t z t , we optimize the conflict between erasure tasks by minimizing the conflict function, where z t is the port conflict at each time node; κ1 and κ2 represent the weights of the two objective functions. By adjusting the weights, we achieve a balance between the two objective functions.

[0074] By optimizing the objective function shown in Equation (2), the ODS scheduling algorithm can simultaneously optimize the system reliability and the conflict between erasure tasks.

[0075] In order to ensure that the ODS scheduling algorithm generates the schedule correctly, we also need to constrain the objective function. The following formula (2) shows the constraints of the system:

[0076]

[0077] Constraint 1 states that each erasure task can only have one start time; Constraint 2 states that the erasure task must be scheduled to a legal scheduling interval, slmin l represents the minimum value of the feasible scheduling interval of the erasure operation; constraints three and five state that each erasure task must run SW continuously l Unit time; Constraint 4 states that the number of ICAP ports used simultaneously at each time node cannot exceed z t , which expresses the congestion of the current time node.

[0078] By solving the integer programming system composed of the objective function shown in formula (2) and the constraints shown in formula (3), we can obtain the start time of each erasure task, that is, the erasure task scheduling.

[0079] (2) NDS scheduling algorithm: The NDS scheduling algorithm approximates the erasure task scheduling problem in an iterative manner. Within a scheduling window, the scheduling time is first discretized, and each time node represents the time period of SI. By recording the congestion at each time node, we can obtain the global erasure task congestion information. Based on the discretized time nodes and the erasure tasks to be scheduled, we first generate a scheduling graph DSSG. The construction method is as follows: First, each erasure task node is connected to the time nodes of its feasible scheduling interval; second, each adjacent time node is connected. Each time node is accompanied by congestion information to help the NDS scheduling algorithm avoid time nodes with high congestion.

[0080] The NDS scheduling algorithm is an iterative algorithm. The specific steps of each iteration are as follows:

[0081] Step 201: Path through the following formula (4) cost Calculate the shortest path from the erasure task node to its maximum feasible scheduling interval:

[0082]

[0083] In formula (4): conflict cost Indicates the total number of ICAP ports required by the system during the erasure period of the current erasure operation minus the total number of ICAP ports available in the system. costIndicates the time interval between the current erase job and the corresponding user job, c n is the congestion degree of time node n, SI is the minimum unit of time discretization, is the maximum feasible scheduling interval of the kth erasure job of the i-th erasure task, SW i is the running time of the i-th erasure task, and m is the time node of the current investigation. It can be observed that path cost We consider both the reliability of the system and the conflicts between erasure tasks, and optimize these two indicators simultaneously by finding the minimum path.

[0084] Step 202: Schedule the erasure job to the first time node passed by the minimum path, and we obtain the optimal schedule of the current scheduled job.

[0085] Step 203: Update the congestion degree c of the time node where the erase scheduling job is scheduled n ,This ensures that the subsequent erasure job can perceive the updated congestion information in time.

[0086] Step 204: Continue scheduling the remaining erasure jobs until there is no conflict between the erasure tasks, or the set maximum number of iterations is reached.

[0087] Figure 2 A specific implementation of the NDS scheduling algorithm in this embodiment is shown: Figure 2 As shown, we first schedule all candidate erasure jobs generated in step 1 sequentially. Each iteration of the erasure scheduling algorithm discards the current schedule and reschedules each erasure job by finding the shortest path in the scheduling graph. The algorithm then updates the congestion information for each time node on the scheduling graph for the next scheduling iteration. The scheduling algorithm terminates when there are no conflicts between erasure jobs or after a fixed number of iteration failures.

[0088] Step 3: Schedule Legalization. First, step 3 identifies the conflicting erasure jobs that cannot be resolved in step 2. By dynamically deleting some erasure tasks, the legalized erasure job scheduling is conflict-free.

[0089] The specific steps for scheduling legalization are as follows:

[0090] Check the congestion of each time node in turn: If the required ICAP ports at the current time point exceed the total ICAP ports of the system, the current time node is considered an illegal scheduling node, and we need to delete some erase jobs to meet the requirement for the number of ICAP ports.

[0091] If the congestion degree of the current time node is greater than 0, we calculate the probability of each erasure job being erased at that time node and delete the first n erasure jobs, where n is the number of ICAP ports required at that time node minus the total number of ICAP ports available in the system.

[0092] Iterate through each time node of the current scheduling window until all conflicts are resolved.

[0093] The calculation method of the deletion probability of each erasure operation is shown in formula (5):

[0094]

[0095] In formula (5): represents the probability of deletion of the kth erasure job of the i-th erasure task at the n-th time node; w1, w2, and w3 represent: the time since the i-th user task was last erased, the total number of conflicts between the k-th erasure job and other erasure jobs, and the importance of the kth erasure job of the i-th erasure task, respectively; θ1 and θ2 are user-defined weights. This calculation method ensures that important tasks are erased more frequently while also preventing starvation scheduling of less important tasks.

[0096] Secondly, if there are multiple ICAP erasure ports in the system, the legalization step can make full use of these redundant ICAP ports and dynamically allocate erasure ports to each erasure task through the graph coloring method. The ICAP port allocation algorithm is as follows:

[0097] In a scheduling window, all erasure jobs in the window are arranged in ascending order according to their start time.

[0098] ICAP ports are allocated to each erasure job in the order they are sorted. The port allocation strategy for each erasure job is as follows: if no port has been allocated to another erasure job at the time of the erasure job, any ICAP port in the system is randomly selected; if an ICAP port has been allocated to another erasure job at the time of the erasure job, an unused ICAP port is randomly selected from the system.

[0099] Since the legal steps of scheduling ensure that the congestion at any time node is 0, using the above-mentioned ICAP port allocation algorithm, we can always assign a legal ICAP port to each erasure job.

[0100] Figure 3 A specific implementation of the ICAP port allocation algorithm in this embodiment is shown: Figure 3As shown, we first sort the scheduled erasure job set according to the ascending order of the start time of each erasure task. The allocation process then starts from the first job in the sorted job set, finds the neighbor nodes that have been assigned ICAPs, and then avoids assigning the same ICAP to the considered erasure job. Here we use a mapping data structure to track ICAP allocation information. Initially, all erasure jobs are annotated as unassigned. After an ICAP is assigned to an erasure job, the mapping data structure will be updated. Since the erasure legalization phase has eliminated potential erasure conflicts at each time node, our ICAP allocation algorithm can always find a legal ICAP allocation strategy for the erasure job. By traversing each erasure task in the erasure job set through the above algorithm, we can obtain the final ICAP allocation.

[0101] Step 4: Schedule local optimization. Due to the heuristic nature of the algorithm in step 2, the erasure schedule generated in step 3 may have some suboptimal schedules. In step 4, we iteratively optimize the erasure schedule generated in step 3 based on the local optimal schedule conditions. Finally, the erasure schedule generated in step 4 will be executed by the erasure module. The algorithm for local optimization of the erasure schedule is as follows:

[0102] In a scheduling window, all erasure jobs in the window are arranged in descending order according to their start time.

[0103] Optimize two adjacent erasure operations sequentially according to the arrangement order.

[0104] For two adjacent erasure operations, the compact operator is first run. If there is a time gap between the two erasure operations, the time gap is eliminated by rescheduling the erasure operation with an earlier start time so that it is adjacent to the other erasure operation.

[0105] For two adjacent erasure operations, the swap operator is run. If the erasure times of the two erasure operations are different, the erasure operation with the longer erasure time is swapped with the operation with the shorter erasure time to ensure that the operation with the shorter erasure time is always run later.

[0106] By reducing the time gap between erasure jobs, we reduce the time interval between erasure jobs and user jobs, making the resulting schedule more reliable.

[0107] Figure 4The diagram illustrates the scheduling local improvement algorithm in this embodiment, which runs in multiple iterations. In each iteration, it finds optimization opportunities for each pair of adjacent erasure jobs from the end of the scheduling window to the beginning of the scheduling window. First, the algorithm checks whether it can legally perform local optimization for each pair of adjacent erasure jobs. The start and end times of each job pair form a local refinement window. Only when the completion time of the window is earlier than the maximum feasible scheduling time of the two cleaning jobs can we legally locally optimize the schedule of the job pair. After checking the legality, we use the compaction (compactoperator) and swap (swap operator) operators to refine the schedule in sequence. After local optimization, we generate the final erasure schedule.

[0108] The above scheme is implemented on an SRAM-based FPGA system. For any system with high reliability requirements, by extracting task information from the system and using the proposed scheduling algorithm, we can generate a high-quality erasure schedule for each user task.

Claims

1. A window-based dynamic erasure scheduling method, characterized in that: The following steps are involved: Step 1: Generate candidate erase jobs in each erase cycle by using linear integer programming and using the utilization ubound of the ICAP module in the FPGA system to control the scheduling congestion between erase jobs; Step 2: Schedule the erase jobs proposed in step 1 while minimizing the erase port conflicts between different erase jobs. The erase conflicts are resolved by using a negotiation-driven scheduling heuristic algorithm or an optimization-driven scheduling method based on integer linear programming: The negotiation-driven scheduling heuristic algorithm converts the erasure scheduling into an integer linear programming problem for solution; The negotiation-driven scheduling heuristic algorithm is an iterative algorithm. Each iteration includes the following steps: Step 201: Use the following path cost Calculate the shortest path from the erasure task node to its maximum feasible scheduling interval: Where: conflict cost Indicates the total number of ICAP ports required by the system during the erasure period of the current erasure operation minus the total number of ICAP ports available in the system. cost Indicates the time interval between the current erase job and the corresponding user job, c n is the congestion degree of time node n, SI is the minimum unit of time discretization, is the maximum feasible scheduling interval of the kth erasure job of the i-th erasure task, SW i is the erasure time of the erasure task corresponding to the i-th user task, m is the time node of the current inspection, ξ i is the importance of the i-th user task; Step 202: Schedule the erasure job to the first time node passed by the minimum path, and obtain the optimal schedule of the current scheduled job; Step 203: Update the congestion degree c of the time node where the erase scheduling job is scheduled n ; Step 204: Continue scheduling the remaining erasure tasks until there is no conflict between the erasure tasks or the set maximum number of iterations is reached; Step 3: Identify the conflicting erase jobs that cannot be resolved in step 2 and dynamically delete some of them so that the erase job scheduling after legalization is conflict-free. If there are multiple ICAP erase ports in the FPGA system, use the redundant ICAP ports to dynamically assign erase ports to each erase task through graph coloring. Step 4: Iteratively optimize the erasure schedule generated in step 3 according to the local optimal scheduling condition. The final generated erasure schedule is executed by the erasure module.

2. A window-based dynamic erasure scheduling method according to claim 1, characterized in that: The step 1 comprises the following steps: Step 101: Adjust the erasure period ST of each user task by solving the integer linear programming problem in the following formula: i : Goal: Minimize Where SW i is the erasure time of the erasure task corresponding to the i-th user task, T i is the operating cycle of the i-th user task, ST i is the running period of the erasure task corresponding to the i-th user task, ξ i is the importance of the i-th user task, |SΛ| is the number of erase tasks in the FPGA system, and ubound is the utilization rate of the ICAP module in the FPGA system; Step 102: Based on the erase cycle of the generated erase task, a candidate erase job is generated in each erase cycle for scheduling in subsequent steps. If there are multiple ICAP erase ports in the FPGA system, redundant ICAP ports are used to dynamically allocate an erase port to each erase task through a graph coloring method.

3. The window-based dynamic erasure scheduling method according to claim 1, wherein: In step 2, the optimization-driven scheduling method model consists of three groups of 0-1 decision variables, X, Y, Z = {x lt ,y lt ,z lt ; l=0,1,…,|SE|-1,t=0,1,2,…,N-1}, where SE is the set of jobs containing all erasure jobs in the schedule, |SE| is the length of this set, and N is the time length of the current scheduling window. When the negotiation-driven scheduling heuristic algorithm is used to resolve erasure conflicts, the start time of each erasure task is obtained by solving the integer programming system composed of the objective function shown in formula (1) and the constraints shown in formula (2), that is, the erasure task scheduling Minimize {X,Y,Z} κ1×relialibity+k2×conflict (1) In formula (1): the relialibity function describes the time interval between the erasure task and the user task, The purpose of optimizing system reliability is achieved by minimizing the reliability function, where ∑ t ty lt Describes the start time of each erasure task, SI is the minimum unit of time discretization, slmax l is the maximum feasible scheduling interval for erasing task l; conflict = ∑ t z t , the conflict between erasure tasks is optimized by minimizing the conflict function, where z t is the port conflict at each time node; k1 and k2 represent the weights of the two objective functions; In formula (2), slmin l Indicates the minimum value of the feasible scheduling interval for the erase operation, SW l Indicates the erasure time of the erasure task.

4. The window-based dynamic erasure scheduling method according to claim 1, wherein: In step 3, dynamically deleting some erasure tasks includes the following steps: Check the congestion of each time node in turn: if the required ICAP ports at the current time point exceed the total ICAP ports of the system, then the current time node is considered an illegal scheduling node, and some erase jobs are deleted to meet the ICAP port number requirement; If the congestion degree of the current time node is greater than 0, calculate the probability of each erasure job at the time node being erased and delete the first n erasure jobs, where n is the number of ICAP ports required for the time node minus the total number of ICAP ports available in the system; Iterate through each time node of the current scheduling window until all conflicts are resolved.

5. The window-based dynamic erasure scheduling method according to claim 4, characterized in that: The deletion probability of each erasure job is calculated as follows: Where: represents the probability of deletion of the kth erasure task of the ith erasure task at the nth time node; w1, w2, and w3 represent: the time since the last erasure of user task i, the total number of conflicts between the kth erasure task and other erasure tasks, and the importance of the ith erasure task, respectively; θ1 and θ2 are user-defined weights; Secondly, if there are multiple ICAP erasure ports in the system, the legalization step can make full use of these redundant ICAP ports and dynamically allocate erasure ports for each erasure task through the graph coloring method.

6. The window-based dynamic erasure scheduling method according to claim 1, wherein: In step 3, dynamically allocating an erasure port to each erasure task includes the following steps: Step 301: In a scheduling window, all erase jobs in the window are arranged in ascending order according to their start time. Step 302: Allocate an ICAP port to each erase operation in sequence according to the order of arrangement. The ICAP port allocation strategy for each erase operation is as follows: if other erase operations at the time node where the erase operation is located have not yet allocated an ICAP port, then randomly select any ICAP port in the FPGA system; if other erase operations at the time node have already allocated an ICAP port, then randomly select an unused ICAP port from the system.

7. The window-based dynamic erasure scheduling method according to claim 1, wherein: In step 4, iteratively optimizing the erasure schedule generated in step 3 according to the local optimal scheduling condition includes the following steps: Step 401: Within a scheduling window, all erasing jobs within the window are arranged in descending order according to their start time; Step 402: Optimize two adjacent erasing operations in sequence according to the arrangement order: For two adjacent erasure operations, the compact operator is first run. If there is a time gap between the two erasure operations, the erasure operation with the earlier start time is rescheduled to be next to the other erasure operation to eliminate the time gap. For two adjacent erasure operations, the swap operator is run. If the erasure times of the two erasure operations are different, the erasure operation with the longer erasure time is swapped with the operation with the shorter erasure time to ensure that the operation with the shorter erasure time is always run later.

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