Integrated LNA PA Integrated Device and Its Preparation Method

Abstract

The present invention discloses an integrated LNA PA integrated device and a preparation method thereof, including: growing a GaN buffer layer, a first GaN channel layer, an InAlN barrier layer, a second GaN channel layer, and an AlGaN barrier layer on a SiC substrate in sequence from bottom to top; forming an "L"-shaped drain region on one side of the device by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer; forming an "I"-shaped source region on the other side of the device by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer; forming drain and source electrodes in the drain region and the source region respectively; growing a passivation layer on the AlGaN barrier layer outside the drain and source regions; forming a "T"-shaped gate region on the passivation layer by etching; and forming a T-shaped gate electrode in the gate region. The present invention can integrate LNA and PA and apply them to a single device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to an integrated LNA PA device and a preparation method thereof. Background Art

[0002] Due to the characteristics of wide bandgap, high voltage resistance, and high mobility of GaN HEMT devices based on the third-generation semiconductor material GaN, they have been widely used in PAs and LNAs in recent years and have been successfully applied in important fields such as 5G base stations, satellite communications, and military industries. Currently, multiple transistors are usually used as PAs and LNAs respectively to form a radio frequency transceiver system.

[0003] However, the use of multiple transistors will lead to high costs, difficult packaging, and poor integration; and as the operating frequency increases, the losses caused by packaging will become more and more serious, and the cost of packaging will also increase significantly. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an integrated LNA PA device and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides an integrated LNA PA preparation method, including:

[0006] Growing a GaN buffer layer, a first GaN channel layer, an InAlN barrier layer, a second GaN channel layer, and an AlGaN barrier layer on a SiC substrate from bottom to top;

[0007] Forming an "L"-shaped drain region on one side of the device by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer;

[0008] Forming an "I"-shaped source region on the other side of the device by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer;

[0009] Evaporating drain metal and source metal in the drain region and the source region respectively to form a drain electrode and a source electrode;

[0010] Growing a passivation layer on the AlGaN barrier layer outside the drain region and the source region;

[0011] Forming a "T"-shaped gate region on the passivation layer by etching;

[0012] Evaporating gate metal in the gate region to form a T-shaped gate electrode.

[0013] In one embodiment of the present invention, on a SiC substrate, a GaN buffer layer, a first GaN channel layer, an InAlN barrier layer, a second GaN channel layer, and an AlGaN barrier layer are grown sequentially from bottom to top, including:

[0014] On the SiC substrate, a GaN buffer layer with a thickness of 1 μm, a first GaN channel layer with a thickness of 10 nm, an InAlN barrier layer with a thickness of 10 nm and an In component of 17%, a second GaN channel layer with a thickness of 10 nm, and an AlGaN barrier layer with a thickness of 10 nm and an Al component of 30% are grown sequentially from bottom to top by using MOCVD technology.

[0015] In one embodiment of the present invention, by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, an "L"-shaped drain region is formed on one side of the device, including:

[0016] A photoresist is applied on the AlGaN barrier layer, and the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer are etched by using Cl-based dry etching technology to form an "I"-shaped drain region on one side of the device;

[0017] The InAlN barrier layer and the first GaN channel layer are continuously etched by using wet etching technology to form an "L"-shaped drain region on one side of the device.

[0018] In one embodiment of the present invention, by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, an "I"-shaped source region is formed on the other side of the device, including:

[0019] A photoresist is applied on the AlGaN barrier layer, and the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer are etched by using Cl-based dry etching technology to form an "I"-shaped source region on the other side of the device.

[0020] In one embodiment of the present invention, drain metal and source metal are respectively evaporated in the drain region and the source region to form a drain electrode and a source electrode, including:

[0021] Ti / Al / Ni / Au drain metal and Ti / Al / Ni / Au source metal are respectively evaporated in the drain region and the source region by using electron beam evaporation technology;

[0022] Under a nitrogen atmosphere, high-temperature rapid annealing is performed under annealing conditions of an annealing temperature of 860 °C and an annealing time of 60 s to form the source electrode and the drain electrode.

[0023] In one embodiment of the present invention, a passivation layer is grown on the AlGaN barrier layer outside the drain region and the source region, including:

[0024] Using PECVD technology, a passivation layer with a thickness of 120 nm is grown on the AlGaN barrier layer outside the drain region and the source region.

[0025] In one embodiment of the present invention, a "T"-shaped gate region is formed on the passivation layer by etching, including:

[0026] Photoresist is applied on the passivation layer, and a "T"-shaped gate region is formed on the passivation layer using F-based dry etching technology.

[0027] In one embodiment of the present invention, gate metal is evaporated in the gate region to form a T-shaped gate electrode, including:

[0028] Using electron beam evaporation technology, Ni / Au gate metal is evaporated in the gate region.

[0029] In one embodiment of the present invention, before growing the passivation layer on the AlGaN barrier layer outside the drain region and the source region, including:

[0030] Active region isolation of the device is achieved by implanting argon ions on both sides of the drain electrode and the source electrode.

[0031] In a second aspect, an embodiment of the present invention provides an integrated LNA PA device, and the integrated LNA PA device is prepared by the steps of the integrated LNA PA integrated preparation method described in any one of the above.

[0032] Advantages of the present invention:

[0033] The integrated LNA PA integrated preparation method proposed by the present invention forms a double-channel GaN HEMT device during the preparation process with the first GaN channel layer and the second GaN channel layer. The distances between the channels of the double-channel GaN HEMT device and the T-shaped gate are different. As the gate voltage increases, the channels are turned on sequentially from bottom to top. Under different bias conditions and with different Pin signal inputs, the opening degrees of the channels are different, and the device can undertake different functions. For example, with a low gate voltage and a small signal input, the double-channel GaN HEMT device can act as an LNA device, and with a high gate voltage and a large signal input, it can meet the requirements of a PA device.

[0034] Meanwhile, in order to achieve a low noise figure for the lower channel, in the present invention, a strongly polarized InAlN barrier layer is grown on the lower channel, i.e., on the first GaN channel layer, which can achieve high mobility and carrier concentration. On the upper channel, i.e., on the second GaN channel layer, a conventional AlGaN barrier layer is grown. And in order to further reduce the noise figure of the lower channel, the present invention uses etching technology to achieve anisotropic selective etching in the drain region to form an "L"-shaped drain region. The design of the "L"-shaped drain region protects the high breakdown voltage of the large source-drain spacing of the upper channel. On the basis of meeting PA applications, the source-drain spacing of the lower channel is shortened, reducing the scattering in the carrier transport process, thereby improving the noise figure.

[0035] It can be seen that the preparation method proposed by the present invention can integrate LNA and PA applications in a single device, reducing costs and greatly improving the integration degree. On the same chip basis, it further solves the problems of radio frequency loss and packaging cost caused by packaging.

[0036] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0037] Figure 1 is a schematic flow chart of an integrated preparation method of an integrated LNA PA provided by an embodiment of the present invention;

[0038] Figure 2 is a schematic structural diagram corresponding to an integrated preparation method of an integrated LNA PA provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic structural diagram of an integrated LNA PA device provided by an embodiment of the present invention.

[0040] Description of the Reference Numerals in the Drawings:

[0041] 1 - SiC substrate; 2 - GaN buffer layer; 3 - First GaN channel layer; 4 - InAlN barrier layer; 5 - Second GaN channel layer; 6 - AlGaN barrier layer; 7 - Photoresist; 8 - Drain electrode; 9 - Source electrode; 10 - Passivation layer; 11 - T-shaped gate electrode. Detailed Embodiments

[0042] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0043] In order to solve the problems of high packaging loss, high packaging cost and large integration difficulty of GaN high electron mobility transistor (HEMT) devices in radio frequency applications, please refer to Figure 1, the present invention proposes an integrated preparation method of a low noise amplifier - power amplifier (LNA - PA) realized by a single device, including the following steps:

[0044] S10. On the SiC substrate 1, grow a GaN buffer layer 2, a first GaN channel layer 3, an InAlN barrier layer 4, a second GaN channel layer 5, and an AlGaN barrier layer 6 in sequence from bottom to top.

[0045] An alternative solution is proposed in an embodiment of the present invention. As Figure 2 (a) shows, on the SiC substrate 1 with a thickness of 0.375 mm, use metal organic chemical vapor deposition (MOCVD) technology to grow a GaN buffer layer 2 with a thickness of 1 μm, a first GaN channel layer 3 with a thickness of 10 nm, an InAlN barrier layer 4 with a thickness of 10 nm and an In component of 17%, a second GaN channel layer 5 with a thickness of 10 nm, and an AlGaN barrier layer 6 with a thickness of 10 nm and an Al component of 30% in sequence from bottom to top.

[0046] S20. By etching the AlGaN barrier layer 6, the second GaN channel layer 5, the InAlN barrier layer 4, and the first GaN channel layer 3, form an "L"-shaped drain region on one side of the device.

[0047] An alternative solution is provided in an embodiment of the present invention. As Figure 2 (b) shows, apply a photoresist 7 on the AlGaN barrier layer 6, use a stepper lithography machine to align the drain marking metal, and use a Cl - based dry etching technology to etch the AlGaN barrier layer 6, the second GaN channel layer 5, the InAlN barrier layer 4, and the first GaN channel layer 3 to form an "I"-shaped drain region on one side of the device, forming sidewalls with better verticality. The specific Cl - based dry etching process conditions are: etch 30 nm using Cl - based etching, the etching gas is BCl3 / Cl2, the flow rate is 20 / 8 sccm, the pressure is 5 mTorr, the ICP power is 50 W, and the RF power is 15 W.

[0048] In Figure 2 (b) the shown "I"-shaped drain region, continue to use a wet etching technology to etch the InAlN barrier layer 4 and the first GaN channel layer 3. As Figure 2As shown in (c), an "L"-shaped drain region is formed on one side of the device. The specific wet etching process can be a wet etching process of TetraMethyl Ammonium Hydroxide (TMAH). The process conditions are as follows: a TMAH solution with a concentration of 10%, an etching temperature of 90 °C, and an etching duration of 10 min until an "L"-shaped drain region as shown in Figure 2 (c) is formed.

[0049] S30. By etching the AlGaN barrier layer 6, the second GaN channel layer 5, the InAlN barrier layer 4, and the first GaN channel layer 3, an "I"-shaped source region is formed on the other side of the device.

[0050] An alternative solution is provided in an embodiment of the present invention. As shown in Figure 2 (d), photoresist 7 is coated on the AlGaN barrier layer 6. Using a step-and-repeat photolithography machine to align with the source-marked metal, the AlGaN barrier layer 6, the second GaN channel layer 5, the InAlN barrier layer 4, and the first GaN channel layer 3 are etched using Cl-based dry etching technology to form an "I"-shaped source region on the other side of the device, forming sidewalls with better perpendicularity. The specific process conditions of the Cl-based dry etching process are as follows: etching 30 nm using Cl-based etching, the etching gas is BCl3 / Cl2, the flow rate is 20 / 8 sccm, the pressure is 5 mTorr, the ICP power is 50 W, and the RF power is 15 W.

[0051] S40. Drain metal and source metal are respectively evaporated in the drain region and the source region to form a drain electrode 8 and a source electrode 9.

[0052] An alternative solution is provided in an embodiment of the present invention. As shown in Figure 2 (e), Ti / Al / Ni / Au drain metal and Ti / Al / Ni / Au source metal are respectively evaporated in the drain region and the source region using electron beam evaporation technology; in a nitrogen atmosphere, high-temperature rapid annealing is performed under annealing conditions of an annealing temperature of 860 °C and an annealing time of 60 s to form a source electrode 9 and a drain electrode 8. Ohmic contacts are respectively formed at the drain electrode 8 and the source electrode 9.

[0053] S50. A passivation layer 10 is grown on the AlGaN barrier layer 6 outside the drain region and the source region.

[0054] An alternative solution is provided in an embodiment of the present invention. Before growing the passivation layer 10 on the AlGaN barrier layer 6 outside the drain region and the source region, it includes: achieving isolation of the active region of the device by implanting argon ions on both sides of the drain electrode 8 and the source electrode 9.

[0055] Normally, mesa isolation is performed before step S20. However, in the embodiments of the present invention, it is selected to perform mesa isolation before growing the passivation layer 10, and by implanting argon ions, the materials on both sides of the drain electrode 8 and the source electrode 9 form a high-resistance state due to the implanted argon ions, so as to achieve isolation of the active region of the device. This isolation method can ensure better isolation performance of the device and will not affect the performance of the device itself.

[0056] The embodiments of the present invention provide an alternative solution. As Figure 2 (f) shows, a passivation layer 10 with a thickness of 120 nm is grown on the AlGaN barrier layer 6 outside the drain region and the source region by using PECVD technology.

[0057] S60: Form a "T"-shaped gate region on the passivation layer 10 by etching.

[0058] The embodiments of the present invention provide an alternative solution. As Figure 2 (g) shows, photoresist 7 is applied on the passivation layer 10, and the step-and-repeat photolithography machine is aligned with the gate metal mark. The "T"-shaped gate region is formed on the passivation layer 10 by using F-based dry etching technology. The specific process conditions of the F-based dry etching process are: CF4 = 25 sccm, O2 = 5 sccm, pressure = 5 mT, upper electrode power = 80 W, and lower electrode power = 10 W.

[0059] S70: Evaporate gate metal in the gate region to form a T-shaped gate electrode 11.

[0060] The embodiments of the present invention provide an alternative solution. As Figure 2 (h) shows, Ni / Au gate metal is evaporated in the gate region by using electron beam evaporation technology to form a T-shaped gate electrode 11.

[0061] In summary, for the integrated LNA PA integrated manufacturing method proposed in the embodiments of the present invention, a double-channel GaN HEMT device is formed by the first GaN channel layer 3 and the second GaN channel layer 5 during the manufacturing process. The distances between the channels of the double-channel GaN HEMT device and the T-shaped gate are different. As the gate voltage increases, the channels are turned on sequentially from bottom to top. Under different bias conditions and with different Pin signal inputs, the opening degrees of the channels are different, and the device can undertake different functions. For example, when a small signal with a low gate voltage is input, the double-channel GaN HEMT device can undertake the function of an LNA device; when a large signal with a high gate voltage is input, it can meet the requirements of a PA device.

[0062] Meanwhile, in order to achieve a low noise figure for the lower channel, in the embodiments of the present invention, a strongly polarized InAlN barrier layer is grown on the lower channel, i.e., on the first GaN channel layer 3, which can achieve high mobility and carrier concentration. On the upper channel, i.e., on the second GaN channel layer 5, a conventional AlGaN barrier layer 6 is grown. And in order to further reduce the noise figure of the lower channel, in the embodiments of the present invention, an anisotropic selective etching is implemented in the drain region through etching technology to form an "L"-shaped drain region. The design of the "L"-shaped drain region protects the high breakdown voltage of the large source-drain spacing of the upper channel. On the basis of meeting the PA application, the source-drain spacing of the lower channel is shortened, the scattering in the carrier transport process is reduced, and thus the noise figure is improved.

[0063] It can be seen that the preparation method proposed in the embodiments of the present invention can integrate the LNA and PA applications in a single device, reduce the cost, greatly improve the integration degree, and further solve the problems of radio frequency loss and packaging cost caused by packaging on the same chip basis.

[0064] In a second aspect, please refer to Figure 3 , the embodiments of the present invention provide an integrated LNA PA device, which is prepared by the steps of the integrated LNA PA integrated preparation method in the first aspect.

[0065] For the embodiments of the device in the second aspect, since it is basically similar to the embodiments of the preparation method in the first aspect, the description is relatively simple. For related parts, refer to the partial description of the embodiments of the preparation method in the first aspect.

[0066] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0067] Although the present invention has been described in conjunction with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases. Certain measures are recited in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0068] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. An integrated preparation method for LNA and PA, characterized in that Including: On the SiC substrate, a GaN buffer layer, a first GaN channel layer, an InAlN barrier layer, a second GaN channel layer, and an AlGaN barrier layer are grown successively from bottom to top; By etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, an "L"-shaped drain region is formed on one side of the device; By etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, an "I"-shaped source region is formed on the other side of the device; In the drain region and the source region, drain metal and source metal are respectively evaporated to form a drain electrode and a source electrode; A passivation layer is grown on the AlGaN barrier layer outside the drain region and the source region; By etching, a "T"-shaped gate region is formed on the passivation layer; Gate metal is evaporated in the gate region to form a T-shaped gate electrode; Among them, by etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, forming an "L"-shaped drain region on one side of the device includes: Photoresist is applied on the AlGaN barrier layer, and the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer are etched using Cl-based dry etching technology to form an "I"-shaped drain region on one side of the device; the InAlN barrier layer and the first GaN channel layer are continuously etched using wet etching technology to form an "L"-shaped drain region on one side of the device.

2. The integrated LNA PA integrated preparation method according to claim 1, characterized in that, On the SiC substrate, growing a GaN buffer layer, a first GaN channel layer, an InAlN barrier layer, a second GaN channel layer, and an AlGaN barrier layer successively from bottom to top includes: On the SiC substrate, a GaN buffer layer with a thickness of 1 μm, a first GaN channel layer with a thickness of 10 nm, an InAlN barrier layer with a thickness of 10 nm and an In component of 17%, a second GaN channel layer with a thickness of 10 nm, and an AlGaN barrier layer with a thickness of 10 nm and an Al component of 30% are grown successively from bottom to top using MOCVD technology.

3. The integrated LNA PA integrated preparation method according to claim 1, wherein By etching the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer, forming an "I"-shaped source region on the other side of the device includes: Photoresist is applied on the AlGaN barrier layer, and the AlGaN barrier layer, the second GaN channel layer, the InAlN barrier layer, and the first GaN channel layer are etched using Cl-based dry etching technology to form an "I"-shaped source region on the other side of the device.

4. The integrated LNA PA integrated preparation method according to claim 1, characterized in that, Evaporating drain metal and source metal in the drain region and the source region respectively to form a drain electrode and a source electrode includes: Using electron beam evaporation technology to evaporate Ti / Al / Ni / Au drain metal and Ti / Al / Ni / Au source metal in the drain region and the source region respectively; Under a nitrogen atmosphere, high-temperature rapid annealing is carried out under annealing conditions of an annealing temperature of 860 °C and an annealing time of 60 s to form source electrodes and drain electrodes.

5. The integrated LNA PA integrated preparation method according to claim 1, characterized in that, A passivation layer is grown on the AlGaN barrier layer outside the drain region and the source region, including: Using PECVD technology, a passivation layer with a thickness of 120 nm is grown on the AlGaN barrier layer outside the drain region and the source region.

6. The integrated LNA PA integrated preparation method according to claim 1, characterized in that, A "T"-shaped gate region is formed on the passivation layer by etching, including: Photoresist is applied on the passivation layer, and a "T"-shaped gate region is formed on the passivation layer using F-based dry etching technology.

7. The integrated LNA PA integrated preparation method according to claim 1, characterized in that, Gate metal is evaporated in the gate region to form a T-shaped gate electrode, including: Using electron beam evaporation technology, Ni / Au gate metal is evaporated in the gate region.

8. The integrated LNA PA integrated preparation method according to claim 1, characterized in that Before growing the passivation layer on the AlGaN barrier layer outside the drain region and the source region, including: Active region isolation of the device is achieved by implanting argon ions on both sides of the drain electrode and the source electrode.

9. An integrated LNA PA device, characterized in that, The integrated LNA PA device is prepared by the steps of the integrated LNA PA integrated preparation method according to any one of claims 1 to 8.

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