A vertical transistor and its manufacturing method

Abstract

This invention discloses a vertical transistor and its manufacturing method, relating to the field of transistor technology. It addresses the technical problem of insufficient gate control capability in existing vertical transistor structures. The solution includes: a source, a drain, a channel, a first gate stack, and a second gate stack; the channel contacts the source and the drain respectively; the channel includes a first annular structure formed between the source and the drain; the first gate stack is located at least within the channel and contacts the inner surface of the channel; the second gate stack includes a second annular structure surrounding the circumference of the channel; the first and second gate stacks are used to be subjected to a reverse control voltage to jointly control the channel. This invention can improve the gate control capability of vertical transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor technology, and in particular to a vertical transistor and a manufacturing method. BACKGROUND

[0002] The structure of the vertical transistor has the characteristics of small footprint and easy integration in the vertical direction. By using this structure, the integration density of the transistor can be maximized. However, with the evolution of the process, the vertical structure transistor will also face problems such as insufficient gate control capability. How to further improve the gate control capability has become a problem that needs to be solved by those skilled in the art. SUMMARY

[0003] The purpose of the present application is to provide a vertical transistor to solve the problem of insufficient gate control capability of the existing structure of the vertical transistor.

[0004] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0005] In one aspect, the present application provides a vertical transistor, comprising: a source electrode, a drain electrode, a channel, a first gate stack and a second gate stack.

[0006] The channel is in contact with the source electrode and the drain electrode, respectively; the channel comprises a first annular structure formed between the source electrode and the drain electrode; the first gate stack is located at least in the channel and in contact with the inner surface of the channel; the second gate stack comprises a second annular structure surrounding the channel in the circumferential direction; the first gate stack and the second gate stack are used to be applied with opposite control voltages to jointly control the channel.

[0007] The vertical transistor has the following beneficial effects: compared with the prior art, the present application adds a gate stack, which has a first gate stack and a second gate stack, the first gate stack is located in the channel, and the second gate stack is located outside the channel. By applying opposite control voltages to the first gate stack and the second gate stack, two electric fields are formed, and under the superposition of the two electric fields, the inner side or the outer side of the channel forms an inversion layer to control the opening and closing of the channel. Compared with the prior art, the present application can form a stronger superimposed electric field, expand the area that can be regulated in the channel, thereby increasing the carrier concentration in the channel, and further increasing the on-state current and improving the control ability of the gate. Because the control voltage is shared by the gate dielectric layers of the two gate stacks, each gate dielectric layer is not easy to be broken down. In the prior art, only one gate dielectric layer bears the control voltage, which is easy to be broken down. Therefore, the present application has a stronger gate control ability compared with the vertical transistor of the existing structure.

[0008] In another aspect, the present application provides a manufacturing method of a vertical transistor, comprising: providing a substrate;

[0009] The vertical transistor is formed on the substrate; the vertical transistor includes a source, a drain, a channel, a first gate stack, and a second gate stack; the channel contacts the source and the drain, respectively; the channel includes a first annular structure formed between the source and the drain; the first gate stack is located at least within the channel and contacts the inner surface of the channel; the second gate stack includes a second annular structure surrounding the circumference of the channel; the first gate stack and the second gate stack are used to be subjected to a reverse control voltage to jointly control the channel.

[0010] The manufacturing method of the vertical transistor provided by the present invention has the following beneficial effects: Compared with the prior art, the manufacturing method of the semiconductor device provided by the present invention has the same beneficial effects as the semiconductor device provided by the above-mentioned technical solutions, and will not be repeated here. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 This is a cross-sectional view of a vertical transistor shown in Embodiment 1 of the present invention;

[0013] Figure 2 for Figure 1 Top view;

[0014] Figure 3 This is a schematic diagram of the manufacturing process of Embodiment 1 of the present invention;

[0015] Figure 4 This is a cross-sectional view of the vertical transistor shown in Embodiment 2 of the present invention;

[0016] Figure 5 This is a cross-sectional view of the vertical transistor shown in Embodiment 3 of the present invention;

[0017] Figure 6 This is a cross-sectional view of the vertical transistor shown in Embodiment 4 of the present invention;

[0018] Figure 7 A flowchart of a method for manufacturing a vertical transistor provided by the present invention.

[0019] Figure label:

[0020] 1. First gate; 2. First gate dielectric layer; 3. Channel; 4. Second gate dielectric layer; 5. Second gate; 6. Source; 7. Drain; 8. Isolation portion; 9. Groove; 21. Fourth ring portion; 22. Fourth bottom; 31. First ring structure; 32. First bottom structure; 41. First ring portion; 42. First bottom; 51. Second ring portion; 52. Second bottom; 81. Third ring portion; 82. Third bottom. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] This invention provides a vertical transistor, with reference to... Figure 1 , Figure 2 , Figure 4 , Figure 5 and Figure 6 It includes: source 6, drain 7, channel 3, first gate stack and second gate stack; the first gate stack is formed by stacking the first gate 1 and the first gate dielectric layer 2, and the second gate stack is formed by stacking the second gate 5 and the second gate dielectric layer 4.

[0027] The channel 3 is in contact with the source 6 and the drain 7, respectively. The channel 3 includes a first annular structure 31, which is located at least between the source 6 and the drain 7.

[0028] Reference Figure 1 The first annular structure 31 is located not only between the source electrode 6 and the drain electrode 7, but also has an upwardly extending portion. The source electrode 6 is in contact with the lower surface of the channel 3, and the drain electrode 7 is in contact with the side surface of the channel 3.

[0029] Reference Figure 6 The first annular structure 31 is located not only between the source 6 and the drain 7, but also has upward and downward extending portions. Both the source 6 and the drain 7 are in contact with the side surface of the channel 3.

[0030] Reference Figure 4 and Figure 5 The first annular structure 31 is located only between the source electrode 6 and the drain electrode 7. The source electrode 6 and the drain electrode 7 are in contact with the lower surface and the upper surface of the channel 3, respectively.

[0031] The first gate stack is located at least within the channel 3 and is in contact with the inner surface of the channel 3.

[0032] The second gate stack includes a second annular structure surrounding the channel 3 in the circumferential direction. The second annular structure is a stacked structure formed by the second annular portion 51 of the second gate 5 and the first annular portion 41 of the second gate dielectric layer 4.

[0033] The first gate stack and the second gate stack are used to be subjected to reverse control voltages to jointly control the channel 3.

[0034] The following explanation uses the control of channel 3's opening and closing as an example. (Of course, control of channel 3 is not limited to opening and closing; it can also be controlled by changing the gate control voltage, thereby changing the source-drain current.) Assuming the transistor's threshold voltage is a positive value, a positive voltage can be applied to the first gate 1 (the voltage referred to in this article is the voltage between the gate and source), and a negative voltage can be applied to the second gate 5. Under the superposition of the two electric fields formed by the first gate 1 and the second gate 5, channel 3 forms an inversion layer on one side of the outer surface or one side of the inner surface, thus becoming conductive. The positive voltage applied to the first gate 1 must be less than the transistor's threshold voltage.

[0035] Whether the inversion layer is formed on the inner or outer surface of the channel 3 depends on the contact between the source 6 and the drain 7 and the channel 3. It is sufficient to ensure that both the source 6 and the drain 7 are in contact with the inversion layer when the channel 3 forms the inversion layer.

[0036] See Figure 1 , Figure 5 and Figure 6 When the source electrode 6 is in contact with only the outer surface (outer side and / or outer bottom surface) of the channel 3, the inversion layer can only be formed on one side of the outer surface of the channel 3.

[0037] See Figure 4 When the drain 7 and the source 6 are in contact with the upper and lower surfaces of the channel 3 respectively, an inversion layer can be formed on one side of the outer surface of the channel 3 or on one side of the inner surface of the channel 3.

[0038] Of course, both the source electrode 6 and the drain electrode 7 can also contact the inner surface of the channel 3, but only the channel 3 can form an inversion layer on one side of the inner surface.

[0039] Thus, to form an inversion layer in channel 3, the absolute value of the voltage applied across the first gate dielectric layer 2 in this invention is A, and the absolute value of the voltage applied across the second gate dielectric layer 4 is B. In the prior art, to form an inversion layer in channel 3, a voltage value C needs to be applied, where C must be greater than either A or B. Since there is only one gate dielectric layer, it needs to bear the voltage value C alone. In comparison, the first gate dielectric layer 2 and the second gate dielectric layer 4 of this invention are less prone to breakdown. Thus, while ensuring that the gate dielectric layer is not broken down, the control voltage of the gate can be increased indirectly, expanding the controllable area in the channel, thereby increasing the carrier concentration in the channel, and further increasing the on-state current, enhancing the gate's control over the channel.

[0040] When controlling the opening and closing of channel 3, the voltage of the second gate 5 can be set to a constant value. When opening and closing channel 3, only the voltage of the first gate 1 needs to be adjusted. Since channel 3 opens under the superposition of the electric fields formed by the second gate 5 and the first gate 1, the voltage applied to the first gate 1 is less than the voltage (threshold voltage) required to open the channel in the prior art. In this invention, when the voltage value applied to the first gate 1 is D, channel 3 is opened. This voltage value D is equivalent to the threshold voltage of this vertical transistor. The voltage value D is determined by the actual voltage of the second gate 5 and the characteristics of the channel 3 itself (the characteristics of the channel 3 do not change after it is formed). Thus, in practical use, the voltage of the second gate 5 can be changed as needed to adjust the threshold voltage of the vertical transistor, thereby enabling the first gate 1 to open the vertical transistor within a more reasonable range and avoiding breakdown of the first gate dielectric layer 2 due to the need to apply an unreasonably large voltage.

[0041] The positions of source 6 and drain 7 can be interchanged; when one is the source, the other is the drain, which can be set according to actual needs. For example, the position of source 6 in the diagram can be used to form the drain, and in this case, the position of drain 7 in the diagram can be used to form the source.

[0042] Reference Figure 1 and Figure 5 The source electrode 6 can be in the shape of a columnar structure. In this case, the gate dielectric layer included in the first gate stack is a barrel-shaped gate dielectric layer, that is, the first gate dielectric layer 2 is barrel-shaped. At this time, the first gate dielectric layer 2 includes a fourth ring portion 21 and a fourth bottom portion 22.

[0043] When the first gate dielectric layer 2 is barrel-shaped, the first gate 1 can be a columnar structure, a barrel-shaped structure, or a ring structure.

[0044] When the first gate dielectric layer 2 is barrel-shaped, the channel 3 may only have the first annular structure 31. In this case, the bottom of the first gate dielectric layer 2 is in contact with the upper surface of the source electrode 6.

[0045] When the first gate dielectric layer 2 is barrel-shaped, the channel 3 can have both a first annular structure 31 and a first bottom structure 32, with the first annular structure 31 surrounding the outer periphery of the first bottom structure 32. The first bottom structure 32 is disposed on the upper surface of the source 6, and the outer surface of the first gate dielectric layer 2 is in contact with the inner surface of the channel 3.

[0046] In the most preferred embodiment, both the channel 3 and the first gate dielectric layer 2 are barrel-shaped, and the first gate 1 is columnar or barrel-shaped. This structure allows the first gate 1 to obtain the maximum gate control area, which includes both the outer peripheral area of ​​the first annular structure 31 and the area of ​​the first bottom structure 32. Secondly, when the channel 3 is a barrel-shaped structure, it is relatively easy to form a barrel-shaped first gate dielectric layer 2 inside the channel 3. The gate dielectric layer material is deposited by atomic layer deposition, and the gate dielectric layer material will be adsorbed on the inner surface (inner peripheral surface and inner bottom surface) of the channel 3, directly forming a barrel shape.

[0047] The source electrode 6 can be ring-shaped.

[0048] In this case, the gate included in the first gate stack is a barrel-shaped gate, an annular gate, or a pillar-shaped gate. That is, the first gate 1 can be a barrel-shaped, annular, or pillar-shaped structure.

[0049] The aforementioned vertical transistor may further include an isolation portion 8, which is formed at least between the second gate stack and the channel 3.

[0050] Reference Figure 6 The isolation section 8 may only have a third ring section 81, which is located between the first annular structure 31 of the channel 3 and the first ring section 41 of the second gate dielectric layer 4.

[0051] Reference Figure 1 The isolation section 8 may have only the third ring section 81; or it may have both the third ring section 81 and the third bottom section 82.

[0052] The isolation section also surrounds one of the source and drain electrodes circumferentially; the other of the source and drain electrodes is formed on the isolation section; the channel and the first gate stack are formed within the space enclosed by the isolation section, the source electrode, and the drain electrode.

[0053] For example: refer to Figure 1 The isolation section 8 can also surround the circumference of the source electrode 6, the drain electrode 7 is disposed above the isolation section 8, and the channel 3 is barrel-shaped and disposed in the space enclosed by the isolation section 8, the source electrode 6, and the drain electrode 7. The first gate dielectric layer 2 is disposed inside the channel 3, and the first gate electrode 1 is disposed inside the first gate dielectric layer 2.

[0054] For example, the isolation section 8 can also surround the drain 7 circumferentially, the source 6 is disposed above the isolation section 8, and the channel 3 is disposed in a barrel shape in the space enclosed by the isolation section 8, the source 6, and the drain 7. The first gate dielectric layer 2 is disposed inside the channel 3, and the first gate electrode 1 is disposed inside the first gate dielectric layer 2.

[0055] When the source is above the drain, the source is a ring source and the drain is a cylindrical drain. When the drain is above the source, the drain is a ring drain and the source is a cylindrical source.

[0056] The following describes four specific implementation methods.

[0057] Example 1: Refer to Figure 1 and Figure 2 Both the channel 3 and the first gate dielectric layer 2 are barrel-shaped. The channel 3 includes a first annular structure 31 and a first bottom structure 32, and the first gate dielectric layer 2 includes a fourth annular portion 21 and a fourth bottom portion 22. The first gate dielectric layer 2 is disposed inside the channel 3. The first gate electrode 1 is pillar-shaped and is disposed inside the first gate dielectric layer 2. The drain electrode 7 is annular and surrounds the outer periphery of the channel 3. The source electrode 6 is pillar-shaped and is disposed below the channel 3. An isolation portion 8 is disposed below the drain electrode 7 and includes a third annular portion 81 and a third bottom portion 82. The third annular portion 81 surrounds the lower part of the channel 3 and the outer periphery of the source electrode 6. The third annular portion 81 is used to support the drain electrode 7 and also to isolate the source electrode 6 and the drain electrode 7. The second gate dielectric layer 4 includes a first annular portion 41 and a first bottom portion 42. The first annular portion 41 surrounds the outer periphery of the drain electrode 7 and the upper part of the third annular portion 81, and the first bottom portion 42 is disposed on the third bottom portion 82. The second gate 5 includes a second ring portion 51 and a second bottom portion 52. The second ring portion 51 surrounds the outer periphery of the first ring portion 41, and the second bottom portion 52 is disposed on the first bottom portion 42.

[0058] Example 2: Refer to Figure 4 Both the source electrode 6 and the drain electrode 7 are annular. The channel 3 has only a first annular structure 31. The source electrode 6 and the drain electrode 7 are respectively disposed below and above the channel 3. The upper surface of the source electrode 6 is in contact with the lower surface of the channel 3, and the lower surface of the drain electrode 7 is in contact with the upper surface of the channel 3. The first gate dielectric layer 2 has only a fourth ring portion 21, which is attached to the inner periphery of the channel 3 and the source electrode 6. A first gate electrode 1 is disposed inside the first gate dielectric layer 2, and the first gate electrode 1 is configured as a pillar. The second gate dielectric layer 4 has only a first ring portion 41, and the second gate dielectric layer 4 surrounds the outer periphery of the channel 3 and the source electrode 6. The second gate electrode 5 has only a second ring portion 51, and the second gate electrode 5 surrounds the outer periphery of the second gate dielectric layer 4.

[0059] Example 3: Refer to Figure 5The source electrode 6 is cylindrical, and the drain electrode 7 is annular. The channel 3, the first gate dielectric layer 2, and the first gate electrode 1 are all barrel-shaped. The channel 3 includes a first annular structure 31 and a first bottom structure 32. The first gate dielectric layer 2 includes a fourth annular portion 21 and a fourth bottom portion 22. The first gate dielectric layer 2 is stacked inside the channel 3, and the first gate electrode 1 is stacked inside the first gate dielectric layer 2. The source electrode 6 and the drain electrode 7 are respectively disposed below and above the channel 3. The upper surface of the source electrode 6 is in contact with the lower surface of the channel 3, and the lower surface of the drain electrode 7 is in contact with the upper surface of the channel 3. The second gate dielectric layer 4 only has a first annular portion 41 and surrounds the outer periphery of the channel 3 and the source electrode 6. The second gate electrode 5 only has a second annular portion 51 and surrounds the outer periphery of the second gate dielectric layer 4.

[0060] Example 4: Refer to Figure 6 The source electrode 6 and drain electrode 7 are both annular. The isolation portion 8 has only a third ring portion 81. The source electrode 6 and drain electrode 7 are respectively disposed below and above the isolation portion 8. The upper surface of the source electrode 6 is in contact with the lower surface of the isolation portion 8, and the lower surface of the drain electrode 7 is in contact with the upper surface of the isolation portion 8. The channel 3 has only a first annular structure 31 and is attached to the inner periphery of the source electrode 6, the isolation portion 8, and the drain electrode 7. The first gate dielectric layer 2 has only a fourth ring portion 21 and is attached to the inner periphery of the channel 3. A first gate electrode 1 is disposed in the first gate dielectric layer 2. The first gate electrode 1 is columnar, and the outer peripheral surface of the first gate electrode 1 is in contact with the inner peripheral surface of the first gate dielectric layer 2. The second gate dielectric layer 4 has only a first ring portion 41 and is attached to the outer periphery of the source electrode 6, the isolation portion 8, and the drain electrode 7. The second gate electrode 5 has only a second ring portion 51 and is attached to the outer periphery of the second gate dielectric layer 4.

[0061] The present invention also provides a method for manufacturing a vertical transistor, comprising providing a substrate, forming a vertical transistor on the substrate, the vertical transistor including a source, a drain, a channel, a first gate stack and a second gate stack; the channel being in contact with the source and the drain respectively; the channel including a first annular structure formed between the source and the drain; the first gate stack being located at least within the channel and in contact with the inner surface of the channel; the second gate stack including a second annular structure surrounding the circumference of the channel; the first gate stack and the second gate stack being used to be subjected to a reverse control voltage to jointly control the channel.

[0062] Reference Figure 1 , Figure 3 and Figure 7 Specifically, this section introduces a method for manufacturing a vertical transistor:

[0063] S1, forming a source material layer on the substrate, patterning the source material layer to form a source, the source being a columnar structure.

[0064] The substrate can be made of materials such as silicon (Si) or silicon dioxide (SiO2). A source material is magnetron sputtered onto the substrate to form a source material layer. The source material can be molybdenum (Mo). The source material layer is patterned to form source 6, which is patterned into a columnar structure.

[0065] S2, forming an isolation material layer that covers the upper and side surfaces of the source electrode, as well as the substrate; forming a drain material layer on the isolation material layer to form a stacked structure.

[0066] A magnetron sputtering isolation material layer is then deposited onto the existing structure. The isolation material can be silicon dioxide (SiO2). This isolation material layer covers the upper and side surfaces of the source electrode 6, as well as the substrate. A drain material layer is then formed by magnetron sputtering onto the isolation material layer. The drain material can be molybdenum (Mo). This step forms a source-isolation-drain stacked structure, which can be described in detail below. Figure 3 The first picture in the middle.

[0067] S3, grooves are etched into the stacked structure to expose the upper surface of the source.

[0068] The upper surface of the stacked structure is etched downward to form a groove 9. The groove 9 is aligned downward to the position of the source electrode 6 and penetrates to the source electrode 6, exposing the upper surface of the source electrode 6.

[0069] S4, a channel and a first grid stack are formed sequentially in the groove.

[0070] A channel material, such as indium gallium zinc oxide (IGZO), is atomically deposited within the groove 9 to form a barrel-shaped channel 3. Inside the channel 3, a first gate dielectric layer material, such as aluminum oxide (Al2O3), is atomically deposited to form a barrel-shaped first gate dielectric layer 2. Inside the first gate dielectric layer 2, a first gate material, such as indium tin oxide (ITO), is atomically deposited to form a columnar or barrel-shaped first gate 1. The first gate material can be selected as indium tin oxide (ITO). The first gate dielectric layer 2 and the first gate 1 form a first gate stack.

[0071] S5, etch the outer periphery of the upper part of the stacked structure so that the upper part of the drain material layer and the isolation material layer forms an annular structure with the inner sidewall of the groove as the inner sidewall, and the lower part of the isolation material layer forms an annular truncated structure to form an isolation part and an annular drain.

[0072] The upper surface of the stacked structure is etched downwards to remove the outer periphery of the upper part of the stacked structure, etching the source material layer into a ring shape to form a ring-shaped drain 7. The upper part of the isolation material layer is etched into a ring shape, and the lower part forms a truncated ring structure to form an isolation portion 8, which includes a third ring portion 81 and a third bottom portion 82.

[0073] S6, a second gate stack is formed on the outer periphery of the upper surface of the annular structure, the drain, and the upper part of the isolation section.

[0074] A second gate dielectric layer material is atomically deposited on the upper surface of the third bottom 82, the outer periphery of the upper portion of the isolation portion 8, and the outer periphery of the drain 7 to form a second gate dielectric layer 4. The second gate dielectric layer material can be aluminum oxide (Al2O3). After the second gate dielectric layer 4 is formed, it includes a first ring portion 41 and a first bottom portion 42. A second gate material is deposited on the second gate dielectric layer to form a second gate 5. The second gate 5 includes a second ring portion 51 and a second bottom portion 52. The second gate dielectric layer 4 and the second gate 5 form a second gate stack portion.

[0075] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that layers and regions of the desired shape can be formed by various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely the same as those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. In carrying out the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. Different dependent claims may recite certain measures, but this does not mean that these measures cannot be combined to produce good results.

[0076] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A vertical transistor, characterized by, Comprising: a source electrode, a drain electrode, a channel, an isolation portion, a first gate stack portion, and a second gate stack portion; the channel is in contact with the source electrode and the drain electrode respectively; the channel comprises a first annular structure formed between the source electrode and the drain electrode; the first gate stack portion is at least located in the channel and in contact with an inner surface of the channel; the second gate stack portion comprises a second annular structure surrounding the channel in a circumferential direction; the first gate stack portion and the second gate stack portion are used to be applied with opposite control voltages to jointly control the channel; the isolation portion is at least formed between the second gate stack portion and the channel; the isolation portion also surrounds one of the source electrode and the drain electrode in a circumferential direction; the other of the source electrode and the drain electrode is formed on the isolation portion; the channel and the first gate stack portion are formed in a space surrounded by the isolation portion, the source electrode, and the drain electrode.

2. The vertical transistor of claim 1, wherein In a case where one of the source electrode and the drain electrode located below is a columnar structure, the gate dielectric layer included in the first gate stack portion is a barrel-shaped gate dielectric layer; in a case where one of the source electrode and the drain electrode located below is an annular structure, the gate dielectric layer included in the first gate stack portion is a barrel-shaped gate dielectric layer or an annular gate dielectric layer; and / or, the gate included in the first gate stack portion is a barrel-shaped gate, an annular gate, or a columnar gate; and / or, the material contained in the gate dielectric layer is aluminum oxide; the material contained in the gate is indium tin oxide.

3. The vertical transistor according to claim 1 or 2, characterized in that the source electrode is located above the drain electrode, the source electrode is an annular source electrode, and the drain electrode is a columnar drain electrode; or the drain electrode is located above the source electrode, the drain electrode is an annular drain electrode, and the source electrode is a columnar source electrode.

4. The vertical transistor according to claim 1 or 2, wherein the channel further comprises a first bottom structure; the first annular structure surrounds the first bottom structure in a circumferential direction.

5. The vertical transistor of claim 1, wherein the first gate stack portion is used to be applied with a first control voltage, the second gate stack portion is used to be applied with a second control voltage, the second control voltage is a constant voltage, and the first control voltage is a variable voltage; when the first control voltage changes, the working state of the channel changes.

6. The vertical transistor of claim 1, wherein the material contained in the channel is indium gallium zinc oxide; and / or, the material contained in the source electrode and / or the drain electrode is molybdenum.

7. A method of manufacturing a vertical transistor, characterized by, Comprising: providing a substrate; Forming a vertical transistor on the substrate; the vertical transistor comprises a source, a drain, a channel, an isolation part, a first gate stack part and a second gate stack part; the channel is in contact with the source and the drain respectively; the channel comprises a first annular structure formed between the source and the drain; the first gate stack part is located at least in the channel and in contact with the inner surface of the channel; the second gate stack part comprises a second annular structure which surrounds the channel circumferentially; the first gate stack part and the second gate stack part are used to be applied with reverse control voltage to jointly control the channel; the isolation part is formed at least between the second gate stack part and the channel; the isolation part also surrounds the circumference of one of the source and the drain; the other of the source and the drain is formed on the isolation part; the channel and the first gate stack part are formed in the space surrounded by the isolation part, the source and the drain.

8. The method for manufacturing a vertical transistor according to claim 7, wherein The forming the vertical transistor on the substrate comprises: forming a source material layer on the substrate, patterning the source material layer to form the source, the source being a columnar structure; forming an isolation material layer, the isolation material layer covering the upper surface and the side surface of the source, and the substrate; forming a drain material layer on the isolation material layer, the source, the isolation material layer and the drain material layer forming a laminated structure; etching a groove on the laminated structure to expose the upper surface of the source; forming the channel and the first gate stack part in the groove in sequence; etching the outer periphery of the upper part of the laminated structure to make the upper part of the drain material layer and the isolation material layer form an annular structure with the inner side wall of the groove as the inner side wall, and the lower part of the isolation material layer form a ring table structure to form the isolation part and the annular drain; forming the second gate stack part on the upper surface of the ring table structure, the outer periphery of the drain and the upper part of the isolation part.

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