Stacked transistor, preparation method thereof, device and electronic equipment

Abstract

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming an active structure on a substrate; forming a pseudo gate stack structure on the substrate; the pseudo gate stack structure comprises a first pseudo gate structure surrounding the first active structure, a gate isolation layer and a second pseudo gate structure surrounding the second active structure; forming a first source-drain epitaxy of the first transistor and a second source-drain epitaxy of the second transistor; removing the first pseudo gate structure and the second pseudo gate structure, and forming a through hole penetrating through the gate isolation layer; forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnection through hole in the through hole; the gate interconnection through holes are respectively connected with the first gate metal layer and the second gate metal layer; a first orthographic projection of the gate interconnection via in the first direction is located inside a second orthographic projection of the active structure in the first direction. According to the invention, parasitic capacitance can be reduced.

Description

Technical Field

[0001] This application relates to semiconductor manufacturing technology, and more particularly to a stacked transistor and its fabrication method, device, and electronic device. Background Technology

[0002] With Moore's Law continuously evolving, and beyond the gate-all-around (GAA) technology node, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered one of the key technologies for continuing the miniaturization of integrated circuits. However, how to achieve efficient metal interconnects and reduce parasitic capacitance in stacked transistors remains a problem that needs to be solved. Summary of the Invention

[0003] This application provides a stacked transistor and its fabrication method, device, and electronic device, which can realize gate interconnection inside the active region to reduce parasitic capacitance.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a method for fabricating a stacked transistor, comprising: forming an active structure on a substrate; the active structure including a first active structure and a second active structure stacked sequentially in a first direction; forming a dummy gate stacked structure on the substrate; the dummy gate stacked structure including a first dummy gate structure surrounding the first active structure, a gate isolation layer, and a second dummy gate structure surrounding the second active structure; forming a first source-drain epitaxial layer of the first transistor and a second source-drain epitaxial layer of the second transistor; wherein the second source-drain epitaxial layer is formed after performing a first wafer flip; removing the first dummy gate structure and the second dummy gate structure, and forming a through-hole penetrating the gate isolation layer; forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnect via in the through-hole; the gate interconnect via connecting the first gate metal layer and the second gate metal layer respectively; a first orthographic projection of the gate interconnect via in a first direction located inside the second orthographic projection of the active structure in a first direction; wherein the first gate metal layer is formed after performing a second wafer flip.

[0006] In some possible implementations, forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnect via in a through-hole, includes: filling an insulating material in the first gate region corresponding to the first active structure and the first region of the through-hole to form a first sacrificial layer; the first region being the portion of the through-hole close to the first gate region; filling a conductive material in the second gate region corresponding to the second active structure and the second region of the through-hole to form a second gate metal layer of the second transistor and a first gate interconnect via; the second region being the portion of the through-hole close to the second gate region; performing a second die flip; removing the first sacrificial layer, and filling the second gate region and the second region of the through-hole with conductive material to form a first gate metal layer of the first transistor and a second gate interconnect via; the first gate interconnect via and the second gate interconnect via being connected to form a gate interconnect via.

[0007] In some possible implementations, forming an active structure on a substrate includes: providing a substrate and forming a stacked structure on the substrate; the stacked structure includes a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer stacked in a first direction; etching the stacked structure to form a first active structure and a second active structure; the etched second sacrificial layer is located between the first active structure and the second active structure.

[0008] In some possible implementations, removing the first dummy gate structure and the second dummy gate structure to form a through-hole through the gate isolation layer includes: removing the second dummy gate structure to expose the second gate region; removing the second sacrificial layer between the second gate region and the first gate region to form a through-hole; and removing the first dummy gate structure to expose the first gate region.

[0009] In some possible implementations, forming a first source-drain epitaxial layer of the first transistor and a second source-drain epitaxial layer of the second transistor includes: etching an active structure to form a first source-drain trench and a second source-drain trench; filling the second source-drain trench with an insulating material to form a third sacrificial layer; depositing a dielectric material on the third sacrificial layer to form a source-drain isolation layer; performing source-drain epitaxial growth in the first source-drain trench to form a first source-drain epitaxial layer; performing a first wafer flip and thinning the substrate; removing the third sacrificial layer to expose the second source-drain trench; and performing source-drain epitaxial growth in the second source-drain trench to form a second source-drain epitaxial layer.

[0010] In some possible implementations, forming a dummy gate structure on a substrate includes: depositing a semiconductor material of a predetermined height on the substrate to form a second dummy gate structure; depositing an insulating material on the second dummy gate structure to form a gate isolation layer; and depositing a semiconductor material on the gate isolation layer to form a first dummy gate structure.

[0011] In some possible implementations, the method further includes: forming a second back-channel interconnect layer for the second transistor before the second wafer flipping; and forming a first back-channel interconnect layer for the first transistor after forming the gate interconnect via.

[0012] This application provides a stacked transistor, fabricated using the stacked transistor fabrication method described above. The stacked transistor includes: a first transistor; the first transistor includes a first active structure and a first gate metal layer; a second transistor; the second transistor includes a second active structure and a second gate metal layer; the first transistor and the second transistor are stacked in a first direction; a gate interconnect via; the gate interconnect via is electrically connected to the first gate metal layer and the second gate metal layer respectively; the orthographic projection of the gate interconnect via in the first direction is located inside the orthographic projection of the first active structure in the first direction.

[0013] This application provides a semiconductor device including: a plurality of stacked transistors as described above; wherein the plurality of stacked transistors are electrically connected through a back-end interconnect layer to form a functional circuit.

[0014] This application provides an electronic device, including: a circuit board; a semiconductor device as described above; the semiconductor device is mounted on the circuit board and electrically connected to the circuit board.

[0015] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0016] In the embodiments of this application, by forming gate interconnect vias located inside the active region, the gate extension region that is necessary to reserve space for external vias can be eliminated, resulting in a smaller gate pattern area and thus significantly reducing parasitic capacitance.

[0017] Furthermore, by forming gate interconnect vias located inside the active region, the problem of mutual constraint between the width of the active region and the size of the interlayer interconnect vias in the stacked device can be solved, so that the width of both the gate interconnect vias and the width of the active region can be increased, thereby freeing up the width of the active region, reducing parasitic resistance and improving device performance.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application.

[0021] Figure 2 This is a design layout of stacked transistors in an embodiment of this application.

[0022] Figures 3 to 40 This is a schematic flowchart of a method for fabricating stacked transistors in an embodiment of this application.

[0023] Figure 41 This is a schematic diagram of a stacked transistor structure in an embodiment of this application.

[0024] The reference numerals and names in the figure are as follows:

[0025] 11-First transistor; 111-First active structure; 112-First source / drain epitaxial layer; 113-First interlayer dielectric layer; 114-First gate metal layer; 115-First gate cut-off structure; 116-First source / drain metal; 117-First back-channel interconnect layer; 12-Second transistor; 121-Second active structure; 122-Second source / drain epitaxial layer; 123-Second interlayer dielectric layer; 124-Second gate metal layer; 125-Second gate cut-off structure; 126-Second source / drain metal; 127-Second back-channel interconnect layer; 13-First gate interconnect via; 14-Second gate interconnect via; 21-Substrate; 22-Bottom layer Sacrificial layer; 231-First semiconductor layer; 232-Second semiconductor layer; 24-Second sacrificial layer; 25-Shallow trench isolation layer; 261-First pseudo-gate structure; 262-Second pseudo-gate structure; 27-Gate isolation layer; 28-Sidewall; 29-First gap; 30-Intermediate isolation layer; 311-First inner sidewall; 312-Second inner sidewall; 32-Third sacrificial layer; 33-Source / drain isolation layer; 34-Through hole; 35-Gate dielectric layer; 36-First sacrificial layer; 41-First insulating layer; 42-First carrier wafer; 43-Second insulating layer; 44-Second carrier wafer; 45-First hard mask; 46-Second hard mask. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0030] As Moore's Law advances, transistor dimensions continue to shrink. After reaching the gate-around technology node, further miniaturization within a plane faces physical limits. Stacked transistor technology has garnered significant attention due to its ability to integrate multiple layers of transistors vertically. This technology significantly improves device density and circuit performance within a limited chip area by vertically stacking multiple active layers and constructing independent transistor devices.

[0031] In some embodiments, conventional gate interconnect via technology forms vertical vias outside the active region to achieve gate connection between upper and lower layers. This interconnection method requires an area of ​​the active region in terms of layout, which limits the optimization of nanosheet width and thus affects the improvement of device driving capability; at the same time, because the external via structure is relatively narrow, the gate resistance and parasitic capacitance are relatively large, which limits the switching speed of the circuit.

[0032] To address the aforementioned technical problems, this application provides a method for fabricating stacked transistors, which enables gate interconnection within the active region, significantly reducing parasitic capacitance.

[0033] Figure 1 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application. See also... Figure 1 As shown, the fabrication method of the above-mentioned stacked transistors includes:

[0034] In step 101, an active structure is formed on the substrate. The active structure includes a first active structure and a second active structure stacked sequentially in a first direction.

[0035] In some embodiments, an active structure refers to a semiconductor structure used to carry transistor channel regions.

[0036] In some embodiments, the stacked transistors include a first transistor and a second transistor, and the types of the first transistor and the second transistor may include: gate all around field effect transistor (GAAFET), planar transistor and complementary field effect transistor (CFET), etc.

[0037] In some embodiments, the shape of the active structure (i.e., the first active structure and the second active structure) is related to the type of transistor. When the transistor is a fully all-around gate field-effect transistor, the active structure is a nanosheet structure; when the transistor is a planar transistor, the active structure is a block structure; but when the transistor is a complementary field-effect transistor, the active structure can be a fin structure.

[0038] In one example, where the transistor is a full-around-gate field-effect transistor, the first and second active structures on the substrate are stacks of two semiconductor materials stacked alternately. For example, silicon (Si) and silicon germanium (SiGe) are deposited alternately, wherein silicon germanium is used as a sacrificial layer and is removed during the channel release process, and the active structure after removing silicon germanium presents as a nanosheet structure.

[0039] In some embodiments, the first active structure is located above the second active structure, and the two are stacked vertically in a first direction.

[0040] In some embodiments, the first and second active structures in the stacked transistors are formed in the same etching process, which makes the first and second active structures self-aligned. The first transistor fabricated based on the first active structure and the second transistor fabricated based on the second active structure are also self-aligned, and the active regions of the first and second transistors are also self-aligned.

[0041] In some possible implementations, step 101 may include: providing a substrate and forming a stacked structure on the substrate; the stacked structure includes a first semiconductor layer, a second sacrificial layer and a second semiconductor layer stacked in a first direction; etching the stacked structure to form a first active structure and a second active structure; the etched second sacrificial layer is located between the first active structure and the second active structure.

[0042] In some embodiments, the substrate is the base material used to support subsequent device structures, typically made of silicon (Si), silicon-on-insulator (SOI), or other semiconductor substrates. In the embodiments of this application, the substrate serves as the starting point for the entire transistor structure, providing a support platform for subsequent epitaxial growth, etching, and other processes.

[0043] In one example, taking a fully all-around gate field-effect transistor as an example, a substrate (which can be a silicon substrate) is provided. A layer of SiGe1 is deposited on the substrate to form a bottom sacrificial layer. SiGe and Si are alternately deposited on the bottom sacrificial layer to form a second semiconductor layer. A layer of SiGe1 is deposited on the second semiconductor layer to form a second sacrificial layer; SiGe and Si are then alternately deposited on the second sacrificial layer to form a first semiconductor layer. The bottom sacrificial layer, the second semiconductor layer, the second sacrificial layer, and the first semiconductor layer together form a stacked structure. It should be noted that the difference between SiGe1 and SiGe lies in the different atomic percentages of Ge, which allows for selective etching in subsequent processes.

[0044] In some embodiments, a stacked structure on a substrate is etched, the etched first semiconductor layer forms a first active structure, the etched second semiconductor layer forms a second active structure, and the etched second sacrificial layer is located between the first active structure and the second active structure.

[0045] In step 102, a pseudo-gate stack structure is formed on the substrate. The pseudo-gate stack structure includes a first pseudo-gate structure surrounding the first active structure, a gate isolation layer, and a second pseudo-gate structure surrounding the second active structure.

[0046] Understandably, a pseudo-gate structure is a temporary gate structure formed before the final metal gate is formed, which can be used to support the etching and deposition operations in the subsequent metal gate formation process.

[0047] In some embodiments, the gate region of the stacked transistor is opened by photolithography, wherein the gate region includes a first gate region corresponding to a first active structure and a second gate region corresponding to a second active structure.

[0048] In some embodiments, the gate isolation layer located between the first pseudo-gate structure and the second pseudo-gate structure is an insulating dielectric layer used to electrically isolate the first pseudo-gate structure and the second pseudo-gate structure.

[0049] In some possible implementations, step 102 may include: depositing a semiconductor material of a predetermined height on a substrate to form a second gate structure; depositing an insulating material on the second pseudo-gate structure to form a gate isolation layer; and depositing a semiconductor material on the gate isolation layer to form a first pseudo-gate structure.

[0050] In some embodiments, the semiconductor materials used to prepare the first pseudo-gate structure and the second pseudo-gate structure may include, but are not limited to, polycrystalline silicon, amorphous silicon, etc.

[0051] In some embodiments, the gate isolation layer may be made of silicon dioxide, silicon nitride, or other insulating materials.

[0052] In some embodiments, a semiconductor material is deposited in the second gate region to form a second dummy gate structure; an insulating material is deposited on the second dummy gate structure to form a gate isolation layer; a semiconductor material is deposited on the gate isolation layer (i.e., the first gate region) to form a first dummy gate structure; and an insulating material is then deposited on the surfaces of the dummy gate structure and the active structure to form a sidewall (spacer).

[0053] In some embodiments, a first pseudo-gate structure surrounds a first active structure, a second pseudo-gate structure surrounds a second active structure, and a gate isolation layer surrounds an etched second sacrificial layer. The height of the gate isolation layer is the same as the height of the second sacrificial layer.

[0054] In step 103, a first source-drain epitaxial layer of the first transistor and a second source-drain epitaxial layer of the second transistor are formed. The second source-drain epitaxial layer is formed after the first wafer flipping operation.

[0055] In some embodiments, a first source-drain epitaxial layer is formed based on a first active structure; the wafer is flipped so that the substrate faces upward and the substrate is thinned; and a second source-drain epitaxial layer is formed based on a second active structure.

[0056] In some embodiments, flipping refers to turning the wafer so that the surface that was originally facing down is now facing up.

[0057] In some possible implementations, step 103 may include: etching the active structure to form a first source / drain trench and a second source / drain trench; filling the second source / drain trench with insulating material to form a third sacrificial layer; depositing dielectric material on the third sacrificial layer to form a source / drain isolation layer; performing source / drain epitaxial growth in the first source / drain trench to form a first source / drain epitaxial layer; performing a first wafer flip and thinning the substrate; removing the third sacrificial layer to expose the second source / drain trench; and performing source / drain epitaxial growth in the second source / drain trench to form a second source / drain epitaxial layer.

[0058] In some embodiments, a portion of the active structure is removed by photolithography and etching to form source / drain trenches (i.e., a first source / drain trench and a second source / drain trench). The second source / drain trench is first filled with an insulating material (such as SiO2 or SiN) to form a third sacrificial layer; the third sacrificial layer can be used to support the subsequently fabricated source / drain isolation layer and the first source / drain epitaxial layer.

[0059] In some embodiments, the source-drain isolation layer is used to isolate the first source-drain epitaxial layer and the second source-drain epitaxial layer to prevent short circuits or crosstalk between adjacent source-drain regions.

[0060] It should be noted that in the embodiments of this application, "source and drain" is an abbreviation for "source and / or drain".

[0061] In some embodiments, the source-drain epitaxial growth process involves selectively growing semiconductor materials (such as Si, SiGe, etc.) in specific grooves using methods such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0062] In some embodiments, after forming the first source / drain epitaxial layer, a dielectric material may be deposited to form the first interlayer dielectric (ILD) layer in the first transistor.

[0063] In some embodiments, before performing the first wafer flipping, an insulating material can be deposited on the first interlayer dielectric layer to form a first insulating layer; the first carrier wafer is then bonded to the first insulating layer. Thus, the first insulating layer and the first carrier wafer can protect the devices in the first transistor after wafer flipping, preventing damage to the devices in the first transistor due to external forces.

[0064] In some embodiments, after wafer flipping, the substrate is removed by a thinning process until the third sacrificial layer is exposed; then, the third sacrificial layer is removed to expose the second source / drain trench; and a second source / drain epitaxial layer is formed in the second source / drain trench.

[0065] In step 104, the first pseudo-gate structure and the second pseudo-gate structure are removed, and a through hole is formed through the gate isolation layer.

[0066] In some embodiments, the second dummy gate structure is first removed to expose the first gate region; then, the second sacrificial layer located between the second gate region and the first dummy gate structure is removed; the second sacrificial layer is surrounded by a gate isolation layer and has the same height as the gate isolation layer; the via left after removing the second sacrificial layer penetrates the gate isolation layer, i.e., a through-hole.

[0067] In some possible implementations, step 104 may include: removing the second dummy gate structure to expose the second gate region; removing the second sacrificial layer between the second gate region and the first gate region to form a through-hole; and removing the first dummy gate structure to expose the first gate region.

[0068] In some embodiments, the removal of the second dummy gate structure is performed after part of the process has been completed in the device region of the second transistor. The second dummy gate material is selectively removed by means such as dry etching or wet etching, thereby exposing the previously covered second gate region.

[0069] In some embodiments, after the second sacrificial layer is removed, a through hole is formed between the first gate region and the second gate region, that is, a through hole that penetrates the gate isolation layer.

[0070] In some embodiments, before performing the first wafer flip, the second sacrificial layer may be replaced with an insulating material to form an intermediate isolation layer; the intermediate isolation layer is used to isolate the first transistor and the second transistor. In the case of forming the intermediate isolation layer, a through-hole is formed through the gate isolation layer by removing the intermediate isolation layer.

[0071] In some embodiments, without forming an intermediate isolation layer, electrical isolation between the first and second transistors can be achieved by ion implantation between the first and second active structures. In this case, a through-hole is formed through the gate isolation layer by removing the second sacrificial layer.

[0072] In step 105, a second gate metal layer of the second transistor and a first gate metal layer of the first transistor are formed, and a gate interconnect via is formed in the through hole.

[0073] In some embodiments, gate interconnect vias are connected to a first gate metal layer and a second gate metal layer, respectively; the first orthographic projection of the gate interconnect vias in a first direction is located inside the second orthographic projection of the active structure in the first direction; wherein the first gate metal layer is formed after a second wafer flipping is performed on the wafer.

[0074] In some practical examples, a second gate metal layer and a portion of gate interconnect vias are formed in the same deposition process; then, the wafer is flipped a second time; in the same deposition process, a first gate metal layer and another portion of gate interconnect vias are formed.

[0075] In some embodiments, the gate interconnect via is in the gate isolation layer and extends through the gate isolation layer; the first orthographic projection of the gate interconnect via in the first direction is located inside the second orthographic projection of the active structure in the first direction, indicating that the gate interconnect via is located inside the active region.

[0076] In some possible implementations, step 105 may include: filling an insulating material in the first gate region corresponding to the first active structure and the first region of the through hole to form a first sacrificial layer; the first region being the portion of the through hole near the first gate region; filling a conductive material in the second gate region corresponding to the second active structure and the second region of the through hole to form a second gate metal layer and a first gate interconnect via of the second transistor; the second region being the portion of the through hole near the second gate region; performing a second die flip; removing the first sacrificial layer and filling a conductive material in the second gate region and the second region of the through hole to form a first gate metal layer and a second gate interconnect via of the first transistor; the first gate interconnect via and the second gate interconnect via being connected to form a gate interconnect via.

[0077] In some embodiments, a first sacrificial layer is formed in a first gate region and a portion of a through-hole region (i.e., the first region). The first sacrificial layer is used to occupy space for the subsequently fabricated first gate metal layer and second gate interconnect via, and to provide support for the subsequently fabricated second gate metal layer and first gate interconnect via.

[0078] In some embodiments, before the second rewinding is performed, the through hole can be divided into upper and lower parts, with the lower part being the first region and the upper part being the second region.

[0079] In some embodiments, the first gate interconnect via and the second gate interconnect via together fill the entire through-hole. The first gate interconnect via and the second gate metal layer are formed in the same deposition process, and they are in contact with each other to form an electrical connection. The second gate interconnect via and the first gate metal layer are formed in the same deposition process, and they are in contact with each other to form an electrical connection. Simultaneously, the first gate interconnect via and the second gate interconnect via, made of conductive material, are also electrically connected due to their contact with each other. This enables the first gate metal layer and the second gate metal layer to achieve gate interconnection within the active region through the gate interconnect vias.

[0080] In some possible implementations, the above method may further include: forming a second back-channel interconnect layer for the second transistor before the second wafer flipping; and forming a first back-channel interconnect layer for the first transistor after forming the gate interconnect via.

[0081] In some embodiments, after forming the second gate metal layer of the second transistor and before the second flip-flop, a back-end interconnect process is performed on the second transistor to form the second source / drain metal and the second back-end interconnect layer of the second transistor.

[0082] In some embodiments, after forming the gate interconnect via and the first gate metal layer, a back-end interconnect process is performed on the first transistor to form the first source / drain metal and the first back-end interconnect layer of the first transistor.

[0083] In some embodiments, the back-end interconnect layer (such as the first back-end interconnect layer and the second back-end interconnect layer) refers to the metal interconnect network in the transistor, which is used to connect various functional modules to form a complete circuit network.

[0084] Figure 2 This is a design layout of stacked transistors in an embodiment of this application. Figures 3 to 40 This is a schematic flowchart of a method for fabricating stacked transistors in an embodiment of this application. Figure 41 This is a schematic diagram of a stacked transistor structure in an embodiment of this application. Below, in conjunction with… Figures 2 to 41 The method for fabricating stacked transistors provided in the embodiments of this application will be described.

[0085] It should be noted that, Figure 2 The design layout shows three cross-sectional directions. Figures 3 to 41 The fabrication process and structural diagram of stacked transistors are shown in these three cross-sectional directions.

[0086] In one example, the stacked transistors are fabricated as follows:

[0087] Step 1: Provide a substrate 21, on which a bottom sacrificial layer 22, a second semiconductor layer 232, a second sacrificial layer 24, and a first semiconductor layer 231 are sequentially stacked (see...). Figure 3 ).

[0088] The first semiconductor layer 231 and the second semiconductor layer 232 are both stacked structures formed by alternating deposition of Si and SiGe.

[0089] Step 2: Etch the first semiconductor layer 231, the second sacrificial layer 24, the second semiconductor layer 232, and the bottom sacrificial layer 22 to form the first active structure 111 and the second active structure 121 (see...). Figure 4 ).

[0090] Step 3: Deposit insulating material on substrate 21 and etch back to form shallow trench isolation (STI) layer 25 (see Figure 5 ).

[0091] Step 4: Deposit semiconductor material (such as polysilicon) in the gate region of the second transistor to form a second dummy gate structure 262; deposit insulating material on the second dummy gate structure 262 to form a gate isolation layer 27; deposit semiconductor material in the gate region of the first transistor to form a first dummy gate structure 261; deposit insulating material to form a sidewall 28 (see...). Figure 6 ).

[0092] Step 5: Etch sidewalls 28 until the first active structure 111 and the second sacrificial layer 24 are exposed (see...) Figure 7 ).

[0093] Step 6: Remove the first active structure 111 in the source / drain region by etching to form the first source / drain groove (see...). Figure 8 ).

[0094] Step 7: Remove the second sacrificial layer 24 to form the first gap 29 (see...) Figure 9 ).

[0095] Step 8: Deposit an insulating dielectric material (such as SiN) in the first gap 29 to form an intermediate isolation layer 30 (see...) Figure 10 ).

[0096] Step 9: Anisotropic etching of the intermediate isolation layer 30 located in the source / drain region (see...) Figure 11 ).

[0097] Step 10: Laterally etch SiGe in the first active structure 111, and fill the etched grooves with insulating material (such as SiN) to form the first inner sidewall 311 (see...). Figure 12 ).

[0098] Step 11: Remove the sidewalls 28 on the surface of the second active structure 121 by anisotropic etching; and remove the second active structure 121 in the source / drain region by etching to form the second source / drain groove (see...). Figure 13 ).

[0099] Step 12: Remove the bottom sacrificial layer 22 and shallow trench isolation layer 25 at the bottom of the source / drain region by anisotropic etching (see...). Figure 14 ).

[0100] Step 13: Fill the second source / drain groove with insulating material (such as SiCN) to form the third sacrificial layer 32 (see...). Figure 15 ).

[0101] Step 14: Deposit insulating material in the source / drain region on the third sacrificial layer 32 to form the source / drain isolation layer 33 (see...). Figure 16 ).

[0102] Step 15: Perform source / drain epitaxial growth in the first source / drain groove to form the first source / drain epitaxial layer 112 (see...). Figure 17 ).

[0103] Step 16: Form the first interlayer dielectric layer 113 in the source / drain region of the first transistor 11 (see...) Figure 18 ).

[0104] Step 17: Deposit insulating material on the first interlayer dielectric layer 113 and the first dummy gate structure 261 to form a first insulating layer 41; bond the first insulating layer 41 to the first carrier wafer 42 (see...). Figure 19 ).

[0105] Step 18: Flip the first transistor 11 and thin the substrate 21 until the shallow trench isolation layer 25 is exposed (see...). Figure 20 ).

[0106] Step 19: Selectively etch the shallow trench isolation layer 25 (see...) Figure 21 ).

[0107] Step 20: In the grooves left by the etched shallow trench isolation layer 25, semiconductor material is deposited. The deposited semiconductor material combines with the second pseudo-gate structure 262 to form a new second pseudo-gate structure 262 (see...). Figure 22 ).

[0108] Step 21: Remove the third sacrificial layer 32 (see...) Figure 23 ).

[0109] Step 22: Laterally etch the SiGe in the second active structure 121, and fill the grooves formed by the etching with insulating material to form the second inner sidewall 312 (see...). Figure 24 ).

[0110] Step 23: Perform source / drain epitaxial growth in the second source / drain groove to form the second source / drain epitaxial layer 122, and form the second interlayer dielectric layer 123 (see...). Figure 25 ).

[0111] Step 24: Remove the second pseudo-gate structure 262 to expose the second gate region in the second transistor 12 (see...). Figure 26 ).

[0112] Step 25: Remove the SiGe layer in the second active structure 121 to release the channel (see...). Figure 27 ).

[0113] Step 26: Remove the intermediate insulating layer 30 to form a through hole 34 (see...) Figure 28 ).

[0114] Step 27: Remove the first dummy gate structure 261 to expose the first gate region in the first transistor 11; then, remove the SiGe layer in the first active structure 111 to perform channel release (see...). Figure 29 ).

[0115] Step 28: Deposit high-K material to form gate dielectric layer 35, which includes the first gate dielectric layer in the first transistor 11 and the second gate dielectric layer in the second transistor 12 (see...). Figure 30 ).

[0116] Step 29: Deposit insulating material in the first gate region and a portion of the through-hole 34 to form the first sacrificial layer 36 (see...). Figure 31 ).

[0117] Step 30: Deposit conductive material (such as W) in another portion of the through-hole 34 and the second gate region to form the second gate metal layer 124 and the first gate interconnect via 13 (see...). Figure 32 ).

[0118] Step 31: Perform gate cut processing to form the second gate cut structure 125 (see...) Figure 33 ).

[0119] Step 32: Form a patterned first hard mask 45 on the second interlayer dielectric layer 123 and the second gate metal layer 124 (see...) Figure 34 The first hard mask 45 is used to define the location of the second source / drain metal in the second transistor.

[0120] Step 33: Form the second source / drain metal 126; through subsequent processing, form the second post-processing interconnect layer 127 (see...). Figure 35 ).

[0121] Step 34: Deposit insulating material on the second back-end interconnect layer 127 to form a second insulating layer 43; bond the second insulating layer 43 to the second carrier wafer 44; flip the second transistor 12 so that the first transistor 11 faces upward, and remove the first carrier wafer 42 and the first insulating layer 41 until the first sacrificial layer 36 is exposed (see...). Figure 36 ).

[0122] Step 35: Remove the first sacrificial layer 36 to expose the first gate region (see...) Figure 37 ).

[0123] Step 36: Deposit conductive material in the first gate region and a portion of the through-hole 34 to form the first gate metal layer 114 and the second gate interconnect via 14 (see...). Figure 38 ).

[0124] Step 37: Perform gate cut-off processing to form the first gate cut-off structure 115 (see...) Figure 39 ).

[0125] Step 38: Form a patterned second hard mask 46 on the first interlayer dielectric layer 113 and the first gate metal layer 114 (see...) Figure 40 The second hard mask 46 is used to define the location of the first source / drain metal in the first transistor.

[0126] Step 39: Form the first source / drain metal 116; through subsequent processing, form the first post-processing interconnect layer 117 (see...). Figure 41 ).

[0127] This completes the fabrication of the stacked transistor.

[0128] In some embodiments, the method for fabricating stacked transistors described in this application can be compatible with methods involving single-pass, double-pass, and triple-pass wafer fabrication.

[0129] In some embodiments, the method for fabricating stacked transistors described in this application can be compatible with both common gate and split gate processes.

[0130] In some embodiments, the first transistor and the second transistor can be transistors with different polarities (i.e., different channel doping types). For example, the first transistor is an N-channel metal oxide-semiconductor field-effect transistor (NMOS), and the second transistor is a P-channel metal oxide-semiconductor field-effect transistor (PMOS); or the first transistor is a PMOS and the second transistor is an NMOS.

[0131] In some embodiments, the present application does not specifically limit the polarity (i.e. different doping types) of devices such as the gate metal layer, gate cut-off structure and source-drain epitaxy in the first transistor and the second transistor, and can be designed according to actual process requirements.

[0132] In the embodiments of this application, by forming gate interconnect vias located inside the active region, the gate extension region that must be reserved for external vias can be eliminated, resulting in a smaller gate pattern area and thus significantly reducing parasitic capacitance.

[0133] Furthermore, by forming gate interconnect vias located inside the active region, the problem of mutual constraint between the width of the active region and the size of the interlayer interconnect vias in the stacked device can be solved, so that the width of both the gate interconnect vias and the width of the active region can be increased, thereby freeing up the width of the active region, reducing parasitic resistance and improving device performance.

[0134] Furthermore, from the perspective of process difficulty, by eliminating the traditional small-size through-hole photolithography process, self-aligned gate interconnect through-holes have been achieved, which can reduce process difficulty, mitigate the technical problems of photolithography alignment, and ultimately reduce device failure rate.

[0135] This application provides a stacked transistor, which can be fabricated using the aforementioned stacked transistor fabrication method. The stacked transistor includes: a first transistor; the first transistor includes a first active structure and a first gate metal layer; a second transistor; the second transistor includes a second active structure and a second gate metal layer; the first transistor and the second transistor are stacked in a first direction; a gate interconnect via; the gate interconnect via is electrically connected to the first gate metal layer and the second gate metal layer respectively; the orthographic projection of the gate interconnect via in the first direction is located inside the orthographic projection of the first active structure in the first direction.

[0136] In some embodiments, see Figure 41As shown, the first transistor 11 and the second transistor 12 are stacked in a first direction. The first transistor 11 and the second transistor 12 constitute a stacked transistor.

[0137] In some embodiments, the active regions of the first transistor 11 and the second transistor 12 are self-aligned; meanwhile, the first gate metal layer 114 of the first transistor 11 and the second gate metal layer 124 of the second transistor 12 are interconnected within the active regions through gate interconnect vias (including the first gate interconnect via 13 and the second gate interconnect via 14).

[0138] The stacked transistors provided in this application embodiment can be inspected using analytical instruments such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). For example, using TEM, it can be observed in a TEM slice that the gate interconnect vias are located inside the active region.

[0139] This application provides a semiconductor device, which may include multiple such semiconductor devices. Figure 41 The stacked transistors shown are electrically connected through a back-end interconnect layer, which transmits signals to form a functional circuit.

[0140] This application provides an electronic device, including: a circuit board and a semiconductor device as described above, wherein the semiconductor device is mounted on the circuit board and electrically connected to the circuit board.

[0141] In some embodiments, an electronic device refers to a device composed of a variety of electronic components capable of performing a specific function. Once semiconductor devices are mounted on the system motherboard, they can be used as main memory or cache, and can support high-speed data read / write and complex computational tasks.

[0142] In some embodiments, the electronic device may include, but is not limited to: mobile communication devices, such as mobile phones, tablets, 5G / 6G base stations; computing devices, such as personal computers, laptops, servers, data center computing units; consumer electronics products, such as smart wearable devices, digital cameras, game consoles; Internet of Things devices or automotive electronic systems.

[0143] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, include: An active structure is formed on a substrate; the active structure includes a first active structure and a second active structure stacked sequentially in a first direction; A pseudo-gate stack structure is formed on the substrate; the pseudo-gate stack structure includes a first pseudo-gate structure surrounding the first active structure, a gate isolation layer, and a second pseudo-gate structure surrounding the second active structure; The first source-drain epitaxial layer of the first transistor and the second source-drain epitaxial layer of the second transistor are formed; wherein the second source-drain epitaxial layer is formed after the first wafer flipping is performed; Remove the first pseudo-gate structure and the second pseudo-gate structure, and form a through hole through the gate isolation layer; A second gate metal layer is formed for the second transistor and a first gate metal layer for the first transistor, and a gate interconnect via is formed in the through-hole; the gate interconnect via connects the first gate metal layer and the second gate metal layer respectively; the first orthographic projection of the gate interconnect via in the first direction is located inside the second orthographic projection of the active structure in the first direction; wherein, the first gate metal layer is formed after the wafer is subjected to a second wafer flip.

2. The method according to claim 1, characterized in that, The second gate metal layer forming the second transistor and the first gate metal layer forming the first transistor, and the gate interconnect via formed in the through hole, include: An insulating material is filled in the first gate region corresponding to the first active structure and the first region of the through hole to form a first sacrificial layer; the first region is the portion of the through hole close to the first gate region; A conductive material is filled in the second gate region corresponding to the second active structure and the second region of the through hole to form the second gate metal layer and the first gate interconnect via of the second transistor; the second region is the portion of the through hole close to the second gate region. Perform a second rewind; The first sacrificial layer is removed, and conductive material is filled in the second gate region and the second region of the through hole to form the first gate metal layer and the second gate interconnect via of the first transistor; the first gate interconnect via and the second gate interconnect via are connected to form a gate interconnect via.

3. The method according to claim 1, characterized in that, The formation of an active structure on the substrate includes: A substrate is provided, and a stacked structure is formed on the substrate; the stacked structure includes a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer stacked in the first direction; The stacked structure is etched to form the first active structure and the second active structure; the etched second sacrificial layer is located between the first active structure and the second active structure.

4. The method according to claim 3, characterized in that, The step of removing the first pseudo-gate structure and the second pseudo-gate structure and forming a through hole through the gate isolation layer includes: Remove the second dummy gate structure to expose the second gate region; The second sacrificial layer between the second gate region and the first gate region is removed to form the through-hole; Remove the first dummy gate structure to expose the first gate region.

5. The method according to claim 1, characterized in that, The first source-drain epitaxial layer forming the first transistor and the second source-drain epitaxial layer forming the second transistor include: The active structure is etched to form a first source / drain groove and a second source / drain groove; An insulating material is filled into the second source / drain groove to form a third sacrificial layer; A dielectric material is deposited on the third sacrificial layer to form a source / drain isolation layer; Source-drain epitaxial growth is performed in the first source-drain groove to form the first source-drain epitaxial layer; Perform the first wafer flipping and thin the substrate; Remove the third sacrificial layer to expose the second source-drain groove; Source-drain epitaxial growth is performed in the second source-drain groove to form the second source-drain epitaxial layer.

6. The method according to claim 1, characterized in that, The formation of the pseudo-gate structure on the substrate includes: A semiconductor material of a predetermined height is deposited on the substrate to form the second pseudo-gate structure; An insulating material is deposited on the second pseudo-gate structure to form the gate isolation layer; The semiconductor material is deposited on the gate isolation layer to form the first pseudo-gate structure.

7. The method according to claim 1, characterized in that, The method further includes: Prior to the second wafer reflow, a second back-end interconnect layer for the second transistor is formed; After forming the gate interconnect via, a first back-channel interconnect layer of the first transistor is formed.

8. A stacked transistor, characterized in that, The stacked transistor is prepared using the method described in any one of claims 1 to 7, wherein the stacked transistor comprises: A first transistor; the first transistor includes a first active structure and a first gate metal layer; The second transistor includes a second active structure and a second gate metal layer; the first transistor and the second transistor are stacked in a first direction; Gate interconnect via; the gate interconnect via is electrically connected to the first gate metal layer and the second gate metal layer respectively; the orthogonal projection of the gate interconnect via in the first direction is located inside the orthogonal projection of the first active structure in the first direction.

9. A semiconductor device, characterized in that, include: Multiple stacked transistors as described in claim 8; Multiple stacked transistors are electrically connected through a back-end interconnect layer to form a functional circuit.

10. An electronic device, characterized in that, include: Circuit board; The semiconductor device as claimed in claim 9; the semiconductor device is mounted on the circuit board and electrically connected to the circuit board.

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