A pipelined folding interpolation analog-to-digital converter

Abstract

The present invention relates to the field of integrated circuits, and more particularly to a pipelined folding interpolation analog-to-digital converter. The present invention comprises a folding interpolation structure containing redundant information and an error correction logic circuit. The redundant information of the current stage and the original quantization information of the subsequent stage are used to correct the errors of the original quantization information of the current stage, and then the information is sent to the encoding circuit to produce a correct data conversion result, which can reduce the requirements for errors such as the offset voltage of the comparator. The error correction logic circuit determines the position range of the zero crossing point of the folding quantization curve of the current stage through a zero crossing detection circuit, generates an edge correction signal aligned with the data bit of the subsequent stage through an edge correction signal generation circuit, and generates correct quantization information through a control circuit. The present invention solves the problem that the data conversion result of the existing pipelined folding interpolation structure analog-to-digital converter is incorrect due to the correctness of the zero crossing point of the folding quantization curve, or the accuracy limitation or offset voltage error of the comparator, resulting in errors in the final data conversion result.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a pipelined folding interpolation analog-to-digital converter. Background Art

[0002] The traditional folding interpolation architecture is the preferred structure for implementing ultra-high-speed A / D converters, but its accuracy is limited to 8 bits. As the demand for accuracy increases, to achieve ultra-high-speed A / D converters with 10-12 bits, a pipelined folding interpolation structure has been developed based on the traditional folding interpolation structure. This multi-stage folding interpolation cascade structure can achieve high folding and high interpolation rates while reducing the gain and bandwidth requirements of each stage of the folding interpolator, allowing the A / D converter to have both high conversion rate and high accuracy.

[0003] The principle of the pipelined folding interpolation structure is that the N+1-stage folding interpolation structure refines the sub-quantization interval of the N-stage folding interpolation structure into multiple smaller sub-intervals, continuing until the final stage. Each stage of the folding interpolation structure generates a folding quantization curve, which is used by a comparator to generate raw quantization information. When the level of the folding quantization curve is greater than 0, the comparator outputs the raw quantization information as 1; when the level of the folding quantization curve is less than 0, the comparator outputs the raw quantization information as 0. The raw quantization information at each stage is then input into the encoding circuit, generating the data output of the A / D converter as the final data conversion result. Therefore, the final data conversion result is directly related to the raw quantization information at each stage, that is, closely related to the correct zero-crossing point of the folding quantization curve. If the zero-crossing point of the folding quantization curve is offset, or if a bit of the raw quantization information is incorrect due to accuracy limitations or offset voltage in the comparator, the final data conversion result will be incorrect.

[0004] However, the existing pipelined folding interpolation structure does not have error correction capability. Summary of the Invention

[0005] In view of the above-mentioned problems or shortcomings, and in order to solve the problem of errors in the data conversion results of the existing pipelined folding interpolation structure analog-to-digital converter, the present invention provides a pipelined folding interpolation analog-to-digital converter, which corrects the original quantized information step by step from the last-level folding interpolation circuit to the upper-level folding interpolation circuit, sends the corrected quantized information to the encoding circuit, and the encoding circuit generates the final data conversion result of the analog-to-digital converter, thereby realizing error correction of the digital coding logic.

[0006] A pipelined folding interpolation analog-to-digital converter includes a folding interpolation circuit, a comparator, an error correction logic circuit and an encoding circuit. The last-stage folding interpolation circuit corrects the original quantized information step by step toward the upper stage, and the corrected quantized information is sent to the encoding circuit.

[0007] The folding interpolation circuit has M (M≥2) stages, with the Mth stage including an interpolation circuit and a quantization folder. The remaining M-1 stages have the same architecture, each including an interpolation circuit, a quantization folder, and a redundant folder. For the Nth stage (N≤M-1) folding interpolation circuit, the quantization folder generates a folded quantization curve, and the redundant folder generates a folded redundant curve. The folded quantization curve and the folded redundant curve of the Nth stage are combined to form a folding curve of the Nth stage. After being processed by the interpolation circuit, the folded curve is output to the corresponding folder of the N+1th stage folding interpolation circuit (the folded redundant curve is transmitted to the redundant folder, and the folded quantization curve is transmitted to the quantization folder) for processing.

[0008] The comparator has N corresponding levels, and each quantization folder and redundant folder of each level of folding interpolation circuit is connected to the comparator. The redundant information and original quantization information of the Nth level are generated by the comparator corresponding to the Nth level and output to the zero-crossing point detection circuit and edge correction signal generation circuit of the Nth level error correction logic circuit.

[0009] The error correction logic circuit has N corresponding stages, each with the same architecture, including a zero-crossing detection circuit, an edge correction signal generation circuit, and a control circuit. The error correction logic circuit sequentially performs error correction, with each Nth stage corresponding to the Nth-stage folding interpolation circuit and comparator. The last stage (the Mth stage) does not perform error correction. The M-1th stage folding interpolation circuit then performs error correction on the original quantized information one stage at a time, proceeding to the next stage. The corrected quantized information is then fed into the encoding circuit.

[0010] For the Nth level error correction logic circuit:

[0011] The zero-crossing detection circuit generates an edge detection signal of the Nth level according to the Nth level redundant information and the original quantization information of the subsequent level, determines the position range of the zero-crossing point of the Nth level folded quantization curve, and the number of edge detection signals is ≥ the number of the Nth level quantization folders.

[0012] The edge correction signal generating circuit generates an N-th level edge correction signal according to the N-th level original quantization information and the subsequent level quantization information. The number of edge correction signals is greater than or equal to the number of the N-th level quantization folders.

[0013] The control circuit outputs the quantized information after error correction: when the edge detection signal of the Nth level is valid, the edge correction signal of the Nth level is output; otherwise, the original quantized information of the Nth level is output.

[0014] The encoding circuit receives the quantization information output by the control circuit in the error correction logic circuit to generate a correct (error-corrected) data final output result.

[0015] Furthermore, error correction is performed on the original quantization information of the Nth level (N≤M-1) folding interpolation circuit, and all zero-crossing points of the Nth level folding curve are included in a folding quantization curve in the N+1th level.

[0016] Furthermore, the latter stages in the zero-crossing point detection circuit and the edge correction signal generating circuit include only the N+1th stage, or a combination of the N+1th stage and the N+2th stage, ..., up to the Mth stage.

[0017] Furthermore, in the zero-crossing point detection circuit, the relationship between the subsequent original quantization information and the Nth level is as follows: the subsequent original quantization information has at most one zero-crossing point of the Nth level folded quantization information in the high-level or low-level area, and the zero-crossing point is located in the middle of the adjacent zero-crossing points of the subsequent original quantization information.

[0018] Furthermore, the edge correction signal generating circuit generates an Nth-level edge correction signal according to the highest bit of the Nth-level original quantization information and the subsequent-level quantization information.

[0019] Furthermore, in the zero-crossing detection circuit, an N-th level edge detection signal is also generated based on the N-th level redundant information, the subsequent original quantization information and the subsequent edge detection signal to further determine the position range of the zero-crossing point of the N-th level folded quantization curve.

[0020] Furthermore, the Nth level folding interpolation structure includes an interpolation circuit with an interpolation rate of 4, two quantization folders and two redundant folders, and the two quantization folders generate two folding curves S N 1 and S N 3. The two redundant folders generate two folding redundant curves S N 2 and S N 4. The folding curve S of the Nth level N 1. S N 2. S N 3 and S N 4 are evenly arranged in sequence, i.e. folding curve S N 2 is located in S N 1 and S N The middle of 3, S N 3 is located in S N 2 and S N The Nth level folding curve passes through the interpolation circuit with an interpolation rate of 4, and is then input to the N+1th level folding interpolation circuit with a folding rate of 4 for processing, to obtain the folding output curve S N+1 1,S N+1 2. S N+1 3 and S N+1 4. Folding quantization curve S N+1 1 contains all zero crossing points of the Nth level folding curve, folding quantization curve SN+ 13 In the high level or low level area, there is at most one N-level folded quantization curve (S N 1 or S N 3) and the zero crossing point is located at the folded quantization curve S N+1 3The middle of adjacent zero crossings.

[0021] Furthermore, the zero-crossing detection circuit utilizes the folded quantization curve S of the N+1th level. N+1 3. Folding redundancy curve S of level N N 2 and S N 4. Generate two edge detection signals of the Nth level.

[0022] Furthermore, the two edge detection signals of the Nth stage are equivalent to:

[0023] and or and

[0024] Furthermore, the zero-crossing detection circuit utilizes the K+1th level (1≤K≤M-2) folded quantization curve S K+1 3. K-th level folding redundancy curve S K 2 and S K 4, and the highest bit edge detection signal Synm of the K+1th level K+1 , generating two edge detection signals of the Kth level.

[0025] Furthermore, the two edge detection signals of the Kth stage are equivalent to:

[0026] and

[0027] or and

[0028] Furthermore, the edge correction signal generating circuit generates two edge correction signals of the Nth level using the highest data bit DL of the subsequent quantization information and the original quantization information of the Nth level, which is equivalent to:

[0029] and

[0030] The present invention includes a folding interpolation structure containing redundant information and an error correction logic circuit. The redundant information of the current stage and the original quantization information of the subsequent stage are used to correct the errors of the original quantization information of the current stage. The zero-crossing point position range of the folded quantization curve of the current stage is determined by a zero-crossing point detection circuit in the error correction logic circuit. An edge correction signal generation circuit generates an edge correction signal aligned with the data bit of the subsequent stage. The control circuit then selects and outputs the signal to generate correct quantization information and send it to the encoding circuit. This effectively ensures that the states of each stage are converted simultaneously, thereby giving the digital encoding logic a certain error correction capability.

[0031] In summary, the present invention implements error correction in digital coding logic by progressively correcting the original quantized information from the last-stage folding interpolation circuit to the next-stage folding interpolation circuit. This corrected quantized information is then fed into an encoding circuit, which then generates the final data conversion result of the analog-to-digital converter. This solves the problem of the data conversion results of existing pipelined folding interpolation analog-to-digital converters, where errors in the final data conversion result can occur due to the accuracy of the zero crossing of the folded quantization curve, or errors in the comparator due to precision limitations or offset voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of the folding interpolation structure containing redundant information in Example 1;

[0033] Figure 2 1 is a schematic diagram of the structure of the error correction logic circuit of the Nth stage in Example 1;

[0034] Figure 3 Schematic diagram of the relationship between the folding curves of the Nth level and the N+1th level in Example 1;

[0035] Figure 4 It is a schematic diagram of the alignment of the low-order and high-order data conversion edges of the analog-to-digital converter;

[0036] Figure 5 Schematic diagram of the relationship between the Nth level folding curve and the N+1th level high-order data bits in Example 1;

[0037] Figure 6 This is the Nth level error correction logic circuit of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0039] Example 1:

[0040] Figure 1The folding interpolation structure with redundant information and the corresponding folding curve diagram of embodiment 1 are shown. The Nth-level folding interpolation structure includes four folders 101 and a resistor interpolation circuit 102 with an interpolation rate of 4. The four folders 101 generate four folding curves S N 1. S N 2. S N 3 and S N 4, where S N 1 and S N 3 is the folded quantization curve, which generates 2 bits of original quantization information of level N through the comparator; S N 2 and S N 4 is a folded redundancy curve, which generates N-th level redundant information through a comparator.

[0041] The effective level precision of the Nth level folding interpolation structure is 2, and the four folding curves (S N 1. S N 2. S N 3 and S N 4) After being processed by the resistor interpolation circuit 102, S N 1 and S N The interpolation curves obtained between 2 are denoted as S N 1_2, S N 1_3, S N 1_4, S N 2 and S N The interpolation curves obtained between 3 are denoted as S N 2_2, S N 2_3, S N 2_4, S N 3 and S N The interpolation curves obtained between 4 are denoted as S N 3_2, S N 3_3, S N 3_4, S44 and S N The interpolation curves obtained between l are denoted as S N 4_2, S N 4_3, S N 4_4, so after processing by the interpolation circuit 102, a total of 16 interpolation curves can be obtained, and these 16 interpolation curves are then input into the N+1th stage folding interpolation circuit for processing.

[0042] The N+1th stage folding interpolation circuit includes four folders 201 and a resistor interpolation circuit 202 with an interpolation rate of 4. The four folders 201 fold the 16 interpolation curves output from the Nth stage into four folding curves S N+1 1. S N+1 2. S N+1 3 and S N+1 4, where the folding curve SN+1 1 From the Nth level folding curve S N 1. S N 2. S N 3 and S N 4 is generated by a folder at level N+1, so the folding curve S N+1 1 also includes the folding curve S N 1. S N 2. S N 3 and S N 4 all zero crossings; similarly, the folded curve S N+1 i (i=2,3,4) is formed by the Nth level folding curve S N 1_i、S N 2_i、S N 3_i and S N 4_i is generated by a folder at level N+1, and the folding curve S N+1 i also includes the folding curve S N 1_i、S N 2_i、S N 3_i and S N All zero crossing points of 4_i. The 4 folding curves of level N+1 (S N+1 1. S N+1 2. S N+1 3 and S N+1 4) 16 interpolation curves are generated by the resistor interpolation circuit 202 with an interpolation rate of 4 and input to the next level of folded interpolation structure for processing until the last level.

[0043] For convenience, the symbol S N X also represents the folding curve S N X is the original quantized information output by the comparator. When the folding curve S N When the X level is greater than 0, the original quantization information S N X is 1; when the folding curve S N When the X level is less than 0, the original quantization information S N X is 0. S N The voltage corresponding to X changing from 0 to 1 or from 1 to 0 is called the zero crossing point. Figure 1 Middle folding curve S N The zero crossing points of 1 are A1, A2 and A3, and the folding curve S N The zero crossing points of 3 are B1 and B2. It can be seen that the folding curve S N+1 The zero crossing point of 1 includes the zero crossing points of all folding curves of level N.

[0044] Folding quantization curve S of level N N 1 and S N3. Quantize a subinterval of level N-1 (range from A1 to A3) into 4 subintervals (A1-B1, B1-A2, A2-B2, B2-A3), which can provide 2-bit precision at this level. The low bit is recorded as D. N 0. High position is D N l. Similarly, the folded redundancy curve S of level N N 2 and S N 4 Similarly, a subinterval of level N-1 is refined into 4 subintervals of level N. Therefore, when the zero-crossing point position is accurate, only the original quantization information S of level N is needed. N 1 and S N 3, the final output data D can be obtained by passing through the encoding circuit N 1. D N 0:

[0045]

[0046]

[0047] From formulas (1) and (2), we can see that in the interval A1-B1, D N 1D N 0=00; between B1-A2, D N 1D N 0=01; between the interval A2-B2, D N 1D N 0=10; between B2-A3, D N 1D N 0=11.

[0048] Even with a pipelined folding circuit with high accuracy, comparator offset voltage or noise are unavoidable, leading to deviations in the zero-crossing positions of each stage and errors in the original quantized information. Therefore, the present invention provides an error-correcting logic circuit that corrects the original quantized information step by step, from the last stage to the next. The generated corrected quantized information is then fed into an encoding circuit for processing, producing a correct (corrected) final data output.

[0049] Figure 2 It is the error correction logic circuit of embodiment 1, including a zero-crossing point detection circuit 21, an edge correction signal generating circuit 22 and a control circuit 23.

[0050] The zero-crossing detection circuit 21 generates an edge detection signal Syn of the Nth level according to the Nth level redundant information and the N+1th level original quantization information, and determines the correct zero-crossing position range of the Nth level folded quantization curve.

[0051] The edge correction signal generating circuit 22 generates an edge correction signal Cal of the Nth level according to the highest bit of the Nth level original quantization information and the N+1th level quantization information.

[0052] The control circuit 23 outputs the edge correction signal Cal when the edge detection signal Syn of the Nth level is valid; otherwise, it outputs the original quantized information S of the Nth level. N X.

[0053] by Figure 1 The N-th level folded interpolation structure is used as an example to illustrate the implementation of the error correction logic circuit.

[0054] First, the error correction logic circuit needs to generate an edge detection signal to determine the folded quantization curve S N 1 and S N 3's zero-crossing position range, that is Figure 1 At A1, A2, A3, B1 and B2 in the Nth level of the folded redundancy curve S N 2 and S N 4 The folded quantization curve S can be roughly divided N 1. S N 3 zero-crossing area, so it can be based on the redundant information S N 2 and S N 4 to generate two edge detection signals Syn1 N and Syn3 N , which can be expressed as:

[0055]

[0056]

[0057] When the redundant information S N 2 and S N 4 When both are high or low, the edge detection signal Syn1 N is high level; when the folded curve S N 2 and S N 4 When one is high and the other is low, the edge detection signal Syn3 N When the edge detection signal is high, it corresponds to the zero-crossing position range of the Nth level folded quantization curve. N When the level is high, the quantization curve S is folded. N 1 can generate zero crossing points A1, A2, A3. When the edge detection signal Syn3 N When valid, the folded quantization curve S N3 can generate zero-crossing points B1 and B2. However, if the zero-crossing position range of the folded quantization curve of this stage is determined only by the folded redundant curve of this stage, this is obviously very rough. It is necessary to use the information of the subsequent folding curve to narrow this range and thus determine the zero-crossing position range more accurately.

[0058] As mentioned above, the N+1 level folding interpolation structure is similar to the N level structure, including the folding quantization curve S N+1 1. S N+1 3 and folded redundant curve S N+1 2. S N+1 4, where the folded quantization curve S N+1 1 and S N+1 3. Quantize a subinterval of level N (e.g. A1-B1) into 4 subintervals of level N+1 (e.g. Figure 3 (as shown by the dotted line in the N+1th level folding curve), providing an effective level accuracy of log2(4)=2 bits.

[0059] For ease of explanation, Figure 3 The folded quantization curve S N+1 3 is copied to the folding curve of level N, and we can see that the folding quantization curve S of level N+1 is N+1 3 and the folded quantization curve S of the Nth level N 1 and S N 3 Existence relationship: S N+1 There is only S in the low level area of ​​3 (such as I area). N 1 or S N 3 (such as A2 in the I region), and ideally these zero crossings are located on the folded quantization curve S N+1 3The middle of adjacent zero crossings.

[0060] Therefore, through the Nth level redundant information S N 2. S N 4, and the N+1th level original quantization information S N+1 3. The range can be further narrowed to more accurately determine the Nth level folding quantization curve S N 1. S N 3. Update formulas (3) and (4), the edge detection signal Syn1 N 、Syn3 N It can be expressed as:

[0061]

[0062]

[0063] If the folded quantization curve S of the N+1th level N+1 3 and the folded quantization curve S of the Nth levelN 1 and S N The relationship of 3 becomes: S N+ In the high level area of ​​13, only S N 1 or S N 3 a zero crossing point, the edge detection signal Syn1 N 、Syn3 N It can be expressed as:

[0064]

[0065]

[0066] As described above, the zero-crossing detection circuit 21 of the Nth stage utilizes the Nth stage redundant information (S N 2. S N 4) The N+1th level original quantized signal (S N+1 3), generate the edge detection signal of the Nth level (Synl N 、Syn3 N ), the position range of the zero-crossing point of the N-th level folded quantization curve can be determined.

[0067] The edge correction signal generating circuit 22 in the error correction logic circuit is used to generate the edge correction signal Cal corresponding to the edge detection signal Syn being valid. Because in the conversion result of the analog-to-digital converter, the high-bit jump moment is always aligned with the low-bit falling edge, such as Figure 4 If the high-bit and low-bit transition times deviate, the analog-to-digital converter (ADC) result will be erroneous. Therefore, when the edge detection signal Syn is valid, the quantization information is no longer determined by the original quantization information at this stage, but by the quantization information at the subsequent stage.

[0068] Will Figure 1 Take the Nth level folding curve out separately, and Figure 5 It can be seen that the folding curve S N 1 in a wide range near the zero crossing point, the folded quantization curve S N 3 levels are constant. For example, in the II area (B1-B3 range) in the figure, the folded quantization curve S N 3 is always high. Therefore, the folded quantization information S can be used to N 3, and the highest bit quantization information D of level N+1 M To generate the original quantized information S N 1 corresponds to the edge correction signal Cal1; similarly, the folded quantization information S at this level can be used N 1 and D M To generate the original quantized information S N The edge correction signal Cal3 of 3 can be expressed as:

[0069]

[0070]

[0071] Through formulas (9) and (10), the Nth level edge correction signal is determined by the N-1th level quantization information, thereby achieving the purpose of simultaneous conversion of the data bits of the Nth level and the N+1th level.

[0072] The control circuit 23 in the error correction logic circuit works as follows: when the edge detection signal Syn is valid (high level), it outputs the edge correction signal Cal; when the edge detection signal Syn is invalid, it outputs the original quantization information S N X. Figure 1 The output of the control circuit 23 is described by taking the folded interpolation structure as an example, including the output of 2-bit quantized information, which can be expressed as out1 and out3:

[0073]

[0074]

[0075] Figure 6 is the error correction logic circuit of embodiment 2, and Figure 2 Compared with the error correction logic circuit of embodiment 1, the difference is that: Figure 6 The zero-crossing detection circuit 41 generates an N-th level edge detection signal based on the N-th level redundant information, the N+1-th level original quantization information, and the N+1-th level edge detection signal (related to the L-th level original quantization information, N+1≤L≤M); the edge correction signal generating circuit 42 generates an N-th level edge correction signal based on the N-th level original quantization information and the L-th level quantization information.

[0076] The principle of the zero-crossing detection circuit 41 is: the N+1th level folded quantization curve S N+1 1 contains all the zero crossing points of the Nth level folding curve, so the N+1th level folding quantization curve S N+1 The edge detection signal of Syn1 also includes the zero crossing point of the Nth level; and since the error correction logic method is to correct the original quantized information step by step from the last level to the next level, the edge detection signal Syn1 of the Nth level N and Syn2 N It can be determined more accurately by formulas (13) and (14), which more accurately determine the range of the zero-crossing position based on formulas (7) and (8).

[0077]

[0078]

[0079] Syn1m in the formulaN+1 The edge correction signal indicating the highest bit of the N+1th level may be correlated with the quantization information of the N+2th level, the N+3th level, ... the Lth level. In this case, the edge correction signal generating circuit 42 generates the highest bit of the quantization information D of the Lth level according to the highest bit of the quantization information D of the Lth level. L and the original quantized information of the Nth level, generate the edge correction signal of the Nth level, and the formula (9) and formula (10) are updated as follows:

[0080]

[0081]

[0082] As can be seen from the above embodiments, the present invention utilizes redundant information from the current stage and the original quantization information from the subsequent stage to perform error correction on the original quantization information of the current stage, generating correct quantization information that is then fed into the encoding circuit to produce a correct data conversion result, thereby reducing the requirements for the comparator offset voltage. The error correction logic circuit includes a zero-crossing detection circuit, an edge correction signal generation circuit, and a control circuit. The zero-crossing detection circuit determines the zero-crossing position range of the folded quantization curve of the current stage, the edge correction signal generation circuit generates an edge correction signal that is aligned with the data bits of the subsequent stage, and the control circuit generates the correct quantization information. The present invention utilizes the zero-crossing detection circuit to determine the zero-crossing position range of the folded quantization curve, utilizes the edge correction signal generation circuit to generate an edge correction signal that is aligned with the data bits of the subsequent stage, and then utilizes the control circuit to select and output, thereby effectively ensuring that the states of each stage are converted simultaneously, thereby endowing the digital encoding logic with a certain error correction capability.

[0083] In summary, the present invention effectively solves the problem that the data conversion results of the existing pipelined folding interpolation structure analog-to-digital converter are erroneous due to the correctness of the zero crossing point of the folding quantization curve, or errors in the comparator due to accuracy limitations or offset voltage.

Claims

1. A pipelined folding interpolation analog-to-digital converter, characterized in that: It includes a folding interpolation circuit, a comparator, an error correction logic circuit and a coding circuit; The folding interpolation circuit has M levels, M≥2, the Mth level includes an interpolation circuit and a quantization folder, and the remaining M-1 levels have the same architecture, including an interpolation circuit, a quantization folder and a redundant folder; For the N-th level folding interpolation circuit, N≤M-1, the quantization folder generates a folding quantization curve, and the redundancy folder generates a folding redundancy curve; the N-th level folding quantization curve and the folding redundancy curve are combined into the N-th level folding curve, which is processed by the interpolation circuit and then output to the corresponding folder of the N+1-th level folding interpolation circuit for processing; The comparator has N corresponding levels, and each quantization folder and redundant folder of each level of folding interpolation circuit is connected to the comparator, and redundant information and original quantization information of the Nth level are generated by the comparator corresponding to the Nth level and output to the zero-crossing point detection circuit and edge correction signal generation circuit of the error correction logic circuit of the Nth level or the previous level; The error correction logic circuit has N corresponding stages, each having the same architecture, including a zero-crossing detection circuit, an edge correction signal generating circuit, and a control circuit; the error correction logic circuit sequentially performs error correction in a one-to-one correspondence manner, with the folding interpolation circuit and comparator of the Nth stage corresponding to the Nth stage; The M-1 level folding interpolation circuit corrects the original quantized information step by step to the next level, and the corrected quantized information is sent to the encoding circuit; For the Nth level error correction logic circuit: The zero-crossing detection circuit generates an edge detection signal of the Nth level according to the Nth level redundant information and the original quantization information of the subsequent level, determines the position range of the zero-crossing point of the Nth level folded quantization curve, and the number of edge detection signals is greater than or equal to the number of quantization folders of the Nth level; An edge correction signal generating circuit generates an edge correction signal of the Nth level according to the original quantization information of the Nth level and the post-quantization information, wherein the number of edge correction signals is greater than or equal to the number of quantization folders of the Nth level; The control circuit outputs the quantized information after error correction: when the edge detection signal of the Nth level is valid, the edge correction signal of the Nth level is output; Otherwise, the output is the original quantized information of level N; The encoding circuit receives the quantization information output by the control circuit in the error correction logic circuit to generate a final output result of the error-corrected data.

2. The pipelined folding interpolation analog-to-digital converter according to claim 1, wherein: Error correction is performed on the original quantization information of the Nth-level folding interpolation circuit, and all zero-crossing points of the Nth-level folding curve are completely included in a folding quantization curve in the N+1th level.

3. The pipelined folding interpolation analog-to-digital converter according to claim 1, wherein: The subsequent stages in the Nth stage zero-crossing point detection circuit and the edge correction signal generating circuit include only the N+1th stage, or a combination of the N+1th stage and the N+2th stage, and so on up to the Mth stage.

4. The pipelined folding interpolation analog-to-digital converter according to claim 1, wherein: In the zero-crossing point detection circuit, the relationship between the subsequent original quantization information and the Nth level is as follows: the subsequent original quantization information has at most one zero-crossing point of the Nth level folded quantization information in the high-level or low-level region, and the zero-crossing point is located between adjacent zero-crossing points of the subsequent original quantization information; In the edge correction signal generating circuit, an edge correction signal of the Nth level is generated according to the highest bit of the original quantization information of the Nth level and the subsequent quantization information.

5. The pipelined folding interpolation analog-to-digital converter according to claim 1, wherein: In the zero-crossing detection circuit, an N-th level edge detection signal is also generated based on the N-th level redundant information, the subsequent original quantization information and the subsequent edge detection signal, to further determine the position range of the zero-crossing point of the N-th level folded quantization curve.

6. The pipelined folding interpolation analog-to-digital converter according to claim 1, wherein: The Nth-stage folding interpolation circuit includes an interpolation circuit with an interpolation rate of 4, two quantization folders and two redundant folders; Two quantization folders generate two folded quantization curves S N 1 and S N 3. Two redundant folders generate two folding redundant curves S N 2 and S N 4. Folding curve S of level N N 1. S N 2. S N 3 and S N 4 are evenly arranged in sequence, i.e. folding curve S N 2 is located in S N 1 and S N The middle of 3, S N 3 is located in S N 2 and S N 4; after the Nth level folding curve passes through the interpolation circuit with an interpolation rate of 4, it is input to the N+1th level folding interpolation circuit with a folding rate of 4 for processing, and the folding output curve S is obtained. N+1 1,S N+1 2. S N+1 3 and S N+1 4. Folding quantization curve S N+1 1 contains all zero crossing points of the Nth level folding curve, folding quantization curve S N+1 3 In the high level or low level area, there is at most one N-th level folded quantization curve S N 1 or S N 3, and the zero crossing point is located at the folded quantization curve S N+1 3The middle of adjacent zero crossings.

7. The pipelined folding interpolation analog-to-digital converter according to claim 6, wherein: The two edge detection signals of the Nth stage are equivalent to: and or and 8. The pipelined folding interpolation analog-to-digital converter according to claim 6, wherein: The zero-crossing detection circuit uses the K+1th level folding quantization curve S K+1 3. K-th level folding redundancy curve S K 2 and S K 4, and the highest bit edge detection signal Synm of the K+1th level K+1 , generating two edge detection signals of the Kth level, 1≤K≤M-2.

9. The pipelined folding interpolation analog-to-digital converter according to claim 8, wherein: The two edge detection signals of the Kth stage are equivalent to: and or and 10. The pipelined folding interpolation analog-to-digital converter according to claim 6, wherein: The edge correction signal generating circuit uses the highest data bit DL of the subsequent quantization information and the original quantization information of the Nth level to generate two edge correction signals of the Nth level, which is equivalent to: and

Images