Method for calculating expansion value of circuit board and method for forming hole of multilayer circuit board

Abstract

This invention discloses a method for calculating the expansion and contraction value of a circuit board and a method for forming holes in a multilayer circuit board. The method for calculating the expansion and contraction value of the circuit board includes: a scanning step, a corner coordinate calculation step, a centroid coordinate calculation step, an average centroid coordinate calculation step, a reference corner coordinate calculation step, an allowable range definition step, and an adjustment step. The method for calculating the expansion and contraction value of the circuit board and the method for forming holes in a multilayer circuit board of this invention can significantly reduce the probability of through holes exceeding the original preset position of the core board, thereby effectively improving the manufacturing yield of multilayer circuit boards.

Description

Technical Field

[0001] This invention relates to a method for calculating the expansion and contraction value of a circuit board and a method for forming holes in a circuit board, and particularly to a method for calculating the expansion and contraction value of a multilayer circuit board and a method for forming holes in a multilayer circuit board. Background Technology

[0002] Existing multilayer circuit boards are typically made by laminating multiple core boards together. These core boards are electrically connected to each other, and multilayer circuit boards usually have at least one plated through hole (PTH) or via. The process of forming a plated through hole or via is as follows: a through hole is first formed on the multilayer circuit board, and then a conductive layer is plated into the through hole.

[0003] like Figure 1 As shown, as the wire diameter of the circuits on each core board decreases, the diameter of the through holes also decreases. Therefore, using the existing manufacturing process of multilayer circuit boards P, it is easy for the through holes H to exceed the allowable error range R of the core board where through holes are set (commonly known in the industry as deflection). This problem may cause damage to the circuits in the core board, resulting in a decrease in the manufacturing yield of multilayer circuit boards. Summary of the Invention

[0004] This invention discloses a method for calculating the expansion and contraction value of a circuit board and a method for forming holes in a multilayer circuit board. It is mainly used to improve the existing methods for calculating expansion and contraction values ​​and forming holes in multilayer circuit boards, which are prone to problems such as through holes exceeding the original preset position of the core board, thereby leading to a decrease in the manufacturing yield of multilayer circuit boards.

[0005] One embodiment of the present invention discloses a method for calculating the expansion and contraction value of a circuit board, which is executed by a processor of a circuit board forming device, so that the circuit board forming device calculates the expansion and contraction value of a multilayer circuit board before drilling a multilayer circuit board. The multilayer core board group is composed of multiple core boards stacked together, each core board having four marking units. No marking unit of the multilayer core board group completely overlaps with any other marking unit in a longitudinal direction, the longitudinal direction being parallel to the normal direction of each core board. The method for calculating the expansion and contraction value of the circuit board includes: a scan... The scanning steps are as follows: A scanning device is controlled to scan the multilayer core board assembly to obtain the marker coordinates of each marker unit of each core board; Angle coordinate calculation step: Using the four marker coordinates corresponding to each core board and the core board information corresponding to each core board, the four corner coordinates of each core board are calculated; the core board information includes at least one core board dimension; Centroid coordinate calculation step: Using the four corner coordinates of each core board, the centroid coordinate of each core board is calculated; Average centroid coordinate calculation step: Using multiple centroid coordinates, an average centroid coordinate is calculated. The calculation steps for the reference corner coordinates are as follows: Using the average centroid coordinates and standard circuit board dimensions, four reference corner coordinates are calculated; wherein, the four reference corner coordinates, connected by four virtual line segments, form a reference rectangle; A tolerance range definition is performed: using each reference corner coordinate as a center and a preset tolerance value as a radius, four initial tolerance ranges are defined; An adjustment step is performed: the average centroid coordinates and the four reference corner coordinates are adjusted to obtain optimized centroid coordinates and four optimized corner coordinates; wherein, the four optimized centroid coordinates, connected by four virtual line segments, form a reference rectangle. An optimized quadrilateral is formed; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are both not greater than an allowable deformation; wherein, four optimized allowable ranges can be defined with each optimized centroid coordinate as the center and the preset allowable value as the radius, and the total number of the initial corner coordinates falling within each optimized allowable range is not less than the total number of the initial corner coordinates falling within each initial allowable range; a calculation step: calculate the deformation of the multilayer core board assembly using the reference rectangle and the optimized quadrilateral.

[0006] One embodiment of the present invention discloses a method for forming holes in a multilayer circuit board, comprising: a preparation step: preparing a multilayer core board assembly, the multilayer core board assembly being composed of multiple core boards stacked together, wherein any one of the marking units does not completely overlap with any other marking unit in a longitudinal direction, the longitudinal direction being parallel to a normal line on a surface of the first core board; a scanning step: controlling a scanning device to scan the multilayer core board assembly to obtain a marking coordinate of each marking unit of each core board; a corner coordinate calculation step: using the four marking coordinates corresponding to each core board and core board information corresponding to each core board, calculating the four corner coordinates of each core board; the core board information includes at least a core board size; a centroid coordinate calculation step: using the four corner coordinates of each core board, calculating the centroid coordinate of each core board; an average centroid coordinate calculation step: using multiple centroid coordinates, calculating an average centroid coordinate; a reference corner coordinate calculation step: using the average centroid coordinate and a standard circuit board size information, calculating the reference corner coordinate. Four reference corner coordinates; wherein, the four reference corner coordinates, when connected by four virtual line segments, can form a reference rectangle; a tolerance range definition: using each of the reference corner coordinates as the center and a preset tolerance value as the radius, four initial tolerance ranges are defined; an adjustment step: adjusting the average centroid coordinates and the four reference corner coordinates to obtain an optimized centroid coordinates and four optimized corner coordinates; wherein, the four optimized centroid coordinates, when connected by four virtual line segments, can form an optimized quadrilateral; the optimized quadrilateral and the base The deformation of the quasi-rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are both not greater than an allowable deformation. The four allowable optimization ranges defined by each optimized centroid coordinate and the preset allowable value as the radius are not less than the total number of initial corner coordinates falling within each of the four allowable optimization ranges. A calculation step: Calculate the deformation of the multilayer core board assembly using the reference rectangle and the optimized quadrilateral.

[0007] In summary, the method for calculating the expansion and contraction value of the circuit board and the method for forming holes in the multilayer circuit board of the present invention can significantly reduce the probability of the through holes exceeding the original preset position of the core board, and can effectively improve the manufacturing yield of multilayer circuit boards.

[0008] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0009] Figure 1 This is a partial schematic diagram of an existing multilayer circuit board;

[0010] Figure 2 This is a flowchart illustrating the method for calculating the expansion and contraction value of the circuit board according to the present invention.

[0011] Figure 3 This is a schematic diagram of the multilayer core board assembly in the method for calculating the expansion and contraction value of the circuit board of the present invention.

[0012] Figure 4 This is an exploded view of the multilayer core board assembly in the method for calculating the expansion and contraction value of the circuit board of the present invention.

[0013] Figure 5 An image obtained after scanning the multilayer core board assembly of the present invention by a scanning device;

[0014] Figure 6 A schematic diagram of the scanning steps and corner coordinate calculation steps of the circuit board expansion / contraction value calculation method of the present invention executed by the processor;

[0015] Figure 7 A schematic diagram of the centroid coordinate calculation step, the average centroid coordinate calculation step, the reference corner coordinate calculation step, and the allowable range definition step of the method for calculating the expansion and contraction value of the circuit board of the present invention for the processor to execute the present invention.

[0016] Figure 8 A schematic diagram illustrating the steps for adjusting the expansion and contraction values ​​of the circuit board for the processor to execute the present invention;

[0017] Figure 9 This is a schematic diagram of the hole forming method for a multilayer circuit board according to the present invention.

[0018] Symbol Explanation

[0019] S1~S8: Process Steps

[0020] SX1~SX10: Process Steps

[0021] 100: Multilayer core board assembly

[0022] 111, 112, 113, 114: Marking units

[0023] 121, 122, 123, 124: Marker Units

[0024] 131, 132, 133, 134: Marking units

[0025] 141, 142, 143, 144: Marking units

[0026] 11A, 12A, 13A, 14A: Line Area

[0027] 11B, 12B, 13B, 14B: Non-line area

[0028] 11, 12, 13, 14: Core board

[0029] B1, B2, B3, B4: Virtual rectangles

[0030] C1: Virtual axis

[0031] C2: Virtual axis

[0032] Z: Border

[0033] C11, C12, C13, C14: Corner coordinates

[0034] C21, C22, C23, C24: Corner coordinates

[0035] C31, C32, C33, C34: Corner coordinates

[0036] C41, C42, C43, C44: Corner coordinates

[0037] G1, G2, G3, G4: Centroid coordinates

[0038] AVG: Average centroid coordinates

[0039] SG1, SG2, SG3, SG4: Reference angle coordinates

[0040] TR1, TR2, TR3, TR4: Initial allowable range Detailed Implementation

[0041] In the following description, if a specific drawing is indicated or shown in a particular drawing, it is only for emphasis in the following description, and most of the relevant content appears in that particular drawing, but it does not limit the following description to refer only to that particular drawing.

[0042] Please refer to the following: Figures 2 to 5 The method for calculating the expansion and contraction value of a circuit board according to the present invention is executed by a processor of a circuit board forming apparatus, so that the circuit board forming apparatus calculates an expansion and contraction value of a multilayer core board assembly before drilling a multilayer core board assembly. The multilayer core board assembly is composed of multiple core boards stacked together, each core board having four marking units, and any marking unit of the multilayer core board assembly is located in a longitudinal direction (e.g., ...). Figure 3 The Z-axis direction in the model does not completely overlap with any of the marked units, and the longitudinal direction is parallel to a normal to a surface of the multilayer core board assembly.

[0043] The methods for calculating the expansion and contraction values ​​of circuit boards include:

[0044] A scanning step S11: Control a scanning device (e.g., an X-ray scanning device) to scan the multilayer core board assembly to obtain the mark coordinates of each mark unit of each core board;

[0045] Step S12 for calculating the coordinates of one corner: Using the coordinates of the four marks corresponding to each core board and the information of one core board corresponding to each core board, calculate the coordinates of the four corners of each core board; the core board information includes at least the size of one core board.

[0046] Step S13 for calculating the centroid coordinates: Calculate the centroid coordinates of each core plate using the coordinates of the four corners of each core plate.

[0047] Step S14 for calculating the average centroid coordinates: Calculate the average centroid coordinates using multiple centroid coordinates;

[0048] Step S15 for calculating the coordinates of the reference corners: Using the average centroid coordinates and the standard dimensions of a circuit board, calculate the coordinates of the four reference corners; whereby the coordinates of the four reference corners are connected by four virtual line segments to form a reference rectangle.

[0049] Step S16: Define four initial allowable ranges with each reference corner coordinate as the center and a preset allowable value as the radius.

[0050] Step S17: Adjust the average centroid coordinates and the four reference corner coordinates to obtain an optimized centroid coordinate and four optimized corner coordinates; wherein, the four optimized centroid coordinates are connected by four virtual line segments to form an optimized quadrilateral; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than an allowable deformation; wherein, four optimized allowable ranges can be defined with each optimized centroid coordinate as the center and a preset allowable value as the radius, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range.

[0051] Calculation step S18: Calculate the deformation (i.e. expansion / contraction value) of the multilayer core board assembly using the reference rectangle and optimized quadrilateral.

[0052] like Figures 3 to 5 As shown, the multilayer core board assembly 100 may contain, for example, four core boards, each with approximately the same size. It should be noted that this is for illustrative purposes only, and the example shown is a multilayer core board assembly 100 containing only four core boards. In practical applications, the multilayer core board assembly 100 may contain more than ten layers of core boards; that is, the number of core boards in the multilayer core board assembly 100 may be greater than two layers. The method by which the multiple core boards in the multilayer core board assembly 100 are fixed to each other is not limited here.

[0053] One of the wide sides of each core board 11, 12, 13, 14 can have a circuit area 11A, 12A, 13A, 14A and a non-circuit area 11B, 12B, 13B, 14B. Each circuit area 11A, 12A, 13A, 14A can have at least one circuit formed on it. The circuit in each circuit area 11A, 12A, 13A, 14A is commonly known as PCB layout. The circuit area 11A of the core board 11 is provided with four marking units 111, 112, 113, and 114, which are roughly located at the four corners of a virtual rectangle B3; the circuit area 12A of the core board 12 is provided with four marking units 121, 122, 123, and 124, which are roughly located at the four corners of a virtual rectangle B4; similarly, the four marking units 131, 132, 133, and 134 of the core board 13 are roughly located at the four corners of a virtual rectangle B1, and the four marking units 141, 142, 143, and 144 of the core board 14 are roughly located at the four corners of a virtual rectangle B2. The shapes of each virtual rectangle B1, B2, B3, and B4 can be proportionally scaled down from the shapes of each core board, and the shapes of different virtual rectangles B1, B2, B3, and B4 are formed by scaling down the shapes of the core boards at different ratios.

[0054] like Figure 4 and Figure 5 As shown, in the image obtained after the scanning device scans the multilayer core board assembly 100, the marking units 111-114, 121-124, 131-134, and 141-144 belonging to different core boards 11, 12, 13, and 14 are arranged without overlapping each other. That is to say, in the image obtained after the scanning device scans the multilayer core board assembly 100, the marking units 111-114, 121-124, 131-134, and 141-144 are arranged in a staggered manner.

[0055] In practical applications, in the scanned image obtained after the scanning device scans the multilayer core board assembly 100, the marking units 111-114 and 131-134 contained in core boards 11 and 13 can be located on the same virtual axis C1, and the marking units 121-124 and 141-144 contained in core boards 12 and 14 can be located on another virtual axis C2. The marking units 111-114 and 131-134 do not overlap on virtual axis C1, and the marking units 121-124 and 141-144 do not overlap on virtual axis C2. It should be particularly emphasized that... Figure 5The border Z shown is only used to show the approximate position of the edge of the multilayer core board assembly 100 in the scanned image, and the border Z does not represent the actual situation of the multilayer core board assembly 100 in the scanned image.

[0056] In practical applications, each marking unit can be a non-penetrating structure of the core board, and can be manufactured together with the wiring in the circuit area of ​​the core board. Of course, in special applications, each marking unit can also be a through hole that penetrates the core board.

[0057] The scanning device is not limited to X-ray scanning devices. Any scanning device with penetrating light is within the scope of application of the scanning device referred to herein. Alternatively, any scanning device that can be used to scan the multilayer core board assembly 100 to obtain the coordinates of each marked unit is also within the scope of application of the scanning device referred to in this invention.

[0058] Please see Figure 6 In the scanning step S11 and the corner coordinate calculation step S12, the processor can use the coordinates of the four marker units 111, 112, 113, 114 (121-124, 131-134, 141-144) of each core board, and the actual size data of each core board, to calculate the four corner coordinates C11, C12, C13, C14 (C21-C24, C31-C34, C41-C44) of each core board. For example, the processor can enlarge the four marker unit coordinates 111, 112, 113, 114 (121-124, 131-134, 141-144) by a predetermined ratio to obtain the four corner coordinates C11, C12, C13, C14 (C21-C24, C31-C34, C41-C44). It should be noted that, in order to clearly explain the contents of each process step of the present invention, Figures 6 to 8 In the diagram, each coordinate is indicated by a circular symbol.

[0059] like Figure 7 As shown, after the processor obtains the coordinates of the four corners C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board, when the processor executes the centroid coordinate calculation step S13, it can sum up all the X-axis coordinates of the four corners C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board and take the average value to obtain the X-axis coordinate value of the centroid coordinate G1 (G2, G3, G4), and sum up all the Y-axis coordinates of the four corners C11, C12, C13, C14 (C21~C24, C31~C34, C41~C44) of each core board and take the average value to obtain the Y-axis coordinate value of the centroid coordinate G1 (G2, G3, G4).

[0060] After the processor obtains the centroid coordinates G1 (G2, G3, G4) of each core board, when executing the average centroid coordinate calculation step S4, it can sum the X-axis coordinates of all centroid coordinates G1, G2, G3, and G4 and take the average value to obtain the average centroid coordinate AVG X-axis coordinate value, and sum the Y-axis coordinates of all centroid coordinates G1, G2, G3, and G4 and take the average value to obtain the average centroid coordinate AVG Y-axis coordinate value. After calculating the average centroid coordinate AVG, the processor can use the length and width of the circuit board in the standard size information of the circuit board to calculate four reference corner coordinates SG1, SG2, SG3, and SG4 with the average centroid coordinate AVG as the center. The four reference corner coordinates SG1, SG2, SG3, and SG4 can be connected to form the reference rectangle RE. After the processor calculates the four reference corner coordinates SG1, SG2, SG3, and SG4, the processor can define four initial allowable ranges TR1, TR2, TR3, and TR4 with each reference corner coordinate SG1, SG2, SG3, and SG4 as the center and with a predetermined allowable value as the radius.

[0061] After the processor defines four initial allowable ranges TR1, TR2, TR3, and TR4, the processor will execute adjustment step S17. When executing adjustment step S17, the processor may first determine the number of corner coordinates contained in each initial allowable range TR1, TR2, TR3, and TR4, the straight-line distance between each reference corner coordinate SG1, SG2, SG3, and SG4 and its adjacent corner coordinates, etc., and decide in which direction the average centroid coordinate AVG and the four reference corner coordinates SG1, SG2, SG3, and SG4 should be moved, so that each initial allowable range TR1, TR2, TR3, and TR4 can cover the maximum number of corner coordinates.

[0062] More specifically, such as Figure 7 As shown, after the processor completes the allowable range definition step S16, assuming the initial allowable range TR1 located in the upper left corner of the diagram contains only three corner coordinates C11, C21, and C31, while one of the corner coordinates C41 falls outside the initial allowable range TR1, and the initial allowable range TR4 located in the lower left corner of the diagram contains only three corner coordinates C14, C24, and C34, while corner coordinate C44 is not located within the initial allowable range TR4. The other two initial allowable ranges TR2 and TR3 in the diagram contain four adjacent corner coordinates C12, C22, C32, C42 and C13, C23, C33, C43, respectively.

[0063] In this case, when the processor executes adjustment step S17, it may adjust the coordinates of the two reference corners SG1 and SG4 located at the upper left and lower left corners of the figure. After the reference corner coordinates SG1 and SG4 are adjusted, the corresponding initial allowable ranges TR1 and TR4 will be adjusted synchronously. After adjusting the position of each initial allowable range TR1 and TR4, the processor will determine the number of corner coordinates contained in each initial allowable range TR1 and TR4. The processor will also determine the deformation of the rectangle formed by the four reference corner coordinates after adjustment and the reference rectangle RE along the X-axis and Y-axis, respectively. If the processor determines whether the deformation is not greater than the allowable deformation, and the adjustment of the initial allowable range can cover more corner coordinates after the reference corner coordinates of the processor are moved, but the deformation of the rectangle formed by the four reference corner coordinates after the adjustment and the reference rectangle RE in the X and Y axes is greater than the allowable deformation, then the processor will adjust the unadjusted reference corner coordinates. In order to increase the number of corner coordinates covered by each initial allowable range, the deformation of the rectangle formed by the four reference corner coordinates after the adjustment and the reference rectangle RE in the X and Y axes will not be greater than the allowable deformation.

[0064] Following on from the above, in practical applications, Figure 7 In the scenario shown, the processor can first calculate the horizontal and vertical distances between each corner coordinate and its adjacent initial allowable range along the X and Y axes, respectively. Then, based on the horizontal and vertical distances corresponding to each corner coordinate, it determines the movement distance of at least one corner coordinate along the X and Y axes. Specifically, as... Figure 7 As shown, in adjustment step S17, the processor may first calculate the differences between the corner coordinates C41 and C44, which are not located within the initial allowable ranges TR1 and TR4, and the corresponding initial allowable ranges TR1 and TR4 on the X and Y axes. Then, it may calculate the differences between the remaining corner coordinates and the adjacent initial allowable ranges on the X and Y axes. After that, the processor can determine whether the other corner coordinates will leave the adjacent initial allowable ranges when the initial allowable ranges TR1 and TR4 are adjusted so that the initial allowable ranges TR1 and TR4 cover the corner coordinates C41 and C44. Thus, it decides how to adjust the various reference corner coordinates.

[0065] In other words, Figure 7In the scenario shown, the processor could, for example, first attempt to adjust the reference corner coordinates SG1 and SG4 located at the top left and bottom left corners of the diagram, without adjusting the reference corner coordinates SG2 and SG3 located at the top right and bottom right corners of the diagram. This would allow the initial allowable ranges TR1 and TR4 located at the top left corner of the diagram to cover the four adjacent corner coordinates C11, C21, C31, C41 and C14, C24, C34, C44, respectively. Assuming the processor adjusts only the two reference corner coordinates SG1 and SG4 located in the diagram, it would then determine the adjusted reference corner coordinates SG1 and SG4. If the deformation of the rectangle formed by the two unadjusted reference corner coordinates SG2 and SG3, along with the reference rectangle RE, exceeds the allowable deformation range along the X and Y axes, the processor will adjust the two reference corner coordinates SG2 and SG3 located at the upper right and lower right corners of the diagram. This will ensure that the initial allowable ranges TR2 and TR3 corresponding to the two reference corner coordinates SG2 and SG3 are still within the range of the four adjacent corner coordinates. The adjustment will continue until the deformation of the rectangle formed by the four adjusted reference corner coordinates, along with the reference rectangle RE, meets the allowable deformation range along the X and Y axes. When the processor determines that the adjusted initial allowable ranges cover more adjacent corner coordinates, and the deformation of the rectangle formed by the four adjusted reference corner coordinates and the reference rectangle RE on the X and Y axes both meet the allowable deformation range, the adjusted reference corner coordinates are the optimized corner coordinates FG1, FG2, FG3, and FG4, and the adjusted initial allowable ranges are the optimized allowable ranges FR1, FR2, FR3, and FR4. The rectangle RE2 formed by connecting the four optimized corner coordinates FG1, FG2, FG3, and FG4 is the optimized quadrilateral.

[0066] It should be noted that when the processor executes adjustment step S17, it may first adjust the four reference corner coordinates SG1, SG2, SG3, and SG4 without changing the shape of the reference rectangle (for example, by simultaneously translating the four reference corner coordinates SG1, SG2, SG3, and SG4 in the X-axis direction, simultaneously translating the four reference corner coordinates SG1, SG2, SG3, and SG4 in the Y-axis direction, and rotating the four reference corner coordinates SG1, SG2, SG3, and SG4 around the average centroid coordinate AVG) to attempt to increase the number of adjacent corner coordinates covered by the four initial allowable ranges TR1, TR2, TR3, and TR4. If the processor fails to increase the number of adjacent corner coordinates covered by the four initial allowable ranges TR1, TR2, TR3, and TR4 after trying, then the processor will attempt to adjust at least one reference corner coordinate SG1, SG2, SG3, and SG4 individually.

[0067] Please see Figure 9This is a flowchart illustrating the hole-forming method for a multilayer circuit board according to the present invention. The hole-forming method for a multilayer circuit board according to the present invention includes the following steps:

[0068] Preparation step SX1: Prepare a multi-layer core board assembly, which consists of multiple core boards stacked together. Any marking unit is located in a longitudinal direction (e.g., ...). Figure 3 The Z-axis direction in the middle does not completely overlap with any of the marking units, and the longitudinal direction is parallel to a normal of a surface of the multilayer core board assembly (e.g., the wide side 11A of the first core board 11).

[0069] Scanning step SX2: Control a scanning device to scan the multilayer core board group to obtain the mark coordinates of each mark unit of each core board;

[0070] Step SX3 for calculating the coordinates of one corner: Calculate the coordinates of the four corners of each core board using the coordinates of the four markers corresponding to each core board and the core board information corresponding to each core board; the core board information should include at least the core board size.

[0071] Step SX4 for calculating the centroid coordinates: Calculate the centroid coordinates of each core plate using the coordinates of the four corners of each core plate.

[0072] Step SX5 for calculating an average centroid coordinate: Calculate an average centroid coordinate using multiple centroid coordinates;

[0073] Step SX6 for calculating the coordinates of the reference corners: Using the average centroid coordinates and the standard dimensions of a circuit board, calculate the coordinates of the four reference corners; whereby the coordinates of the four reference corners are connected by four virtual line segments, a reference rectangle can be formed.

[0074] SX7: Define four initial allowable ranges with each reference corner coordinate as the center and a preset allowable value as the radius.

[0075] Step SX8: Adjust the average centroid coordinates and the four reference corner coordinates to obtain an optimized centroid coordinate and four optimized corner coordinates; wherein, the four optimized centroid coordinates are connected by four virtual line segments to form an optimized quadrilateral; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than an allowable deformation; wherein, four optimized allowable ranges can be defined with each optimized centroid coordinate as the center and a preset allowable value as the radius, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range.

[0076] Calculation step SX9: Calculate the deformation (i.e. expansion / contraction value) of the multilayer core board assembly using the reference rectangle and optimized quadrilateral;

[0077] A forming step SX10: Control a hole forming device (e.g., a laser perforation device) to form at least one hole in the multilayer core board assembly based on the deformation amount and the hole location information of a circuit board, so that the multilayer core board assembly becomes a multilayer circuit board.

[0078] The scanning steps SX2, corner coordinate calculation steps SX3, centroid coordinate calculation steps SX4, average centroid coordinate calculation steps SX5, reference corner coordinate calculation steps SX6, allowable range definition SX7, and adjustment steps SX8 in this embodiment are the same as the aforementioned scanning steps S2, corner coordinate calculation steps S3, centroid coordinate calculation steps S4, average centroid coordinate calculation steps S5, reference corner coordinate calculation steps S6, allowable range definition S7, and adjustment steps S8, and will not be described again here.

[0079] In the molding step SX10, through holes or blind holes can be formed on the multilayer core board assembly using a hole forming device as needed, and there is no limitation thereto.

[0080] In summary, the circuit board expansion and contraction calculation method and the multilayer circuit board hole forming method of the present invention can better calculate the circuit board expansion and contraction value. As a result, the probability of problems such as deflection breakage when the hole forming equipment forms blind holes or through holes on the multilayer core board assembly can be greatly reduced.

[0081] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included within the protection scope of the present invention.

Claims

1. A method for calculating the expansion and contraction value of a circuit board, executed by a processor of a circuit board forming equipment, so that the circuit board forming equipment calculates the expansion and contraction value of a multilayer core board assembly before drilling holes in the assembly, wherein the multilayer core board assembly is composed of multiple core boards stacked together, each core board having four marking units, wherein any marking unit of the multilayer core board assembly does not completely overlap with any other marking unit in the longitudinal direction, and the longitudinal direction is parallel to the normal to the surface of the multilayer core board assembly; the method for calculating the expansion and contraction value of the circuit board includes: Scanning steps: Control the scanning device to scan the multilayer core board assembly to obtain the mark coordinates of each mark unit of each core board; Corner coordinate calculation steps: Using the four marked coordinates corresponding to each core board and the core board information corresponding to each core board, calculate the coordinates of the four corners of each core board; the core board information includes at least one core board dimension; Centroid coordinate calculation steps: Calculate the centroid coordinates of each core plate using the coordinates of its four corners; The steps for calculating the average centroid coordinates are as follows: Calculate the average centroid coordinates using multiple centroid coordinates. The steps for calculating the reference corner coordinates are as follows: using the average centroid coordinates and the standard size information of the circuit board, the coordinates of the four reference corners are calculated; wherein, the four reference corner coordinates are connected by four virtual line segments to form a reference rectangle; Permissible range definition steps: Using the coordinates of each of the aforementioned reference corners as the center, and with a preset permissible value as the radius, four initial permissible ranges are defined; Adjustment steps: Adjust the average centroid coordinates and the four reference corner coordinates to obtain an optimized centroid coordinate and four optimized corner coordinates; wherein, the four optimized centroid coordinates are connected by four virtual line segments to form an optimized quadrilateral; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than the allowable deformation; wherein, four optimized allowable ranges can be defined with each optimized centroid coordinate as the center and the preset allowable value as the radius, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range; Calculation steps: Calculate the deformation of the multilayer core board assembly using the reference rectangle and the optimized quadrilateral.

2. The method for calculating the expansion and contraction value of a circuit board as described in claim 1, wherein, In the adjustment step, the average centroid coordinate and the four reference corner coordinates are controlled to simultaneously perform at least one of the following actions: translation in the X-axis direction, translation in the Y-axis direction, and rotation around the average centroid coordinate.

3. The method for calculating the expansion and contraction value of the circuit board as described in claim 1, wherein, The X-coordinate of the centroid coordinate of each core plate is the average of the X-coordinates of the four corner coordinates of the core plate; the Y-coordinate of the centroid coordinate of each core plate is the average of the Y-coordinates of the four corner coordinates of the core plate; the X-coordinate of the average centroid coordinate is the average of the X-coordinates of the centroid coordinates of multiple core plates; the Y-coordinate of the average centroid coordinate is the average of the Y-coordinates of the centroid coordinates of multiple core plates.

4. The method for calculating the expansion and contraction value of the circuit board as described in claim 1, wherein, In the adjustment step, the horizontal and vertical distances between each corner coordinate and the adjacent initial allowable range on the X and Y axes are calculated first. Based on the horizontal and vertical distances corresponding to each corner coordinate, the movement distance of the reference corner coordinate on the X and Y axes is determined.

5. The method for calculating the expansion and contraction value of a circuit board as described in claim 1, wherein, Each of the core boards includes a circuit area and a non-circuit area. The four marking units in each core board are formed in the non-circuit area, and each marking unit does not penetrate the core board. The four marking units of each core board are located at the four corners of a virtual rectangle. The shape of the virtual rectangle is a proportional reduction of the shape of the core board, and different virtual rectangles are formed by reducing the shape of the core board by different proportions.

6. A method for forming holes in a multilayer circuit board, comprising: Preparation steps: Prepare a multi-layer core board assembly, which is composed of multiple core boards stacked together. Each core board has four marking units. No marking unit in the multi-layer core board assembly completely overlaps with any other marking unit in the longitudinal direction. The longitudinal direction is parallel to the normal to the surface of the multi-layer core board assembly. Scanning steps: Control the scanning device to scan the multilayer core board assembly to obtain the mark coordinates of each mark unit of each core board; Corner coordinate calculation steps: Using the four marked coordinates corresponding to each core board and the core board information corresponding to each core board, calculate the coordinates of the four corners of each core board; the core board information includes at least one core board dimension; Centroid coordinate calculation steps: Calculate the centroid coordinates of each core plate using the coordinates of its four corners; The steps for calculating the average centroid coordinates are as follows: Calculate the average centroid coordinates using multiple centroid coordinates. The steps for calculating the reference corner coordinates are as follows: using the average centroid coordinates and the standard size information of the circuit board, the coordinates of the four reference corners are calculated; wherein, the four reference corner coordinates are connected by four virtual line segments to form a reference rectangle; Permissible range definition steps: Using the coordinates of each of the aforementioned reference corners as the center, and with a preset permissible value as the radius, four initial permissible ranges are defined; Adjustment steps: Adjust the average centroid coordinates and the four reference corner coordinates to obtain optimized centroid coordinates and four optimized corner coordinates; wherein, the four optimized centroid coordinates are connected by four virtual line segments to form an optimized quadrilateral; the deformation of the optimized quadrilateral and the reference rectangle in the X-axis direction and the deformation of the optimized quadrilateral and the reference rectangle in the Y-axis direction are not greater than the allowable deformation; wherein, four optimized allowable ranges can be defined with each optimized centroid coordinate as the center and the preset allowable value as the radius, and the total number of initial corner coordinates falling within each optimized allowable range is not less than the total number of initial corner coordinates falling within each initial allowable range; Calculation steps: Calculate the deformation of the multilayer core board assembly using the reference rectangle and the optimized quadrilateral; Forming step: Control the hole forming equipment to form at least one hole in the multilayer core board assembly according to the deformation amount and the circuit board hole position information, so that the multilayer core board assembly becomes a multilayer circuit board.

7. The method for forming holes in a multilayer circuit board as described in claim 6, wherein, In the adjustment step, the average center of gravity coordinate and the four reference corner coordinates are controlled to simultaneously perform at least one of the following actions: translation in the X-axis direction, translation in the Y-axis direction, and rotation around the Z-axis.

8. The method for forming holes in a multilayer circuit board as described in claim 6, wherein, The X-coordinate of the centroid coordinate of each core plate is the average of the X-coordinates of the four corner coordinates of the core plate; the Y-coordinate of the centroid coordinate of each core plate is the average of the Y-coordinates of the four corner coordinates of the core plate; the X-coordinate of the average centroid coordinate is the average of the X-coordinates of the centroid coordinates of multiple core plates; the Y-coordinate of the average centroid coordinate is the average of the Y-coordinates of the centroid coordinates of multiple core plates.

9. The method for forming holes in a multilayer circuit board as described in claim 6, wherein, In the adjustment step, the horizontal and vertical distances between each corner coordinate and the adjacent initial allowable range on the X and Y axes are calculated first. Based on the horizontal and vertical distances corresponding to each corner coordinate, the movement distance of the reference corner coordinate on the X and Y axes is determined.

10. The method for forming holes in a multilayer circuit board as described in claim 6, wherein, Each of the core boards includes a circuit area and a non-circuit area. The four marking units in each core board are formed in the non-circuit area, and each marking unit does not penetrate the core board. The four marking units of each core board are located at the four corners of a virtual rectangle. The shape of the virtual rectangle is a proportional reduction of the shape of the core board, and different virtual rectangles are formed by reducing the shape of the core board by different proportions.

Images