Three-dimensional memory devices and methods for forming the same

Abstract

Three-dimensional (3D) memory devices and methods of forming the same are disclosed. In a particular aspect, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Description

Technical Field

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of fabricating the same. Background Art

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processing and manufacturing techniques become challenging and costly. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] 3D memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals in and out of the memory array. Summary of the Invention

[0004] Disclosed herein are 3D memory devices and methods of fabricating the same.

[0005] In one aspect, a 3D memory device includes a first semiconductor component, a second semiconductor component, and an inter-component bonding layer between the first and second semiconductor components. The first semiconductor component includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and a stacked dielectric layer. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor component includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and a stacked dielectric layer. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

[0006] In another aspect, a method for forming a 3D memory device is provided. A first semiconductor substrate is provided, a first array structure is formed on the first semiconductor substrate, and a first peripheral structure is formed adjacent to the first array structure, thereby providing a first semiconductor assembly. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. A second semiconductor substrate is provided, a second array structure is formed on the second semiconductor substrate, and a second peripheral structure is formed adjacent to the second array structure, thereby providing a second semiconductor assembly. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack. The first semiconductor assembly and the second semiconductor assembly are bonded via an inter-assembly bonding layer.

[0007] In another aspect, a system includes a 3D memory device configured to store data and a memory controller that controls the 3D memory device. The 3D memory device includes a first semiconductor component, a second semiconductor component, and an inter-component bonding layer between the first and second semiconductor components. The first semiconductor component includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and a stacked dielectric layer. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor component includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and a stacked dielectric layer. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the invention.

[0009] Figure 1A A side view of a cross section of an exemplary 3D memory device is shown according to some aspects of the present disclosure.

[0010] Figure 1B shows some aspects of the present disclosure Figure 1A 3D memory device shown in FIG.

[0011] Figures 2A-2F shows some aspects of the present disclosure Figure 1A An enlarged side view of a cross-section of an exemplary 3D memory device is shown in FIG.

[0012] Figures 3A-3I A fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0013] Figure 4 A flow chart illustrating a method for forming an exemplary 3D memory device according to aspects of the present disclosure is shown.

[0014] Figure 5 A block diagram of an exemplary system having a 3D memory device according to aspects of the present disclosure is shown.

[0015] Figure 6A A diagram illustrating an exemplary memory card having a 3D memory device according to aspects of the present disclosure is shown.

[0016] Figure 6BA diagram illustrating an exemplary solid-state drive (SSD) having a 3D memory device according to aspects of the present disclosure is shown.

[0017] The present disclosure will be explained with reference to the accompanying drawings. DETAILED DESCRIPTION

[0018] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. In addition, this disclosure may also be used for various other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with one another and in ways not specifically shown in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of this disclosure.

[0019] Generally, a term can be understood, at least in part, from its usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can likewise be understood to express singular usage or to express plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of other factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0020] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “on” or “over” means not only “on something” or “over something,” but also includes the meaning of “on something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0021] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 180 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0023] As used herein, the term "layer" refers to a portion of a material including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the lower or upper structure range or the entirety. In addition, a layer may be an area of ​​a continuous structure whose thickness is less than the thickness of a homogeneous or heterogeneous continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (wherein interconnect lines and / or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

[0024] In some 3D NAND memory devices, in order to increase the storage capacity per unit area of ​​such devices, semiconductor designers may choose one or more methods, such as increasing the storage capacity of each memory cell, adding multiple layers to the semiconductor structure of the device, creating multiple levels (decks) of the semiconductor structure, increasing the number of cells by reducing the size of each memory cell, etc. These methods may be accompanied by numerous manufacturing difficulties. For example, when multiple levels of semiconductor structures are stacked to form a 3D memory device, it becomes extremely difficult to control the overlay of the channel structures of these levels. Moreover, deep etching is required through multiple levels in order to connect the channel sidewalls formed in the upper and lower channels passing through each level. However, the lack of precision in channel superposition will cause damage to the channel structure during etching, especially in the lower level, and also result in insufficient etching of the bottom layer of some channel structures. In addition, the epitaxial growth of the semiconductor material at the bottom of the channel structure also becomes difficult.

[0025] To address one or more of the aforementioned issues, the present disclosure introduces a solution in which two semiconductor components are bonded together using an inter-component bonding layer formed between the two components. Specifically, each semiconductor component may include an array structure comprising a memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers, and a peripheral structure comprising a plurality of peripheral circuits electrically connected to the memory stack. Thus, the cell density of a 3D memory device is increased without sacrificing the cell size of each memory cell, which would otherwise result in the aforementioned issues. As a result, the electrical performance of the 3D memory device can be improved.

[0026] Figure 1A A side view of a cross section of an exemplary 3D memory device 100 according to some aspects of the present disclosure is shown. In some embodiments, the 3D memory device 100 is a single chip including a first semiconductor component 110, a second semiconductor component 170, and an inter-component bonding layer 140 between the two components. The inter-component bonding layer 140 can include a first portion 141 adjacent to the first semiconductor component 110 and a second portion 147 adjacent to the second semiconductor component 170. Figure 1B shows some aspects of the present disclosure Figure 1A 1 is a side view of a portion 101 of a cross section of a 3D memory device shown in FIG. Specifically, the side view shows the first semiconductor component 110 and the first portion 141 of the inter-component bonding layer 140. Note that Figure 1A and Figure 1B , an x-axis and a y-axis are included to further illustrate the spatial relationship of components in the 3D memory device 100 having semiconductor components 110 and 170. The 3D memory device 100 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally in the x-direction (i.e., the lateral direction). As used herein, when a semiconductor component (e.g., semiconductor component 170) is positioned in the lowest plane of the semiconductor device (e.g., the 3D memory device 100) in the y-direction (i.e., the vertical direction), one component (e.g., a layer or component) of the semiconductor device is determined relative to the semiconductor component of the semiconductor device in the y-direction to determine whether it is on, above, or below another component (e.g., a layer or component) of the semiconductor device. Unless otherwise noted, the same concepts are applied throughout this disclosure to describe spatial relationships. It should also be noted that in Figure 1B In the embodiment, the first semiconductor component 110 and the first portion 141 of the inter-component bonding layer 140 are in a flipped position, which is consistent with the embodiment of the present invention. Figure 1A The opposite is true.

[0027] In some embodiments, first semiconductor component 110 includes a first array structure 112 and a first peripheral structure 114. First peripheral structure 114 can be formed separately from first array structure 112 and bonded thereto. Alternatively, first peripheral structure 114 can be formed after first array structure 112 is formed and adjacent thereto. According to some embodiments, bonding interface 116 is provided between first array structure 112 and first peripheral structure 114.

[0028] According to the present disclosure, the first peripheral structure 114 may include a substrate 111. The substrate 111 is not adjacent to the inter-component bonding layer 140 and, therefore, faces away from the inter-component bonding layer 140. The substrate 111 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The first peripheral structure 114 may also include a plurality of peripheral circuits 113 on the substrate 111, which are configured to control and sense the first semiconductor component 110 and / or the second semiconductor component 170. The peripheral circuits 113 may be any suitable digital, analog, and / or mixed-signal control and sensing circuits for facilitating the operation of the 3D memory device 100, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuit 113 may include transistors formed on substrate 111, wherein all or part of the transistors are formed in substrate 111 (e.g., below the top surface of substrate 111) and / or directly on substrate 111. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) may also be formed in substrate 111. In some embodiments, the transistors are high-speed and utilize advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It should be understood that, in some embodiments, peripheral circuit 113 may further include any other circuits compatible with advanced logic processes, including logic circuits such as processors and programmable logic devices (PLDs), or memory circuits such as static random-access memory (SRAM) and dynamic RAM (DRAM).

[0029] In some embodiments, the first semiconductor component 110 of the 3D memory device 100 further includes an interconnect layer 115 above the peripheral circuitry 113 to transmit electrical signals to and from the peripheral circuitry 113. The interconnect layer 115 may include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term interconnect may broadly include any appropriate type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 115 may further include one or more interlayer dielectric (ILD) layers (also known as intermetallic dielectric (IMD) layers) in which interconnect lines and VIA contacts may be formed. That is, the interconnect layer 115 may include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer 115 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in the interconnect layer 115 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof.

[0030] In some embodiments, the first peripheral structure 114 of the first semiconductor component 110 further includes a bonding layer 117 at the bonding interface 116 and above the interconnect layer 115 and the peripheral circuit 113. The bonding layer 117 may include a plurality of interface contacts 119 and a dielectric electrically isolating the interface contacts 119. The interface contacts 119 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the bonding layer 117 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The interface contacts 119 and the surrounding dielectric in the bonding layer 117 may be used for hybrid bonding.

[0031] Similarly, if Figure 1BAs shown, the first array structure 112 of the first semiconductor component 110 may further include a bonding layer 121 at the bonding interface 116 and above the bonding layer 117 of the first peripheral structure 114. The bonding layer 121 may include a plurality of interface contacts 123 and a dielectric electrically isolating the interface contacts 123. The interface contacts 123 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the bonding layer 121 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The interface contacts 123 and the surrounding dielectric in the bonding layer 121 may be used for hybrid bonding. According to some embodiments, the interface contacts 123 contact the interface contacts 119 of the bonding layer 117 at the bonding interface 116, thereby enabling the peripheral circuit 113 to be electrically connected to the memory stack 125, which will be discussed in detail below.

[0032] In some embodiments, the first array structure 112 can be bonded face-to-face on top of the first peripheral structure 114 at a bonding interface 116. In other embodiments, the bonding interface 116 is provided between the bonding layers 117 and 121 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 116 is the location where the bonding layers 117 and 121 meet and bond. In practice, the bonding interface 116 can be a layer having a certain thickness that includes the top surface of the bonding layer 117 of the first peripheral structure 114 and the bottom surface of the bonding layer 121 of the first array structure 112.

[0033] In some embodiments, the first array structure 112 further includes an interconnect layer (not shown) above the bonding layer 121 to transmit electrical signals. Similar to the interconnect layer 115 of the first peripheral structure 114, the interconnect layer of the first array structure 112 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may also include one or more ILD layers, and interconnect lines and VIA contacts may be formed in the ILD layer. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0034] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which the memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string may include a corresponding channel structure 124. Figure 1BAs shown, each channel structure 124 can extend vertically through a plurality of pairs, each pair including a stacked conductive layer 126 and a stacked dielectric layer 128. The interleaved stacked conductive layers 126 and stacked dielectric layers 128 are part of a memory stack 125. The number of pairs of stacked conductive layers 126 and stacked dielectric layers 128 in the memory stack 125 determines the number of memory cells in the first semiconductor component 110. It should be understood that in some embodiments, the memory stack 125 can have a multi-level architecture, such as in a 3D memory device 100 having a first semiconductor component 110 and a second semiconductor component 170, as shown. Figure 1A , which includes multiple memory levels stacked vertically on each other. The number of pairs of stacked conductive layers 126 and stacked dielectric layers 128 in each memory level can be the same or different.

[0035] The memory stack 125 may include a plurality of interleaved stacked conductive layers 126 and stacked dielectric layers 128. The stacked conductive layers 126 and stacked dielectric layers 128 in the memory stack 125 may alternate in a vertical direction. In other words, except for the stacked layers located at the top or bottom of the memory stack 125, each stacked conductive layer 126 may be adjacent to two stacked dielectric layers 128 on both sides, and each stacked dielectric layer 128 may be adjacent to two stacked conductive layers 126 on both sides. The stacked conductive layers 126 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stacked conductive layer 126 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrodes of the stacked conductive layers 126 may extend laterally to serve as word lines, terminating at one or more stepped structures in the memory stack 125. The stacked dielectric layers 128 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0036] like Figure 1B As shown, the first array structure 112 of the first semiconductor component 110 may further include a doped semiconductor layer 130 above the memory stack 125. The doped semiconductor layer 130 may include doped polysilicon and serve as a sidewall selective epitaxial growth (SEG) body surrounding the channel structure 124 and / or as a conductive layer electrically connecting the channel structure 124. Therefore, the doped semiconductor layer 130 is in contact with the channel structure 124.

[0037] In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., serving as a semiconductor channel) and a composite dielectric layer (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments, the memory film is a composite layer comprising a tunneling layer, a storage layer (also referred to as a "charge trap layer"), and a barrier layer. The remaining space in the channel hole may be partially or completely filled with a capping layer comprising a dielectric material (e.g., silicon oxide) and / or an air gap. The channel structure 124 may have a cylindrical shape (e.g., a pillar). In some embodiments, the capping layer, semiconductor channel, tunneling layer, storage layer, and barrier layer of the memory film are radially arranged in this order from the center of the pillar toward the outer surface. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). In some embodiments, the channel structure 124 further includes a channel plug 129 in the bottom portion (e.g., at the lower end) of the channel structure 124. The doped semiconductor layer 130 may be in contact with the semiconductor channel. Furthermore, the channel plug 129 may be in contact with the semiconductor channel. The channel plug 129 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 serves as a drain of the channel structure 124.

[0038] like Figure 1B As shown, each channel structure 124 can extend vertically through the interlaced stacked conductive layers 126 and stacked dielectric layers 128 of the memory stack 125 into the doped semiconductor layer 130. In some embodiments, the semiconductor channel can include a doped portion and an undoped portion. It should be understood that one or more stacked conductive layers 126 near the doped semiconductor layer 130 can each be a source select gate (SSG (source select gate), sometimes called a bottom select gate (BSG)), and the remaining stacked conductive layers 126 can include word lines. In some embodiments, one or more source select gates laterally face the doped portion. It should be understood that if the first array structure 112 includes more than one source select gate, the doped portion can extend beyond all source select gates. On the other hand, the doped portion may not extend further to face the word line. That is, according to some embodiments, the lower end of the doped portion is located vertically between the source select gate and the word line.

[0039] In some embodiments, the doped portion of the semiconductor channel comprises N-type doped polysilicon. The dopant may be any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. In some embodiments, the doping concentration of the doped portion is about 10 19 cm -3 With about 10 21 cm -3 Between, for example, 10 19 cm -3 with 10 21 cm -3 Between (for example, 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3 , any range defined by any one of these values ​​as the lower limit, or any range defined by any two of these values).

[0040] like Figure 1BAs shown, the first array structure 112 of the first semiconductor component 110 may further include one or more insulating structures 127, each of which extends vertically through the interleaved stacked conductive layers 126 and stacked dielectric layers 128 of the memory stack 125. According to some embodiments, unlike the channel structures 124 that extend further into the doped semiconductor layer 130, the insulating structures 127 stop at the bottom surface of the doped semiconductor layer 130, that is, do not extend vertically into the doped semiconductor layer 130. That is, the top surface of the insulating structure 127 may be flush with or lower than the bottom surface of the doped semiconductor layer 130. Each insulating structure 127 may also extend laterally to divide the channel structure 124 into a plurality of blocks. That is, the memory stack 125 may be divided into a plurality of memory blocks by the insulating structures 127, so that the array of channel structures 124 can be separated into each memory block. Unlike the slot structures that include front-side array common source (ACS) contacts in existing 3D NAND memory devices, according to some embodiments, the insulating structures 127 do not include any contacts therein (i.e., do not serve as source contacts) and therefore do not introduce parasitic capacitance and leakage current with the stacked conductive layer 116. In some embodiments, each insulating structure 127 includes an opening (e.g., a slot) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 127 can be filled with silicon oxide. It should be understood that in some examples, the insulating structures 127 can be partially filled with a non-dielectric material, such as polysilicon, to adjust the mechanical properties of the insulating structures 127, such as hardness and / or stress.

[0041] The top surface of the first semiconductor component 110 may include a stop layer 132. The stop layer 132 may include any suitable material having a high etch selectivity (eg, greater than about 5), such as silicon oxide, silicon nitride, or polysilicon. Figure 1B As shown, the stop layer 132 can have one or more contacts 133 that pass through the stop layer 132 and the doped semiconductor layer 130. In some embodiments, the contacts 133 are through-silicon vias (TSV) type contacts. Each contact 133 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., TiN). In some embodiments, at least one contact 133 also includes a spacer (e.g., a dielectric layer) that electrically isolates the contact 133 from the doped semiconductor layer 130.

[0042] In some embodiments, the first array structure 112 of the first semiconductor component 110 further includes peripheral contacts 135 that each extend vertically outside the memory stack 125. Each peripheral contact 135 can have a depth greater than the depth of the memory stack 125 to extend vertically from the interface contact 123 to the doped semiconductor layer 130 in the peripheral region outside the memory stack 125. In some embodiments, the peripheral contacts 135 are below and in contact with the contacts 133, so that the doped semiconductor layer in the first array structure 112 is electrically connected to the peripheral circuit 113 in the first peripheral structure 114. The peripheral contacts 135 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (e.g., TiN).

[0043] The above description uses the first semiconductor component 110 as an example. It is well understood that the second semiconductor component 170 can have the same or nearly the same components and configuration as the first semiconductor component 110. For example, the second semiconductor component 170 can similarly include a second array structure 172 and a second peripheral structure 174. The second peripheral structure 174 can be formed separately from the second array structure 172 and bonded thereto. In some embodiments, the second peripheral structure 174 and the second array structure 172 are formed simultaneously, thereby saving manufacturing time. Alternatively, the second peripheral structure 174 can be formed after the second array structure 172 is formed and adjacent thereto. A bonding interface 176 is provided between the second array structure 172 and the second peripheral structure 174, as shown in FIG. Figure 1A shown.

[0044] In some embodiments, second array structure 172 includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The relative positions of these stacked conductive layers and stacked dielectric layers can be the same as the relative positions of the stacked conductive layers and stacked dielectric layers of first array structure 112 described above. In some embodiments, second peripheral structure 174 includes a plurality of peripheral circuits electrically connected to the second memory stack of second array structure 172.

[0045] According to the present disclosure, in some embodiments, an inter-component bonding layer 140 is provided between the first semiconductor component 110 and the second semiconductor component 170. The first semiconductor component 110 and the second semiconductor component 170 can both include identical components that are symmetrical about the inter-component bonding layer 140 once the 3D memory device 100 is formed. The symmetrical relationship between identical or nearly identical components makes it easier to align the two components during the bonding process. In some embodiments, the second semiconductor component 170 includes a channel structure 184 extending through the second memory stack. The channel structure 184 can be symmetrical with the channel structure 124 about the inter-component bonding layer 140. It should be understood that in some embodiments, the channel structure 184 and the channel structure 124 do not necessarily have to be symmetrical, for example Figure 2B 、 Figure 2C and Figure 2E 1 , 100 - 2 , and 100 - 4 .

[0046] like Figure 1A As shown, within the same semiconductor device, the array structure of each semiconductor device is vertically closer to the inter-device bonding layer 140 than its corresponding peripheral structure. For example, the first array structure 112 is closer to the inter-device bonding layer 140 than the first peripheral structure 114; and the second array structure 172 is closer to the inter-device bonding layer 140 than the second peripheral structure 174. This configuration simplifies the pad-out manufacturing process, in which electrical contacts are provided to peripheral circuits on one side of the 3D memory device 100.

[0047] In some other embodiments not shown herein, in the same semiconductor component, the peripheral structure of each semiconductor component is closer to the inter-component bonding layer in the vertical direction than its corresponding array structure. For example, the first peripheral structure is closer to the inter-component bonding layer than the first array structure; the second peripheral structure is closer to the inter-component bonding layer than the second array structure. Each semiconductor component in this configuration can be formed by a transfer bonding method, wherein the peripheral structure can be formed in a second doped semiconductor layer, the second doped semiconductor layer is formed above the array structure having the first doped semiconductor layer, and a contact pad electrically contacting the peripheral structure can be formed above the peripheral structure. Therefore, the two semiconductor components can then be bonded via the inter-component bonding layer from the side of each semiconductor component having the contact pad. This configuration can have the additional benefit of reducing thermal damage to the peripheral structure and allowing the electrical path to be formed entirely of copper.

[0048] According to the present disclosure, the inter-component bonding layer 140 may include a conductive material and a dielectric material, so that the first semiconductor component 110 and the second semiconductor component 170 are electrically connected at a desired position after bonding, while being electrically isolated at other positions of the inter-component bonding layer 140. In some embodiments, the inter-component bonding layer 140 includes at least one bonding contact 143, such as Figure 1A shown.

[0049] The bonding contacts 143 may be partially or fully embedded in the bonding layer 142. In embodiments where the bonding contacts 143 are fully embedded in the bonding layer 142, as shown in FIG. Figure 1B As shown, the surface of the bonding contact 143 can be flush with the surface of the bonding layer 142 to reduce stress or even fracture of the semiconductor component formed thereon (which is caused by the unevenness of the surface of the inter-component bonding layer 140). The bonding contact 143 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. Therefore, after the two semiconductor components are bonded together in a manner in which the conductive components are aligned, at least one of the first peripheral circuits 113 of the first semiconductor component 110 can be electrically connected to at least one of the second peripheral circuits of the second semiconductor component 170 via the bonding contact 143. Conversely, in order to achieve electrical isolation between the two semiconductor components bonded by the inter-component bonding layer 140, the bonding layer 142 can be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0050] In some embodiments, the bonding contact 143 is formed at a position of the inter-component bonding layer 140 below which no memory stack 125, channel structure 124, or insulating structure 127 is vertically disposed. Figure 1B As shown. Therefore, according to the present disclosure, the bonding contact 143 can be provided in the inter-component bonding layer 140 at a position laterally away from the two memory stacks of the two semiconductor components 110 and 170. The advantage of this configuration is that the bonding contact 143 is directly located between the first and second peripheral circuits of the two semiconductor components 110 and 170, thereby eliminating unnecessary wiring and shortening signal transmission time.

[0051] In some embodiments, the inter-component bonding layer 140 includes a first portion 141 and a second portion 147 . Figure 1A As shown. The first portion 141 may be formed together with the formation of the first semiconductor component 110 or after the formation of the first semiconductor component 110. Similarly, the second portion 147 may be formed together with the formation of the second semiconductor component 170 or after the formation of the second semiconductor component 170. Figure 1BAs shown, the first portion 141 may be located above the first semiconductor component 110. Figure 1A As shown, the second portion 147 can be located above the second semiconductor component 170. In some embodiments, the second portion 147 also includes a bonding contact 146 and a layer 145. The bonding contact 146 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The bonding layer 145 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact 146 can be partially or completely embedded within the bonding layer 145. In embodiments where the bonding contact 146 is completely embedded within the bonding layer 145, the surface of the bonding contact 146 can be flush with the surface of the bonding layer 145.

[0052] When the inter-component bonding layer 140 includes two parts 141 and 147, they can be connected at the bonding interface 144 by various bonding techniques. One example of such a bonding technique is hybrid bonding. Figure 1A As shown, the bonding interface 144 may be a layer having a certain thickness, which includes the bottom surface of the bonding layer 141 of the first semiconductor component 110 and the top surface of the bonding layer 147 of the second semiconductor component 170. In some other embodiments, the two semiconductor components 110 and 170 may be bonded at the bonding interface 144 by one of other bonding techniques (e.g., anodic bonding, fusion (direct) bonding, adhesive bonding, etc.).

[0053] Through the bonding process, the bonding contacts 143 in the first portion 141 and the bonding contacts 146 in the second portion 147 contact each other in a face-to-face manner at the bonding interface 144, thereby jointly serving as an electrical connection between the peripheral contacts of the two semiconductor components 110, 170. The combined bonding contacts 143 and bonding contacts 146 can be collectively referred to as bonding contacts of the inter-component bonding layer 140. Due to this electrical connection, electrical signals such as data signals, control signals, etc. from any semiconductor component of the semiconductor components 110, 170 can be transmitted to the other semiconductor component. Therefore, the 3D memory device 100 can be operated (e.g., written, read, controlled, etc.) by leading out the contact layer through the pads on one side of the device. As shown in FIG. Figure 1A As shown, a pad lead-out contact layer 199 may be provided on one side of the first semiconductor component 110 to transmit electrical signals between the 3D memory device 100 and an external circuit. In some embodiments, the pad lead-out contact layer 199 is a BEOL type interconnect layer including one or more interconnects 198. Figure 1AAs shown, the pad lead-out contact layer 199 is not adjacent to the inter-component bonding layer 140 and is thus facing away from the inter-component bonding layer 140. Therefore, the interconnects 198 formed on the surface of the first semiconductor component 110 can be electrically connected to the peripheral circuitry in the second peripheral structure 174 of the second semiconductor component 170 through various conductive features, including the interface contacts at the bonding interface 174, the peripheral contacts in the second array structure 172, the bonding contacts 143 and 147 at the inter-component bonding layer 140, the peripheral contacts 135 in the first array structure 112 of the first semiconductor component 110, the interface contacts 119 and 123 at the bonding interface 116, and the peripheral circuitry 113 in the first peripheral structure 114. Therefore, electrical signals can be transmitted between external circuitry and various components of the 3D memory device 100, including the first peripheral structure 114, the first array structure 112, the second array structure 172, and the second peripheral structure 174.

[0054] Because more memory cells are arranged vertically in the device, the present disclosure allows the 3D memory device 100 to significantly increase the storage capacity per unit area on the lateral surface, which is at least twice the number of memory cells in a conventional 3D memory device that does not use the technology disclosed herein. Manufacturing time is also saved because each semiconductor component can be manufactured in parallel using roughly the same process and can then be easily bonded together in the final manufacturing operation. In addition, one semiconductor component can be used as a supporting substrate for another semiconductor component bonded to it because it has already achieved sufficient thickness and robustness when manufacturing is completed. These numerous benefits make the present disclosure an ideal choice for improving the cell density of 3D memory devices without sacrificing the cell size of each memory cell.

[0055] Figure 2A shows some aspects of the present disclosure Figure 1A FIG. 2 is an enlarged side view 201 of a cross section of an exemplary 3D memory device 100 shown in FIG. Figure 2A As shown, the respective channel structures of the semiconductor components 110 , 170 are identical, which has been described in detail above and will not be repeated herein.

[0056] Figure 2B An enlarged side view 202 of a cross section of another exemplary 3D memory device 100-1 according to some aspects of the present disclosure is shown. The 3D memory device 100-1 also includes a first semiconductor component 110-1 and a second semiconductor component 170-1. The first semiconductor component 110-1 may have the same components and configuration as the first semiconductor component 110 of the 3D memory device 100. Figure 2BAs shown, the second semiconductor component 170 - 1 of the 3D memory device 100 - 1 may include a channel structure 184 - 1 that is different from its corresponding channel structure in the second semiconductor component 170 of the 3D memory device 100 .

[0057] In some embodiments, the channel structure 184-1 extends vertically through the memory stack 185-1 and the semiconductor layer 178-1. That is, the channel structure 184-1 may include two parts: an upper portion surrounded by the semiconductor layer 178-1 (i.e., above the interface between the semiconductor layer 178-1 and the memory stack 185-1) and a lower portion surrounded by the memory stack 185-1 (i.e., below the interface between the semiconductor layer 178-1 and the memory stack 185-1). Similar to the channel structure 124, the channel structure 184-1 may also include a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 194-1) and a composite dielectric layer (e.g., as a memory film (not shown)). The memory film may also include a tunneling layer, a storage layer (also called a "charge trap layer"), and a blocking layer. The remaining space of the channel hole may be partially or completely filled with a capping layer including a dielectric material (e.g., silicon oxide) and / or an air gap. Channel structure 174-1 may have a cylindrical shape (eg, a pillar). According to some embodiments, the capping layer, semiconductor channel 194-1, tunneling layer, storage layer, and barrier layer of the memory film are radially arranged in this order from the center toward the outer surface of the pillar.

[0058] like Figure 2B As shown, according to some embodiments, a portion of semiconductor channel 194-1 along the sidewall of channel structure 184-1 (e.g., in an upper portion of channel structure 184-1) is in contact with sub-layer 198-1 of semiconductor layer 178-1. That is, according to some embodiments, the memory film is disconnected in an upper portion of sub-layer 198-1 of channel structure 184-1 adjacent to semiconductor layer 178-1, thereby exposing semiconductor channel 194-1 to contact surrounding sub-layer 198-1 of semiconductor layer 178-1. Figure 2B As shown in , in some embodiments, the sublayer 198-1 is a polysilicon layer doped with any suitable N-type dopant (e.g., P, Ar, Sb). The sublayer 198-1 can be formed by replacing a sacrificial layer through a slit opened from the gate line. In other embodiments not shown herein, the sublayer 198-1 is a polysilicon layer doped with any suitable P-type dopant (e.g., boron (B), gallium (Ga), and aluminum (Al)). The sublayer 198-1 can also be formed by replacing a sacrificial layer through a slit opened from the gate line, and a semiconductor plug can be formed from the semiconductor channel 194-1 through a SEG process, thereby creating a "sidewall SEG" of the channel structure 184-1. This configuration can alleviate problems such as overlay control, epitaxial layer formation, and SONO perforation.

[0059] Figure 2C An enlarged side view 203 of a cross-section of another exemplary 3D memory device 100-2 according to aspects of the present disclosure is shown. The 3D memory device 100-2 also includes a first semiconductor component 110-2 and a second semiconductor component 170-2. The first semiconductor component 110-2 can have the same components and configuration as the first semiconductor component 110 of the 3D memory device 100. The second semiconductor component 170-2 of the 3D memory device 100-2 can include a channel structure 184-2 that is different from its corresponding channel structure in the second semiconductor component 170 of the 3D memory device 100 or its corresponding channel structure in the second semiconductor component 170-1 of the 3D memory device 100-1.

[0060] like Figure 2C As shown, a semiconductor plug 195-2 can be disposed in the upper portion of the channel structure 184-2, which contacts the semiconductor channel 194-2 and serves as a channel controlled by the source select gate of the memory stack of the second semiconductor component 170-2. The semiconductor plug 195-2 can be partially embedded in the layer 178-2. In some embodiments, the semiconductor plug 195-2 and the layer 178-2 use the same single crystal silicon material, so the semiconductor plug 195-2 can be formed using the layer 178-2 through an SEG process. Therefore, the semiconductor plug 195-2 can contact the semiconductor channel 194-2. In some embodiments, the semiconductor plug 195-2 can be electrically connected to the upper portion of the semiconductor channel 194-2.

[0061] Figure 2D An enlarged side view 204 of a cross-section of another exemplary 3D memory device 100-3 according to some aspects of the present disclosure is shown. The 3D memory device 100-3 also includes a first semiconductor component 110-3 and a second semiconductor component 170-3. Both the first semiconductor component 110-3 and the second semiconductor component 170-3 can have the same components and configuration as the second semiconductor component 170-1 of the 3D memory device 100-1. Therefore, their detailed description will not be repeated here.

[0062] Figure 2EAn enlarged side view 205 of a cross section of another exemplary 3D memory device 100-4 according to some aspects of the present disclosure is shown. The 3D memory device 100-4 further includes a first semiconductor component 110-4 and a second semiconductor component 170-4. The first semiconductor component 110-4 can have the same components and configuration as the second semiconductor component 170-1 of the 3D memory device 100-1, and the second semiconductor component 170-4 can have the same components and configuration as the second semiconductor component 170-2 of the 3D memory device 100-2, and therefore, detailed descriptions thereof will not be repeated herein.

[0063] Figure 2F An enlarged side view 206 of a cross-section of another exemplary 3D memory device 100-5 according to some aspects of the present disclosure is shown. The 3D memory device 100-5 also includes a first semiconductor component 110-5 and a second semiconductor component 170-5. Both the first semiconductor component 110-5 and the second semiconductor component 170-5 can have the same components and configuration as the second semiconductor component 170-2 of the 3D memory device 100-2. Therefore, their detailed description will not be repeated here.

[0064] Figure 5 A block diagram of an exemplary system 500 having a 3D memory device according to some aspects of the present disclosure is shown. The system 500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 5 As shown, system 500 may include a host 508 and a memory system 502 having one or more 3D memory devices 504 and a memory controller 506. Host 508 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 508 may be configured to send or receive data stored in memory device 504.

[0065] The 3D memory device 504 may be any 3D memory device disclosed herein, such as Figure 1A3D memory device 100 shown in FIG. In some embodiments, each 3D memory device 504 includes NAND flash memory. Consistent with the scope of the present disclosure, the 3D memory device 504 can be manufactured by providing a first semiconductor component and a second semiconductor component, and bonding the two components via an inter-component bonding layer. The inter-component bonding layer can include a first portion adjacent to the first semiconductor component and a second portion adjacent to the second semiconductor component, each portion having a bonding contact embedded in the bonding layer of the portion. As a result, an electrical connection is established between the two semiconductor components. Therefore, the storage capacity per unit area of ​​the 3D memory device 504 can be significantly increased on the lateral surface. As a result, the electrical performance of the 3D memory device 504 can be improved, which in turn improves the performance of the memory system 502 and the system 500, for example, achieving a higher operating speed.

[0066] According to some embodiments, a memory controller 506 is coupled to the 3D memory device 504 and a host 508 and is configured to control the 3D memory device 504. The memory controller 506 can manage data stored in the 3D memory device 504 and communicate with the host 508. In some embodiments, the memory controller 506 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 506 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multi-media card (eMMC), used as a data storage device and enterprise storage array for mobile devices (e.g., smartphones, tablets, laptops, etc.). The memory controller 506 can be configured to control operations of the 3D memory device 504, such as read, erase, and program operations. The memory controller 506 may also be configured to manage various functions for data stored or to be stored in the 3D memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 may also be configured to process error correction code (ECC) for data read from or written to the 3D memory device 504. Any other suitable functions may also be performed by the memory controller 506, such as formatting the 3D memory device 504. The memory controller 506 may communicate with an external device (e.g., a host 508) according to a specific communication protocol.For example, the memory controller 506 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0067] The memory controller 506 and the one or more 3D memory devices 504 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 502 can be implemented as and packaged into different types of terminal electronic products. Figure 6A In one example shown, the memory controller 506 and the single 3D memory device 504 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 602 may further include a memory card that connects the memory card 602 to a host (e.g., Figure 5 The host 508 in the memory card connector 604 is electrically coupled. Figure 6B In another example shown, the memory controller 506 and the plurality of 3D memory devices 504 may be integrated into an SSD 606. The SSD 606 may further include a processor that interfaces the SSD 606 with a host (e.g., Figure 5 In some embodiments, the storage capacity and / or operating speed of the SSD 606 is greater than the storage capacity and / or operating speed of the memory card 602.

[0068] Figures 3A-3I A fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure is shown. Figure 4 A flow chart of a method 400 for forming an exemplary 3D memory device is shown, according to some embodiments of the present disclosure. Figures 3A-3I and Figure 4 Examples of 3D memory devices shown in include Figures 1A to 2F The 3D memory devices 100 to 100-5 shown in FIG will be described together. Figures 3A-3I and Figure 4 It should be understood that the operations shown in method 400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 4 The different orders shown are executed.

[0069] According to the present disclosure, two separate semiconductor components (hereinafter referred to as "first semiconductor component" and "second semiconductor component") are provided during the fabrication of a 3D memory device. In some embodiments, the two semiconductor components are prepared in parallel, thereby saving a considerable amount of processing time compared to preparing them sequentially.

[0070] refer to Figure 3A and Figure 4 Regarding the preparation of the first semiconductor component, method 400 begins with operation 402, in which a first semiconductor substrate 301 is provided. The first semiconductor substrate 301 may include a carrier substrate 302, a stop layer 303 formed on the carrier substrate 302, and a fill layer 304 formed above the stop layer 303. The carrier substrate 302 may be removed from the final product. The carrier substrate 302 may be part of a dummy wafer and may be made of any suitable material, such as glass, sapphire, plastic, silicon, etc., to name a few, to reduce its cost. The fill layer 304 may include polysilicon, a high-k dielectric, or a metal. As described in detail below, the stop layer 303 may act as an etch stop layer when etching the memory film of the channel structure from the front side or when removing the carrier substrate 302 from the back side. The stop layer 303 may include any dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be understood that in some examples, a pad oxide layer (eg, a silicon oxide layer) may be formed between the carrier substrate 302 and the stop layer 303 to relax stress between the different layers and avoid peeling. Figure 3AAs shown, a stop layer 303 can be formed on the carrier substrate 302 using one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). In some embodiments, a fill layer 304 is formed by depositing polysilicon or any other suitable material (e.g., a high-k dielectric or metal) on the stop layer 303 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof).

[0071] The method 400 proceeds to operation 404, where a first array structure is formed on the first semiconductor substrate 301. At the beginning of this operation, a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers may be formed as part of the first array structure on the semiconductor substrate 301. The process includes providing a dielectric stack 322, which includes a plurality of pairs of first dielectric layers 318 (referred to herein as "stacked sacrificial layers 318") and second dielectric layers 328 (referred to herein as "stacked dielectric layers 328") that may be formed above the filler layer 304, the first dielectric layers 318 and the second dielectric layers 328 being collectively referred to herein as "dielectric layer pairs". According to some embodiments, the dielectric stack 322 may include interleaved stacked sacrificial layers 318 and stacked dielectric layers 328. In some embodiments, the stacked sacrificial layers 318 are subsequently replaced by stacked conductive layers 326, which will be discussed in detail below. The stacked dielectric layers 328 and the stacked sacrificial layers 318 may be alternately deposited over the fill layer 304 on the carrier substrate 302 and the stop layer 303 to form a dielectric stack 322. In some embodiments, each stacked dielectric layer 328 comprises a silicon oxide layer, and each stacked sacrificial layer 318 comprises a silicon nitride layer. The dielectric stack 322 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, as Figure 3A As shown, a stair-step structure can be formed on the edge of the dielectric stack 322. The stair-step structure can be formed by performing multiple so-called "trim-etch" cycles on the dielectric layer pairs of the dielectric stack 322 toward the carrier substrate 302. As a result of applying repeated trim-etch cycles to the dielectric layer pairs of the dielectric stack 322, the dielectric stack 322 can have one or more sloped edges and a top dielectric layer pair that is shorter than a bottom dielectric layer pair.

[0072] In some embodiments, multiple channel structures 324 can be formed that extend vertically through the dielectric stack 322 and the filling layer 304. Each channel structure 324 can include a memory film 331 and a semiconductor channel 334. In some embodiments, to form the channel structures 324, a channel hole is formed that extends vertically through the dielectric stack 322, the filling layer 304, and the stop layer 303. The memory film 331 and the semiconductor channel 334 are sequentially formed along the sidewalls and bottom surfaces of the channel hole. Each channel hole is an opening that extends vertically through the dielectric stack 322, the filling layer 304, and the stop layer 303, stopping at the stop layer 303. In some embodiments, multiple openings are formed so that each opening becomes a location for growing a separate channel structure 324 in a later process. In some embodiments, the fabrication process for forming the channel holes of the channel structures 324 includes wet etching and / or dry etching, such as deep RIE (DRIE). The etching of the channel holes continues until stopped by the stop layer 303. In some embodiments, the etching conditions, such as etching rate and time, can be controlled to ensure that each channel hole has reached and stopped by the stop layer 303, thereby minimizing gouging variation between the channel holes and the channel structure 324 formed therein. It should be understood that, depending on the specific etch selectivity, one or more channel holes may extend into the stop layer 303 to a small extent and still be considered stopped by the stop layer 303 in the present disclosure.

[0073] In some embodiments, the memory film 331, including a barrier layer, a storage layer, and a tunneling layer, and the semiconductor channel 334 are sequentially formed along the sidewalls and bottom surface of the channel hole in this order. In some embodiments, the barrier layer, storage layer, and tunneling layer are first deposited sequentially along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory film 331. Then, a semiconductor material, such as polysilicon (e.g., undoped polysilicon), can be deposited over the tunneling layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the semiconductor channel 334. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer are sequentially deposited (a "SONO" structure) to form the barrier layer, storage layer, and tunneling layer of the memory film 331, as well as the semiconductor channel 334.

[0074] In some embodiments, a capping layer is formed in the channel hole and over the semiconductor channel 334 to completely or partially fill the channel hole (e.g., with or without an air gap). The capping layer can be formed by depositing a dielectric material (e.g., silicon oxide) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). A channel plug 329 can then be formed in the top portion of the channel hole. In some embodiments, the memory film 331, the semiconductor channel 334, and the portion of the capping layer on the top surface of the dielectric stack are removed and planarized by chemical mechanical polishing (CMP), wet etching, and / or dry etching. A recess can then be formed in the top portion of the channel hole by wet etching and / or dry etching the semiconductor channel 334 and the portion of the capping layer in the top portion of the channel hole. The channel plug 329 can then be formed by depositing a semiconductor material, such as polysilicon, into the recess using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). According to some embodiments, a channel structure 324 is thereby formed, which passes through the dielectric stack 322 , the filling layer 304 , and the stop layer 303 and stops at the stop layer 303 .

[0075] refer to Figure 3B , a plurality of dummy channel structures 305 may be provided in the substrate 301. In some embodiments, the dummy channel structures 305 are formed in regions other than the region where the channel structures 324 are located. For example, the dummy channel structures 305 may be formed in a manner that vertically extends through the stepped structure region without cutting through the stacked conductive layer 326 or the stacked dielectric layer 328. The dummy channel structures 305 may be formed by etching dummy holes and filling the dummy holes with a dielectric material. The dummy channel structures 305 may provide support for a semiconductor structure (e.g., an array structure) formed in the substrate and prevent bending of electrical wiring within the substrate.

[0076] In some embodiments, a dielectric layer is formed extending vertically through the dielectric stack 322 ( Figure 3A336 and stops at the fill layer 304. In some embodiments, the manufacturing process for forming the gap 336 includes wet etching and / or dry etching, such as DRIE. Gate replacement can then be performed through the gap 336 to replace the dielectric stack 322 with the memory stack 325. Specifically, a lateral recess (not shown) is first formed by removing the stacked sacrificial layer through the gap 336. In some embodiments, the stacked sacrificial layer 318 is removed by applying an etchant through the gap 336, thereby creating lateral recesses that are staggered between the stacked dielectric layers 328. The etchant can include any suitable etchant that selectively etches the stacked sacrificial layer 318 relative to the stacked dielectric layer 328.

[0077] In some embodiments, stacked conductive layer 326 (including a gate electrode and an adhesion layer) is deposited into the lateral recess through gap 336. In some embodiments, gate dielectric layer 337 is deposited into the lateral recess before stacked conductive layer 326, such that stacked conductive layer 326 is deposited on gate dielectric layer 337. Stacked conductive layer 326, such as a metal layer, can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, gate dielectric layer 337, such as a high-k dielectric layer, is also formed along the sidewalls and bottom of gap 336. According to some embodiments, a memory stack 325 is thereby formed, including interleaved stacked conductive layers 326 and stacked dielectric layers 328, thereby replacing dielectric stack 322.

[0078] In some embodiments, an insulating structure 306 is formed that extends vertically through the memory stack 325 and stops at the top surface of the fill layer 304. The insulating structure 306 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) into the gap 336 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fully or partially fill the gap 336 (with or without an air gap). In some embodiments, the insulating structure 336 includes a gate dielectric layer 337 (e.g., comprising a high-k dielectric) and a dielectric cap layer (not shown) (e.g., comprising silicon oxide). Although not shown, in some examples, the dielectric cap layer can partially fill the gap 336, and a polysilicon core layer (not shown) can fill the remaining space of the gap 336 as part of the insulating structure 306 to adjust the mechanical properties of the insulating structure 306, such as hardness or stress.

[0079] refer to Figure 3CAfter forming the insulating structure 306, peripheral contacts 335, local contacts (including channel local contacts 307 and wordline local contacts 308), and interface contacts 323 (e.g., MEOL contacts and / or BEOL contacts) are formed from the lower portion to the upper portion of the semiconductor substrate 301. The peripheral contacts 335, channel local contacts 307, wordline local contacts 308, and interface contacts 323 can be formed by etching contact openings using wet etching and / or dry etching (e.g., RIE), and then filling the contact openings with a conductive material using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The contact material can include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, during this operation, the upper surface of the interface contact 323 is flush with the upper surface of the semiconductor substrate 301. Thus, the basic structure of the first array structure 312 is formed.

[0080] The method 400 proceeds to operation 406, where a first peripheral structure 314 (e.g., Figure 3D ). In some embodiments, a new manufacturing technology can be used to form a first peripheral structure 314 directly above the first array structure 312 and the interface layer, wherein a plurality of peripheral circuits can be formed above the interface layer, which can in turn be formed above the first array structure. In some other embodiments, the first peripheral structure 314 can be formed separately and then bonded to the first array structure 312 at the bonding interface. In other embodiments, the first peripheral structure 314 and the first array structure 312 are formed simultaneously, thereby saving manufacturing time. In either case, according to the present disclosure, the first peripheral structure 314 is adjacent to the first array structure 312 and includes a plurality of peripheral circuits electrically connected to the memory stack 325.

[0081] refer to Figure 3D And using bonding formation as an example, after forming the first array structure 312, the first peripheral structure 314 can be bonded to the first array structure 312 at the bonding interface 316. The first peripheral structure 314 can be formed separately on a substrate, which can be a silicon substrate. A plurality of transistors can be formed on a silicon substrate using a variety of processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP) and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate by ion implantation and / or thermal diffusion, which serve as, for example, source regions and / or drain regions of the transistor. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate by wet etching and / or dry etching and thin film deposition. Transistors can form a plurality of peripheral circuits 313 of the first peripheral structure 314.

[0082] In some embodiments, an interconnect layer 315 is formed below the peripheral circuit 313 to transmit electrical signals to and from the peripheral circuit 313. The interconnect layer 315 may include a plurality of interconnects (also referred to herein as contacts), including lateral interconnects and VIA contacts. The interconnect layer 315 may also include one or more ILD layers, in which interconnects and VIA contacts may be formed. That is, the interconnect layer 315 may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer 315 may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer 315 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

[0083] In some embodiments, bonding layer 317 is formed within first peripheral structure 314 and beneath interconnect layer 315 and peripheral circuitry 313. Bonding layer 317 can include a plurality of interface contacts 319 and a dielectric electrically isolating interface contacts 319. Interface contacts 319 can include a conductive material, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​bonding layer 317 can be formed with a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Interface contacts 319 and the surrounding dielectric within bonding layer 317 can be used for hybrid bonding. To form bonding layer 317, an ILD layer is deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof); wet and / or dry etching (e.g., reactive ion etching (RIE)) is used, followed by forming interface contacts 319 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or any other suitable process, or any combination thereof).

[0084] In some embodiments, the first array structure 312 may include a bonding layer 321 adjacent to the bonding interface 316. Figure 3D As shown, bonding layer 321 includes a plurality of interface contacts 323 and a dielectric electrically isolating interface contacts 323. The composition and formation of bonding layer 321 may be the same as bonding layer 317 and thus will not be repeated herein.

[0085] In some embodiments, the first array structure 312 and the first peripheral structure 314 are bonded in a face-to-face manner so that the peripheral circuit 313 is above the memory stack 325. Bonding can include hybrid bonding. The downward-facing bonding layer 317 can be bonded to the upward-facing bonding layer 321, thereby forming a bonding interface 316 between the first array structure 312 and the first peripheral structure 314. In some embodiments, before bonding, a treatment process is applied to the bonding surface, such as plasma treatment, wet treatment and / or heat treatment. After bonding, the interface contacts 319 in the bonding layer 317 and the interface contacts 323 in the bonding layer 321 are aligned with each other and contact each other, so that the memory stack 325 and the channel structure 324 formed therethrough can be electrically connected to the peripheral circuit 313. Thus, the basic structure of the first semiconductor component 310 is formed.

[0086] refer to Figure 3E , turning the first semiconductor component 310 upside down. Subsequently, a portion of the semiconductor substrate 301 can be removed from one side of the first array structure 312 so that one or more peripheral contacts 335 in the first array structure 312 can be exposed. In some embodiments, one or more of the carrier substrate 302, the stop layer 303, and the fill layer 304 are removed. The carrier substrate 302 can be removed by CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 can be stripped. In some embodiments in which the carrier substrate 302 includes silicon and the stop layer 303 includes silicon nitride, the carrier substrate 302 is removed by silicon CMP, which can automatically stop when reaching the stop layer 303 having a material different from silicon (i.e., serving as a backside CMP stop layer). In some embodiments, the carrier substrate 302 (silicon substrate) is removed by wet etching using tetramethylammonium hydroxide (TMAH), which automatically stops when reaching the stop layer 303 having a material different from silicon (i.e., serving as a backside etch stop layer). The stop layer 303 can ensure that the carrier substrate 302 is completely removed without worrying about thickness uniformity after thinning.

[0087] In some embodiments, after removing the carrier substrate 302, the stop layer 303 is removed by using, for example, phosphoric acid wet etching, CMP, or grinding. The fill layer 304 can be removed by using, for example, dry etching and / or wet etching. As a result, portions of the channel structures 324 and the peripheral contacts 335 are exposed. The exposed portions of the channel structures 324 can include the memory film 331 (including the barrier layer, the storage layer, and the tunneling layer) associated with each channel structure 324 and the top portion of the semiconductor channel 334. In some embodiments, the exposed top portion of the semiconductor channel 334 is doped to increase conductivity. For example, a tilted ion implantation process can be performed to dope the top portion of the semiconductor channel 334 (e.g., including polysilicon) with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb) to a desired doping concentration, thereby creating a doped portion and leaving the remainder of the semiconductor channel 334 as an undoped portion.

[0088] refer to Figure 3F , a doped semiconductor layer 330 may then be formed on the surface of the semiconductor substrate 301. For example, a semiconductor layer (e.g., polysilicon) is deposited over the surface of the semiconductor substrate 301 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The deposited semiconductor layer may be doped with one or more N-type dopants (e.g., P, As, or Sb) using ion implantation and / or thermal diffusion. In some embodiments, to form the doped semiconductor layer 330, in-situ doping of N-type dopants such as P, As, or Sb is performed when the semiconductor layer is deposited over the surface of the semiconductor substrate 301. In some embodiments, a CMP process may be performed to remove any excess doped semiconductor layer 330 as needed. The doped semiconductor layer 330 may be formed to contact the channel structure 324. In some embodiments, the doped semiconductor layer 330 is formed to contact the semiconductor channel 334.

[0089] Subsequently, an ILD layer 309 may be formed on the doped semiconductor layer 330. The ILD layer 309 may be formed by depositing a dielectric material on the top surface of the doped semiconductor layer 330 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0090] refer to Figure 3G A plurality of contact openings (not shown) may be formed to expose various components on the upper surface of the first semiconductor component 310, such as the peripheral contacts 335 and the portion of the doped semiconductor layer 330 where the channel structure 324 is disposed. In some embodiments, the contact openings are formed using wet etching and / or dry etching (e.g., RIE). Figure 3GAs shown, a conductive layer is formed in the contact openings, thereby forming source contact 338 and contact 333. According to some embodiments, source contact 338 is above and in contact with doped semiconductor layer 330. In some embodiments, a conductive layer (e.g., Al or Cu) is deposited into the contact openings to fill the contact openings using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). A planarization process such as CMP may then be performed to remove excess conductive layer. Subsequently, a passivation layer 339 may be formed over contact 333 and source contact 338.

[0091] refer to Figure 3H A bonding layer 342 may be formed above and adjacent to the surface of the first semiconductor component 310 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The bonding layer 342 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. A plurality of openings may then be etched to allow bonding contacts 343 to be formed therein. In some embodiments, a conductive layer (e.g., Al or Cu) is deposited into the openings using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the contact openings. A planarization process such as CMP may then be performed to remove excess conductive layer. Thus, the bonding contacts 343 may be embedded within the bonding layer 342. Thus, a first portion 341 of the inter-component bonding layer 340 may be formed.

[0092] In some embodiments, the bonding contact 343 is formed at a position below the inter-component bonding layer 340 where no memory stack 325, channel structure 324, or insulating structure 306 is vertically disposed. Figure 3H Therefore, according to the present disclosure, a bonding contact 343 (such as a bonding contact 343) can be provided in the inter-component bonding layer 340 at a position laterally away from the two memory stacks of the two semiconductor components 310, 370. Figure 3I ). This configuration has the advantage that the bonding contact 343 is located directly between the first and second peripheral circuits of the two semiconductor components 310, 370, thereby eliminating unnecessary wiring and shortening signal transmission time.

[0093] refer to Figure 3I, method 400 proceeds to operation 412, where a second semiconductor substrate (not shown) is provided. At operation 414, a second array structure 372 can be formed on the second semiconductor substrate. The second array structure can include a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. At operation 416, a second peripheral structure 374 can be formed. The second peripheral structure 374 can be adjacent to the second array structure 372 and include a plurality of peripheral circuits electrically connected to the second memory stack. The second array structure 372 and the second peripheral structure 374 can be bonded via a bonding interface 376 to form a second semiconductor assembly 370. According to the present disclosure, the formation and configuration of the various components of the second semiconductor assembly 370 are the same as the formation and configuration of the various components of the first semiconductor assembly 310, and therefore will not be repeated herein.

[0094] In some embodiments, a bonding layer 345 can be formed over and adjacent to the surface of the second semiconductor component 370 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The bonding layer 345 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. A plurality of openings can then be etched to allow bonding contacts 346 to be formed therein. In some embodiments, a conductive layer (e.g., Al or Cu) is deposited into the openings using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the contact openings. A planarization process such as CMP can then be performed to remove excess conductive layer. Thus, the bonding contacts 346 can be embedded within the bonding layer 345. Thus, a second portion 347 of the inter-component bonding layer 340 can be formed.

[0095] Method 400 proceeds to operation 420, where the first semiconductor component 310 and the second semiconductor component 370 are bonded via the inter-component bonding layer 340. In some embodiments, a first portion 341 adjacent to the first semiconductor component 310 and a second portion 347 adjacent to the second semiconductor component 370 are bonded in a face-to-face manner at a bonding interface 344. Various bonding techniques can be used to connect the two semiconductor components 310 and 370, such as hybrid bonding, anodic bonding, fusion bonding, adhesive bonding, etc. Thus, the 3D memory device 300 according to the present disclosure is manufactured using method 400.

[0096] According to one aspect of the present disclosure, a 3D memory device includes a first semiconductor component, a second semiconductor component, and an inter-component bonding layer between the first and second semiconductor components. The first semiconductor component includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor component includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

[0097] In some embodiments, the inter-component bonding layer includes a conductive material and a dielectric material.

[0098] In some embodiments, the inter-component bonding layer includes a first portion adjacent to the first semiconductor component and a second portion adjacent to the second semiconductor component. The first portion includes a first bonding contact embedded in a first bonding layer of the first portion. The second portion includes a second bonding contact embedded in a second bonding layer of the second portion.

[0099] In some embodiments, the first bonding contact and the second bonding contact collectively serve as an electrical connection between the first semiconductor component and the second semiconductor component.

[0100] In some embodiments, at least one of the plurality of first peripheral circuits is electrically connected to at least one of the plurality of second peripheral circuits via a bonding contact of the inter-component bonding layer.

[0101] In some embodiments, the bonding contact is provided in the inter-component bonding layer at a location laterally remote from both the first memory stack and the second memory stack.

[0102] In some embodiments, the first array structure is vertically closer to the inter-component bonding layer than the first peripheral structure.

[0103] In some embodiments, the second array structure is vertically closer to the inter-component bonding layer than the second peripheral structure.

[0104] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer. The channel structure is in contact with a doped semiconductor layer disposed above the memory stack corresponding to the array structure including the channel structure.

[0105] In some embodiments, the doped semiconductor layer includes doped polysilicon.

[0106] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer, wherein the semiconductor channel along a sidewall of the channel structure contacts a sublayer of the semiconductor layer.

[0107] In some embodiments, at least one of the first array structure and the second array structure includes a channel structure having a semiconductor channel and a semiconductor plug, wherein the semiconductor plug contacts the semiconductor channel.

[0108] In some embodiments, the channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

[0109] In some embodiments, a substrate is provided on one side of one of the first semiconductor component and the second semiconductor component, the semiconductor substrate facing away from the inter-component bonding layer.

[0110] In some embodiments, a pad extraction contact layer is provided on one side of the other of the first semiconductor component and the second semiconductor component, the pad extraction contact layer facing away from the inter-component bonding layer and configured to transmit electrical signals between the 3D memory device and an external circuit.

[0111] According to another aspect of the present disclosure, a method for forming a 3D memory device is provided. A first semiconductor substrate is provided, a first array structure is formed on the first semiconductor substrate, and a first peripheral structure is formed adjacent to the first array structure, thereby providing a first semiconductor component. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. A second semiconductor substrate is provided, a second array structure is formed on the second semiconductor substrate, and a second peripheral structure is formed adjacent to the second array structure, thereby providing a second semiconductor component. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack. The first semiconductor component and the second semiconductor component are bonded via an inter-component bonding layer.

[0112] In some embodiments, the first array structure and the first peripheral structure are bonded via a first bonding interface.

[0113] In some embodiments, a portion of the first semiconductor substrate is removed from one side of the first array structure to expose one or more peripheral contacts in the first array structure.

[0114] In some embodiments, a first portion of the inter-component bonding layer is formed adjacent to the first semiconductor component. The first portion includes a first bonding contact embedded in the first bonding layer.

[0115] In some embodiments, the second array structure and the second peripheral structure are bonded via a second bonding interface.

[0116] In some embodiments, a portion of the second semiconductor substrate is removed from one side of the second array structure to expose one or more peripheral contacts in the second array structure.

[0117] In some embodiments, a second portion of the inter-component bonding layer is formed adjacent to the second semiconductor component. The second portion includes a second bonding contact embedded in the second bonding layer.

[0118] In some embodiments, the first portion and the second portion of the inter-component bonding layer are bonded.

[0119] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer. The channel structure is in contact with a doped semiconductor layer disposed above the memory stack corresponding to the array structure including the channel structure.

[0120] In some embodiments, the doped semiconductor layer includes doped polysilicon.

[0121] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer, wherein the semiconductor channel along a sidewall of the channel structure contacts a sublayer of the semiconductor layer.

[0122] In some embodiments, at least one of the first array structure and the second array structure includes a channel structure having a semiconductor channel and a semiconductor plug, wherein the semiconductor plug contacts the semiconductor channel.

[0123] In some embodiments, the channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

[0124] According to another aspect of the present disclosure, a system includes a 3D memory device configured to store data and a memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a first semiconductor component, a second semiconductor component, and an inter-component bonding layer between the first and second semiconductor components. The first semiconductor component includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor component includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

[0125] In some implementations, the system further includes a host coupled to the memory controller and configured to send or receive the data.

[0126] In some embodiments, the inter-component bonding layer includes a conductive material and a dielectric material.

[0127] In some embodiments, the inter-component bonding layer includes a first portion adjacent to the first semiconductor component and a second portion adjacent to the second semiconductor component. The first portion includes a first bonding contact embedded in a first bonding layer of the first portion. The second portion includes a second bonding contact embedded in a second bonding layer of the second portion.

[0128] In some embodiments, the first bonding contact and the second bonding contact collectively serve as an electrical connection between the first semiconductor component and the second semiconductor component.

[0129] In some embodiments, at least one of the plurality of first peripheral circuits is electrically connected to at least one of the plurality of second peripheral circuits via a bonding contact of the inter-component bonding layer.

[0130] In some embodiments, the bonding contact is provided in the inter-component bonding layer at a location laterally remote from both the first memory stack and the second memory stack.

[0131] In some embodiments, the first array structure is vertically closer to the inter-component bonding layer than the first peripheral structure.

[0132] In some embodiments, the second array structure is vertically closer to the inter-component bonding layer than the second peripheral structure.

[0133] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer. The channel structure is in contact with a doped semiconductor layer disposed above the memory stack corresponding to the array structure including the channel structure.

[0134] In some embodiments, the doped semiconductor layer includes doped polysilicon.

[0135] In some embodiments, at least one of the first and second array structures includes a channel structure extending vertically through one of the first and second memory stacks and the semiconductor layer, wherein the semiconductor channel along a sidewall of the channel structure contacts a sublayer of the semiconductor layer.

[0136] In some embodiments, at least one of the first array structure and the second array structure includes a channel structure having a semiconductor channel and a semiconductor plug, wherein the semiconductor plug contacts the semiconductor channel.

[0137] In some embodiments, the channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

[0138] In some embodiments, a substrate is provided on one side of one of the first semiconductor component and the second semiconductor component, the semiconductor substrate facing away from the inter-component bonding layer.

[0139] In some embodiments, a pad extraction contact layer is provided on one side of the other of the first semiconductor component and the second semiconductor component, the pad extraction contact layer facing away from the inter-component bonding layer and configured to transmit electrical signals between the 3D memory device and an external circuit.

[0140] The specific embodiments previously described can be readily modified and / or adapted to suit various applications. Therefore, such changes and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0141] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device comprising: A first semiconductor component comprises: a first array structure comprising a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and a first peripheral structure comprising a plurality of first peripheral circuits electrically connected to the first memory stack; The second semiconductor component comprises: a second array structure comprising a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and a second peripheral structure comprising a plurality of second peripheral circuits electrically connected to the second memory stack; and an inter-component bonding layer between the first semiconductor component and the second semiconductor component, in: The bonding contacts in the inter-component bonding layer are arranged only in a peripheral region, wherein the peripheral region is a region located outside the first memory stack and the second memory stack in a lateral direction; The first array structure further includes a first doped semiconductor layer, a channel structure extending vertically through the first memory stack, and a first insulating structure extending vertically through the first memory stack but not extending into the first doped semiconductor layer, and the second array structure further includes a second doped semiconductor layer and a second insulating structure extending vertically through the second memory stack but not extending into the second doped semiconductor layer; The first doped semiconductor layer extends laterally to the peripheral region, and the channel structure further extends beyond the first doped semiconductor layer and includes a source contact in contact with the first doped semiconductor layer; The channel structure further includes a channel plug connected to the first peripheral structure through an interface contact between the first array structure and the first peripheral structure; and The first insulating structure and the second insulating structure are symmetrical with respect to the inter-component bonding layer, and the first doped semiconductor layer and the second doped semiconductor layer are interposed between the first insulating structure and the second insulating structure.

2. The three-dimensional memory device according to claim 1, wherein: The inter-component bonding layer includes a conductive material and a dielectric material.

3. The three-dimensional memory device according to claim 1, wherein: The inter-component bonding layer includes a first portion adjacent to the first semiconductor component and a second portion adjacent to the second semiconductor component, wherein the first portion comprises a first bonding contact embedded in a first bonding layer of the first portion, and The second portion includes a second bonding contact embedded in a second bonding layer of the second portion.

4. The three-dimensional memory device according to claim 3, wherein: The first bonding contact and the second bonding contact together serve as an electrical connection between the first semiconductor component and the second semiconductor component.

5. The three-dimensional memory device according to claim 4, wherein: At least one of the plurality of first peripheral circuits is electrically connected to at least one of the plurality of second peripheral circuits via the first bonding contact and the second bonding contact of the inter-component bonding layer.

6. The three-dimensional memory device according to any one of claims 3 to 5, wherein: The first bonding contact and the second bonding contact are provided in the inter-component bonding layer at locations laterally distant from both the first memory stack and the second memory stack.

7. The three-dimensional memory device according to any one of claims 1 to 5, wherein: The first array structure is closer to the inter-component bonding layer than the first peripheral structure in a vertical direction.

8. The three-dimensional memory device according to any one of claims 1 to 5, wherein: The second array structure is closer to the inter-component bonding layer than the second peripheral structure in a vertical direction.

9. The three-dimensional memory device according to any one of claims 1 to 5, wherein: The second array structure further includes a channel structure vertically extending through the second memory stack and the second doped semiconductor layer.

10. The three-dimensional memory device according to claim 1, wherein: The first doped semiconductor layer includes doped polysilicon.

11. The three-dimensional memory device according to claim 1, wherein: in, A semiconductor channel along a sidewall of the channel structure contacts a sublayer of the first doped semiconductor layer.

12. The three-dimensional memory device according to any one of claims 1 to 5, wherein: The second array structure further includes a channel structure having a semiconductor channel and a semiconductor plug, and The semiconductor plugs in the second array structure are in contact with the semiconductor channels.

13. The three-dimensional memory device according to claim 12, wherein: The channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

14. The three-dimensional memory device according to any one of claims 1 to 5, 10 to 11, and 13, wherein: providing a substrate on one side of one of the first semiconductor component and the second semiconductor component, and The substrate faces away from the inter-component bonding layer.

15. The three-dimensional memory device according to claim 14, wherein: providing a pad lead-out contact layer on one side of the other of the first semiconductor component and the second semiconductor component, and The pad lead-out contact layer faces away from the inter-component bonding layer.

16. A method for forming a three-dimensional (3D) memory device, comprising: Providing a first semiconductor component by the following steps: providing a first semiconductor substrate; forming a first array structure on the first semiconductor substrate, wherein the first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and forming a first peripheral structure adjacent to the first array structure, wherein the first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack; Providing a second semiconductor component by the following steps: providing a second semiconductor substrate; forming a second array structure on the second semiconductor substrate, wherein the second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and forming a second peripheral structure adjacent to the second array structure, wherein the second peripheral structure includes a plurality of second peripheral circuits electrically connected to a second memory stack; and bonding the first semiconductor component and the second semiconductor component via an inter-component bonding layer; in: The bonding contacts in the inter-component bonding layer are arranged only in a peripheral region, wherein the peripheral region is a region located outside the first memory stack and the second memory stack in a lateral direction; The first array structure further includes a first doped semiconductor layer, a channel structure extending vertically through the first memory stack, and a first insulating structure extending vertically through the first memory stack but not extending into the first doped semiconductor layer, and the second array structure further includes a second doped semiconductor layer and a second insulating structure extending vertically through the second memory stack but not extending into the second doped semiconductor layer; The first doped semiconductor layer extends laterally to the peripheral region, and the channel structure further extends beyond the first doped semiconductor layer and includes a source contact in contact with the first doped semiconductor layer; The channel structure further includes a channel plug connected to the first peripheral structure through an interface contact between the first array structure and the first peripheral structure; and The first insulating structure and the second insulating structure are symmetrical with respect to the inter-component bonding layer, and the first doped semiconductor layer and the second doped semiconductor layer are interposed between the first insulating structure and the second insulating structure.

17. The method according to claim 16, wherein The first array structure and the first peripheral structure are bonded via a first bonding interface.

18. The method according to claim 17, wherein: Providing the first semiconductor component further includes: A portion of the first semiconductor substrate is removed from one side of the first array structure to expose one or more peripheral contacts in the first array structure.

19. The method according to claim 18, wherein Bonding the first semiconductor component and the second semiconductor component further includes: forming a first portion of the inter-component bonding layer adjacent to the first semiconductor component, and The first portion includes a first bonding contact embedded in a first bonding layer.

20. The method according to any one of claims 16 to 19, wherein: The second array structure and the second peripheral structure are bonded via a second bonding interface.

21. The method according to claim 20, wherein Providing a second semiconductor component further includes: A portion of the second semiconductor substrate is removed from one side of the second array structure to expose one or more peripheral contacts in the second array structure.

22. The method according to claim 21, wherein Bonding the first semiconductor component and the second semiconductor component further includes: forming a second portion of the inter-component bonding layer adjacent to a second semiconductor component, and The second portion includes a second bonding contact embedded in the second bonding layer.

23. The method according to claim 22, wherein Bonding the first semiconductor component and the second semiconductor component further includes: The first portion and the second portion of the inter-component bonding layer are bonded.

24. The method according to any one of claims 16 to 19 and 21 to 23, wherein The second array structure further includes a channel structure vertically extending through the second memory stack and the second doped semiconductor layer.

25. The method according to claim 16, wherein The first doped semiconductor layer includes doped polysilicon.

26. The method according to any one of claims 16 to 19 and 21 to 23, wherein A semiconductor channel along a sidewall of the channel structure contacts a sublayer of the first doped semiconductor layer.

27. The method according to any one of claims 16 to 19 and 21 to 23, wherein The second array structure further includes a channel structure having a semiconductor channel and a semiconductor plug, and The semiconductor plugs in the second array structure are in contact with the semiconductor channels.

28. The method according to claim 24, wherein The channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

29. A memory system comprising: A three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: A first semiconductor component comprises: a first array structure comprising a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and a first peripheral structure comprising a plurality of first peripheral circuits electrically connected to the first memory stack; The second semiconductor component comprises: a second array structure comprising a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers; and a second peripheral structure comprising a plurality of second peripheral circuits electrically connected to the second memory stack; and an inter-component bonding layer between the first semiconductor component and the second semiconductor component; and a memory controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device, in: The bonding contacts in the inter-component bonding layer are arranged only in a peripheral region, wherein the peripheral region is a region located outside the first memory stack and the second memory stack in a lateral direction; The first array structure further includes a first doped semiconductor layer, a channel structure extending vertically through the first memory stack, and a first insulating structure extending vertically through the first memory stack but not extending into the first doped semiconductor layer, and the second array structure further includes a second doped semiconductor layer and a second insulating structure extending vertically through the second memory stack but not extending into the second doped semiconductor layer; The first doped semiconductor layer extends laterally to the peripheral region, and the channel structure further extends beyond the first doped semiconductor layer and includes a source contact in contact with the first doped semiconductor layer; The channel structure further includes a channel plug connected to the first peripheral structure through an interface contact between the first array structure and the first peripheral structure; and The first insulating structure and the second insulating structure are symmetrical with respect to the inter-component bonding layer, and the first doped semiconductor layer and the second doped semiconductor layer are interposed between the first insulating structure and the second insulating structure.

30. The memory system of claim 29, further comprising a host coupled to the memory controller and configured to send or receive the data.

31. The memory system of claim 29, wherein: The inter-component bonding layer includes a conductive material and a dielectric material.

32. The memory system according to any one of claims 29 to 31, wherein: The inter-component bonding layer includes a first portion adjacent to the first semiconductor component and a second portion adjacent to the second semiconductor component, wherein the first portion comprises a first bonding contact embedded in a first bonding layer of the first portion, and The second portion includes a second bonding contact embedded in a second bonding layer of the second portion.

33. The memory system of claim 32, wherein: The first bonding contact and the second bonding contact together serve as an electrical connection between the first semiconductor component and the second semiconductor component.

34. The memory system of claim 33, wherein: At least one of the plurality of first peripheral circuits is electrically connected to at least one of the plurality of second peripheral circuits via a bonding contact of the inter-component bonding layer.

35. The memory system of claim 32, wherein: The first bonding contact and the second bonding contact are provided in the inter-component bonding layer at locations laterally distant from both the first memory stack and the second memory stack.

36. The memory system of any one of claims 29-31 and 33-35, wherein: The first array structure is closer to the inter-component bonding layer than the first peripheral structure in a vertical direction.

37. The memory system of any one of claims 29-31 and 33-35, wherein: The second array structure is closer to the inter-component bonding layer than the second peripheral structure in a vertical direction.

38. The memory system of any one of claims 29-31 and 33-35, wherein: The second array structure further includes a channel structure vertically extending through the second memory stack and the second doped semiconductor layer.

39. The memory system of claim 29, wherein: The first doped semiconductor layer includes doped polysilicon.

40. The memory system of claim 29, wherein: A semiconductor channel along a sidewall of the channel structure contacts a sublayer of the first doped semiconductor layer.

41. The memory system of any one of claims 29-31 and 33-35, wherein: The second array structure further includes a channel structure having a semiconductor channel and a semiconductor plug, and The semiconductor plugs in the second array structure are in contact with the semiconductor channels.

42. The memory system of claim 38, wherein: The channel structure of the first array structure and the channel structure of the second array structure are symmetrical about the inter-component bonding layer.

43. The memory system of any one of claims 29-31, 33-35, 39-40, and 42, wherein: providing a substrate on one side of one of the first semiconductor component and the second semiconductor component, and The substrate faces away from the inter-component bonding layer.

44. The memory system of claim 43, wherein: providing a pad lead-out contact layer on one side of the other of the first semiconductor component and the second semiconductor component, and The pad lead-out contact layer faces away from the inter-component bonding layer and is configured to transmit electrical signals between the three-dimensional memory device and an external circuit.

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