A method, system, device and readable storage medium for processing DSM commands

Abstract

A method, system, device and readable storage medium for processing DSM commands proposed by the present invention. The method includes: setting a buffer area for storing DSM commands in a post-storage memory; the pre-storage controller splits the DSM commands into multiple logical block addresses according to a preset rule and sends them to the post-storage memory in the form of a queue. After receiving them, the post-storage memory stores them in the buffer area; the post-storage controller synchronizes the logical block addresses through command logic fusion in the buffer area, and places a response instruction and a feedback signal sent to the pre-storage controller on the transmission bus; the pre-storage controller receives the response instruction and the feedback signal from the post-storage controller through the transmission bus; after the execution is completed, the pre-storage controller feeds back the end of the DSM command. The present invention effectively shortens the response time of DSM commands.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly to a method, system, device and readable storage medium for processing DSM commands. Background Art

[0002] Servers are classified into storage servers, computing servers, etc. according to functional categories. As the name implies, storage servers are mainly used for data storage, and storage technologies can be further divided into cold storage, warm storage, and hot storage. Generally speaking, hot storage generally refers to storage with relatively active access, cold storage is relative to hot storage, and generally refers to storage with less frequent access, and warm data is data between the above two situations. For example, photos taken within a month may still be frequently accessed and belong to hot storage information; photos taken several years ago, which have not been accessed for a long time, belong to cold storage information.

[0003] In recent years, the short video business has developed rapidly. Major short video companies provide users with services such as online recording, beautification, and editing. In addition to computing servers for data processing and scheduling, these services still require a large amount of high-speed memories for data reading and writing operations. Although higher bottleneck data IO bandwidth and distributed storage have been developed, which have alleviated the peak pressure to a certain extent, the server faces a large user group and the trend of rapid user growth, which undoubtedly brings greater potential challenges at present.

[0004] Traditional memory storage technologies mainly adopt the following technical solutions in responding to DSM (Dataset Management) instructions:

[0005] The host uses DSM commands to indicate the attributes of the logical block range. The attributes include the frequency of reading or writing data, the access size, and other information that can be used to optimize performance and reliability. Compatible controllers may choose not to take any measures based on the provided information. As Figure 1 shown in a DSM command format in Discard Online mode, each DSM command consists of 256 4KB LBAs. Its operating principle is as follows:

[0006] The front-end storage controller (FE) will send the 256 4KB LBAs in the DSM command to the back-end storage controller BE one by one for data synchronization LOCK, data processing, and after the instruction is completed, a response feedback is made for UNLOCK, thereby completing the entire instruction until the 256 4KB LBAs are processed.

[0007] In the above technical solution, the DSM duration is sufficient for cold storage and warm storage. However, when dealing with the scenario of instant online processing of a large user group, the front-end storage controller and the back-end storage controller may experience processing response timeouts, resulting in storage anomalies. On the user terminal, the user will be prompted that the task processing has timed out, and even fatal problems such as data corruption or loss may occur. Summary of the Invention

[0008] In view of the above problems, the purpose of the present invention is to provide a method, system, device, and readable storage medium for processing DSM commands, which effectively shortens the response time of DSM commands.

[0009] To achieve the above object, the present invention is realized through the following technical solutions: A method for processing DSM commands includes:

[0010] In the back-end memory, a buffer area for storing DSM commands is set up;

[0011] The front-end storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the back-end memory in the form of a queue. After receiving them, the back-end memory stores them in the buffer area;

[0012] The back-end storage controller synchronizes the logical block addresses through command logic fusion in the buffer area, and places the response instruction and feedback signal sent to the front-end storage controller on the transmission bus;

[0013] The front-end storage controller receives the response instruction and feedback signal from the back-end storage controller through the transmission bus; after execution is completed, the front-end storage controller feeds back the end of the DSM command.

[0014] Further, the step of setting up a buffer area for storing DSM commands in the back-end memory includes: using the logical block technology to set up a buffer area for the back-end storage controller for storing and logical fusion of the entire DSM command.

[0015] Further, the step that the front-end storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the back-end memory in the form of a queue, and after receiving them, the back-end memory stores them in the buffer area includes:

[0016] The front-end storage controller splits the DSM command into multiple logical block addresses according to a preset rule, and places the logical block addresses on the transmission bus according to the first-in-first-out queue rule. The back-end storage controller receives the DSM instruction sent by the bus and stores it in the buffer area.

[0017] Further, the preset rule is specifically:

[0018] Split a DSM command into 256 logical block addresses of 4K.

[0019] Further, the post - storage controller synchronizes the logical block addresses through command logic fusion in the buffer area, and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus, including:

[0020] The post - storage controller synchronizes 256 logical block addresses through command logic fusion in the buffer area, locks the transmission bus, updates the flash translation layer, and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus.

[0021] Further, the pre - storage controller receives the response instruction and feedback signal of the post - storage controller through the transmission bus, including:

[0022] The pre - storage controller receives the response instruction and feedback signal of the post - storage controller on the transmission bus, unlocks the transmission bus after updating the registers of the pre - storage controller.

[0023] Correspondingly, the present invention also discloses a DSM command processing system, including:

[0024] A buffer area setting unit, configured to set a buffer area for storing DSM commands in the post - memory;

[0025] A transmission unit, configured to split the DSM command into multiple logical block addresses according to a preset rule through the pre - storage controller and send them to the post - memory in a queue form. After receiving, the post - memory stores them in the buffer area;

[0026] A response unit, configured to control the post - storage controller to synchronize the logical block addresses through command logic fusion in the buffer area, and place the response instruction and feedback signal sent to the pre - storage controller on the transmission bus; A receiving unit, configured to control the pre - storage controller to receive the response instruction and feedback signal of the post - storage controller through the transmission bus.

[0027] Further, the system further includes:

[0028] A bus control unit, configured to lock or unlock the transmission bus;

[0029] An update unit, configured to update the flash translation layer.

[0030] Correspondingly, the present invention discloses a DSM command processing device, including:

[0031] A memory, configured to store a processing program of the DSM command;

[0032] A processor, configured to implement the steps of the DSM command processing method as described in any one of the above when executing the processing program of the DSM command.

[0033] Correspondingly, the present invention discloses a readable storage medium, on which a processing program for DSM commands is stored. When the processing program for DSM commands is executed by a processor, the steps of the processing method for DSM commands described in any one of the above are implemented.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention discloses a processing method, system, device and readable storage medium for DSM commands, which can increase the response and feedback actions of the logical block address of the DSM command by adding a buffer area, integrate the processing mechanism of its logical block address, and greatly reduce the response time after eliminating the repeated response actions. It provides an efficient idea for the instantaneous online processing scenario of a large user group.

[0035] It can be seen that, compared with the prior art, the present invention has outstanding substantive features and significant progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0037] Figure 1 It is a schematic diagram of the DSM command format in the Discard Online mode in the background art of the present invention.

[0038] Figure 2 It is a flowchart of the method in the specific implementation manner of the present invention.

[0039] Figure 3 It is a system structure diagram of the specific implementation manner of the present invention.

[0040] In the figure, 1. buffer area setting unit; 2. transmission unit; 3. response unit; 4. receiving unit; 5. bus control unit; 6. update unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The core of the present invention is to provide a processing method for DSM commands. In the prior art, when the storage controller processes DSM commands in the Discard Online mode, the processing time is too long, which cannot meet the instantaneous online processing scenario of a large user group. Due to response timeout, the user terminal will prompt the user that the task processing times out, and even fatal problems such as data corruption or loss will occur.

[0042] For the DSM command processing method provided by the present invention, first, in the post - memory, a buffer for storing DSM commands is set up. Then, the pre - storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the post - memory in the form of a queue. After receiving them, the post - memory stores them in the buffer. At this time, the post - storage controller synchronizes the logical block addresses through command logic fusion in the buffer and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus. Finally, the pre - storage controller receives the response instruction and feedback signal from the post - storage controller through the transmission bus. After the execution is completed, the pre - storage controller feeds back the end of the DSM command. Thus, it can be seen that the present invention effectively shortens the response time of the DSM command.

[0043] To enable those skilled in the art to better understand the solution of the present invention, the following further detailed description of the present invention will be given in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] Embodiment 1:

[0045] As Figure 2 shown, this embodiment provides a method for processing DSM commands, including the following steps:

[0046] S1: In the post - memory, a buffer for storing DSM commands is set up.

[0047] Specifically, the buffer is set up for the post - storage controller using the logical block technology for the storage and logical fusion of the entire DSM command.

[0048] S2: The pre - storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the post - memory in the form of a queue. After receiving them, the post - memory stores them in the buffer.

[0049] Specifically, the pre - storage controller splits a DSM command into 256 logical block addresses of 4K and places the logical block addresses on the transmission bus according to the first - in - first - out queue rule. The post - storage controller receives the DSM instruction sent by the bus and stores it in the buffer.

[0050] S3: The post - storage controller synchronizes the logical block addresses through command logic fusion in the buffer and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus.

[0051] Specifically, the post-storage controller synchronizes 256 logic block addresses in the cache area through command logic fusion, locks the transmission bus, updates the flash translation layer, and places response instructions and feedback signals to the front-storage controller on the transmission bus.

[0052] S4: The front storage controller receives the response instruction and feedback signal from the rear storage controller via the transmission bus.

[0053] The front storage controller receives the response instruction and feedback signal of the rear storage controller through the transmission bus, updates the register of the front storage controller, and then unlocks the transmission bus.

[0054] S5: After the execution is completed, the front storage controller returns the DSM command as complete.

[0055] This embodiment provides a method for processing a DSM command, which can integrate the response and feedback actions of the logical block address of the DSM command by adding a buffer area and integrating its processing mechanism of the logical block address, thereby eliminating repeated response actions and significantly reducing the response time. This provides an efficient idea for instant online processing scenarios for a large user group.

[0056] In order to better illustrate the technical effect of this method in significantly reducing the response time of DSM commands compared with the existing technology, the actual processing time of a DSM command of a company's NVME SSD is compared using two technical solutions. The details are as follows:

[0057] The single DSM instruction processing logic and mechanism provided by the prior art are as follows:

[0058] 1. The front memory controller places a DSM instruction on the receiving bus of the rear memory controller, and the rear memory controller receives the bus DSM instruction.

[0059] 2. The front storage controller transmits a single 4KB LBA command from the cache using a first-in-first-out queue rule.

[0060] 3. The post-storage controller receives LBA on the receiving bus, synchronizes, locks, updates FTL, and places command response and feedback signals on the bus;

[0061] 4. The front storage controller receives the response and feedback signal of the rear storage controller on the receiving bus, updates the register of the front storage controller, and then unlocks.

[0062] 5. After looping through steps 2-4 and completing the execution of 256 4KB LBAs, the front-end storage controller returns the DSM command and ends.

[0063] The time taken for each process when the above mechanism is used to process instructions is shown in Table 1:

[0064] Table 1-Time breakdown of the prior art for processing a single DSM instruction

[0065]

[0066]

[0067] It can be seen from Table 1 that the time it takes to actually process a DSM command using the single DSM instruction processing logic and mechanism of the prior art is about 282 ms.

[0068] The single DSM instruction processing logic and mechanism provided in this embodiment are as follows:

[0069] 1. Use logic block technology for the post-storage controller to set up a cache area for DSM instructions, which is similar to the CPU cache area and is used for storage and logic integration of the entire DSM command.

[0070] 2. The front storage controller places a complete DSM instruction in the cache area of ​​the front controller on the receiving bus of the rear storage controller according to the first-in-first-out queue rule. The rear storage controller receives the bus DSM instruction and stores it in the cache area of ​​the rear storage controller.

[0071] 3. The post-storage controller synchronizes 256 LBAs in the cache area through command logic fusion, locks the bus, updates the FTL, and places command response and feedback signals on the bus.

[0072] 4. The front storage controller receives the response and feedback signal of the rear storage controller on the receiving bus, updates the register of the front storage controller, and then changes the bus to the unlock state.

[0073] 5. After the execution is completed, the front storage controller returns the DSM command to end.

[0074] The time taken for each process when the above mechanism is used to process instructions is shown in Table 2:

[0075] Table 2-Detailed time table of the present invention for processing a single DSM instruction

[0076]

[0077] It can be seen from Table 2 that the time required to actually process a DSM command using the single DSM instruction processing logic and mechanism provided in this embodiment is about 2 ms.

[0078] It can be seen that by adding a buffer and integrating its LBA processing mechanism, the present invention eliminates 255 repeated operations, resulting in a significant reduction in the response time of a single DSM command.

[0079] Embodiment 2:

[0080] Based on Embodiment 1, as Figure 3 shown, the present invention also discloses a processing system for DSM commands, including: a buffer setting unit 1, a transmission unit 2, a response unit 3, a receiving unit 4, a bus control unit 5, and an update unit 6.

[0081] The buffer setting unit 1 is used to set a buffer for storing DSM commands in the post memory. Specifically, the buffer setting unit 1 is used to: use the logical block technology to set a buffer for the post storage controller for the storage and logical integration of the entire DSM command.

[0082] The transmission unit 2 is used to split the DSM command into multiple logical block addresses according to a preset rule through the pre-storage controller and send them to the post memory in the form of a queue. After the post memory receives it, it stores it in the buffer. Specifically, the transmission unit 2 is used to: split a DSM command into 256 logical block addresses of 4K through the pre-storage controller, and place the logical block addresses on the transmission bus according to the first-in-first-out queue rule. The post storage controller receives the DSM instruction sent by the bus transmission bus and stores it in the buffer.

[0083] The response unit 3 is used to control the post storage controller to synchronize the logical block addresses through command logic fusion in the buffer and place the response instruction and feedback signal sent to the pre-storage controller on the transmission bus.

[0084] The receiving unit 4 is used to control the pre-storage controller to receive the response instruction and feedback signal from the post storage controller through the transmission bus. Specifically, the receiving unit 4 is used to: control the pre-storage controller to receive the response instruction and feedback signal from the post storage controller through the transmission bus and update the register of the pre-storage controller.

[0085] The bus control unit 5 is used to lock or unlock the transmission bus. Specifically, the bus control unit 5 is used to: lock the transmission bus after the synchronization of the logical block addresses is completed; unlock the transmission bus after the register of the pre-storage controller is updated.

[0086] The update unit 6 is used to update the flash translation layer. Specifically, the update unit 6 is used to: update the flash translation layer after the synchronization of the logical block addresses is completed.

[0087] This embodiment provides a DSM command processing system, which can reduce the response time of DSM commands significantly by increasing a buffer area, integrating the processing mechanism of the logical block address of the DSM command, and eliminating repeated response actions for the response and feedback actions of the logical block address of the DSM command.

[0088] Embodiment Three:

[0089] This embodiment discloses a DSM command processing device, including a processor and a memory; wherein, when the processor executes the DSM command processing program stored in the memory, the following steps are implemented:

[0090] 1. In the post memory, set a buffer area for storing DSM commands.

[0091] 2. The pre-storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the post memory in the form of a queue. After receiving them, the post memory stores them in the buffer area.

[0092] 3. The post-storage controller synchronizes the logical block addresses through command logic fusion in the buffer area, and places the response instruction and feedback signal sent to the pre-storage controller on the transmission bus.

[0093] 4. The pre-storage controller receives the response instruction and feedback signal from the post-storage controller through the transmission bus.

[0094] 5. After the execution is completed, the pre-storage controller feeds back the end of the DSM command.

[0095] Furthermore, the DSM command processing device in this embodiment may further include:

[0096] An input interface, which is used to obtain the DSM command processing program imported from the outside world and save the obtained DSM command processing program to the memory, and can also be used to obtain various instructions and parameters transmitted by external terminal devices and transmit them to the processor so that the processor can perform corresponding processing using the above various instructions and parameters. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk reading interface, etc.

[0097] An output interface, which is used to output various data generated by the processor to the terminal device connected thereto, so that other terminal devices connected to the output interface can obtain various data generated by the processor. In this embodiment, the output interface may specifically include, but is not limited to, a USB interface, a serial interface, etc.

[0098] The communication unit is used to establish a remote communication connection between the DSM command processing device and the external server so that the DSM command processing device can mount the image file to the external server. In this embodiment, the communication unit may specifically include but is not limited to a remote communication unit based on wireless communication technology or wired communication technology.

[0099] The keyboard is used to obtain various parameter data or instructions input by the user by tapping the keycaps in real time.

[0100] The display is used to display the relevant information of the server power supply line short circuit locating process in real time.

[0101] The mouse can be used to assist users in inputting data and simplify user operations.

[0102] Embodiment 4:

[0103] This embodiment also discloses a readable storage medium, and the readable storage medium mentioned here includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium known in the technical field. The readable storage medium stores a processing program for a DSM command, and when the processing program for the DSM command is executed by a processor, the following steps are implemented:

[0104] 1. In the post memory, a buffer area is set up for storing DSM commands.

[0105] 2. The front storage controller splits the DSM command into multiple logical block addresses according to preset rules, and sends them to the rear storage in the form of a queue. After receiving the commands, the rear storage stores them in the cache area.

[0106] 3. The post-storage controller synchronizes the logic block address in the cache area through command logic fusion, and places the response instruction and feedback signal sent to the front-storage controller on the transmission bus.

[0107] 4. The front storage controller receives the response instruction and feedback signal from the rear storage controller through the transmission bus.

[0108] 5. After the execution is completed, the front storage controller returns the DSM command to end.

[0109] In summary, the present invention effectively shortens the response time of the DSM command.

[0110] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the methods disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the description is relatively simple. For related parts, reference can be made to the description in the method section.

[0111] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0112] In several embodiments provided by the present invention, it should be understood that the disclosed systems, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the systems or units can be in electrical, mechanical, or other forms.

[0113] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, the functional modules in each embodiment of the present invention can be integrated in a processing unit, or each module can exist physically separately, or two or more modules can be integrated in one unit.

[0115] Similarly, the processing units in each embodiment of the present invention can be integrated in a functional module, or each processing unit can exist physically, or two or more processing units can be integrated in one functional module.

[0116] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be located in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the art.

[0117] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0118] The above has introduced in detail the method, system, device and readable storage medium for processing DSM commands provided by the present invention. Specific examples are used herein to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for processing DSM commands, characterized in that, including: In the post - memory, a buffer is set for storing DSM commands; The pre - storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the post - memory in the form of a queue. After receiving them, the post - memory stores them in the buffer; The post - storage controller synchronizes the logical block addresses through command logic fusion in the buffer, and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus; The pre - storage controller receives the response instruction and feedback signal from the post - storage controller through the transmission bus; After the execution is completed, the pre - storage controller feeds back the end of the DSM command; The specific preset rule is: Split a DSM command into 256 logical block addresses of 4K; The post - storage controller synchronizes the logical block addresses through command logic fusion in the buffer, and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus, including: The post - storage controller synchronizes 256 logical block addresses through command logic fusion in the buffer, locks the transmission bus, updates the flash translation layer, and places the response instruction and feedback signal sent to the pre - storage controller on the transmission bus; The pre - storage controller receives the response instruction and feedback signal from the post - storage controller through the transmission bus, including: The pre - storage controller receives the response instruction and feedback signal from the post - storage controller on the transmission bus. After updating the registers of the pre - storage controller, it unlocks the transmission bus.

2. The method for processing DSM commands according to claim 1, wherein, The setting of the buffer for storing DSM commands in the post - memory includes: Use the logical block technology to set a buffer for the post - storage controller for the storage and logical fusion of the entire DSM command.

3. The method for processing DSM commands according to claim 1, wherein The pre - storage controller splits the DSM command into multiple logical block addresses according to a preset rule and sends them to the post - memory in the form of a queue. After receiving them, the post - memory stores them in the buffer, including: The pre - storage controller splits the DSM command into multiple logical block addresses according to a preset rule, places the logical block addresses on the transmission bus according to the first - in - first - out queue rule. The post - storage controller receives the DSM instruction sent by the bus and stores it in the buffer.

4. A processing system for DSM commands, characterized in that, including: A buffer setting unit for setting a buffer for storing DSM commands in the post - memory; A transmission unit for splitting the DSM command into multiple logical block addresses according to a preset rule through the pre - storage controller and sending them to the post - memory in the form of a queue. After receiving them, the post - memory stores them in the buffer; A response unit for controlling the post - storage controller to synchronize the logical block addresses through command logic fusion in the buffer and place the response instruction and feedback signal sent to the pre - storage controller on the transmission bus; A receiving unit for controlling the pre - storage controller to receive the response instruction and feedback signal from the post - storage controller through the transmission bus; The specific preset rule is: Split a DSM command into 256 logical block addresses of 4K; The post - storage controller synchronizes logical block addresses through command logic fusion in the buffer area, and places response instructions and feedback signals sent to the pre - storage controller on the transmission bus, including: The post - storage controller synchronizes 256 logical block addresses through command logic fusion in the buffer area, locks the transmission bus, updates the flash translation layer, and places response instructions and feedback signals sent to the pre - storage controller on the transmission bus; The pre - storage controller receives the response instructions and feedback signals of the post - storage controller through the transmission bus, including: The pre - storage controller receives the response instructions and feedback signals of the post - storage controller on the transmission bus. After updating the registers of the pre - storage controller, it unlocks the transmission bus.

5. The processing system for DSM commands according to claim 4, characterized in that, It further includes: A bus control unit for locking or unlocking the transmission bus; An update unit for updating the flash translation layer.

6. A processing device for DSM commands, characterized in that, It includes: A memory for storing the processing program of the DSM command; A processor for implementing the steps of the DSM command processing method described in any one of claims 1 to 3 when executing the processing program of the DSM command.

7. A readable storage medium, characterized in that: The processing program of the DSM command is stored on the readable storage medium. When the processing program of the DSM command is executed by the processor, the steps of the DSM command processing method described in any one of claims 1 to 3 are implemented.

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