Memory clock phase determination method and apparatus, electronic device, and storage medium

Abstract

The embodiment of the present application provides a memory clock phase determination method and device. The method comprises the following steps: according to a first to-be-tested value and a second to-be-tested value in a preset to-be-tested value set of a memory clock phase, performing Nth group tests on the memory respectively, obtaining two test results, determining a to-be-tested value of (N+1)th group test according to the number of errors in the two test results, the first to-be-tested value and the second to-be-tested value, determining a target value passed the test according to the to-be-tested value of the (N+1)th group test, so that the characteristics of the number of errors affected by the memory clock phase are utilized, the to-be-tested value of the (N+1)th group test is automatically determined according to the number of errors in the test results of the Nth group test, thereby the test range is reduced more quickly, the target value is found more quickly, the time consumption of parameter debugging of the memory clock phase of the memory is reduced, and the problem that the automatic training cannot be performed on the patch particle memory and the DDR2 memory is solved, so that the application range of the automatic adaptation of the memory clock phase is wider.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory clock phase determination method, a memory clock phase determination device, an electronic device and a readable storage medium. BACKGROUND

[0002] At present, when customizing a board card, especially a chip memory is often used on the board card, it takes a lot of time to debug some parameters required by the memory work. Some most basic parameters, for example, the grain size, the row and column address lines of the hardware, the type of the grain, the number of banks (memory banks), etc., because the parameters are relatively fixed, they can be filled according to the actual situation of the hardware and the grain.

[0003] However, some more complex parameters, for example, the memory clock phase of the memory, are considered to be more complex to test the memory timing, and cannot be done at one time, and the parameters need to be constantly tried and corrected to find the most appropriate value.

[0004] In the prior art, the memory itself has a high timing requirement, and for the board card with different hardware wiring, sometimes it is not possible to train stable parameters, and for the chip grain memory and DDR (Double Data Rate) 2 memory, it is not possible to achieve the purpose of automatic training. In summary, the parameter debugging of the memory clock phase of the memory is time-consuming and laborious, and for the chip grain memory and DDR2 memory, it is not possible to automatically train. SUMMARY

[0005] The technical problem to be solved by the embodiments of the present application is to provide a memory clock phase determination method, device, electronic device and readable storage medium, so as to solve the problem that the parameter debugging of the memory clock phase of the memory is time-consuming and laborious, and for the chip grain memory and DDR2 memory, it is not possible to automatically train.

[0006] In order to solve the above problems, the present application provides a memory clock phase determination method, comprising:

[0007] According to the first test value and the second test value in the preset test value set of the memory clock phase, the memory is respectively tested in the Nth group, and the corresponding first test result and the second test result are obtained; wherein, the N is an integer greater than or equal to 1;

[0008] According to the number of errors in the first test result and the second test result and the first test value and the second test value, the test value of the memory clock phase of the N+1th group is determined;

[0009] According to the test value of the memory clock phase of the N+1th group, the target value of the memory clock phase that passes the test is determined.

[0010] Optionally, the determining the to-be-tested value of the memory clock phase of the N+1th test according to the number of errors in the first test result and the second test result and the first to-be-tested value and the second to-be-tested value comprises:

[0011] comparing the number of errors in the first test result and the second test result;

[0012] in the case that the number of errors in the two test results is not equal, taking the average of the first to-be-tested value and the second to-be-tested value and the to-be-tested value with less errors in the first to-be-tested value and the second to-be-tested value as the two to-be-tested values of the memory clock phase of the N+1th test;

[0013] in the case that the number of errors in the two test results is equal, taking the average of the first to-be-tested value and the second to-be-tested value as the to-be-tested value of the memory clock phase of the N+1th test.

[0014] Optionally, in the case that the number of errors in the two test results is not equal, the determining the target value of the memory clock phase passing the test according to the to-be-tested value of the memory clock phase of the N+1th test comprises:

[0015] testing the memory according to the two to-be-tested values of the memory clock phase of the N+1th test respectively to obtain two corresponding test results;

[0016] in the case that the number of errors in the two test results is equal, taking the average of the two to-be-tested values of the N+1th test as the to-be-tested value of the memory clock phase of the N+2th test;

[0017] determining the target value according to the to-be-tested value of the memory clock phase of the N+2th test.

[0018] Optionally, in the case that the number of errors in the two test results is equal, the determining the target value of the memory clock phase passing the test according to the to-be-tested value of the memory clock phase of the N+1th test comprises:

[0019] testing the memory according to the to-be-tested value of the memory clock phase of the N+1th test to obtain the test result of the N+1th test;

[0020] in the case that the test result of the N+1th test indicates that the test fails, determining the to-be-tested value of the memory clock phase of the N+yth test in the preset to-be-tested value set in the order from small to large of the absolute value of the difference between the to-be-tested value of the N+1th test; wherein the y is an integer greater than or equal to 2;

[0021] determining the target value according to the to-be-tested value of the memory clock phase of the Nth+ y test.

[0022] Optionally, N = 1, one of the first to-be-tested value and the second to-be-tested value is the maximum value in the preset to-be-tested value set, and the other is the minimum value in the preset to-be-tested value set.

[0023] The application further provides a memory clock phase determination device, comprising:

[0024] a test module, configured to perform an Nth test on a memory according to a first to-be-tested value and a second to-be-tested value in a preset to-be-tested value set of a memory clock phase, and obtain a corresponding first test result and a second test result; wherein N is an integer greater than or equal to 1;

[0025] a to-be-tested value determination module, configured to determine a to-be-tested value of a memory clock phase of an Nth+1 test according to the number of errors in the first test result and the second test result and the first to-be-tested value and the second to-be-tested value;

[0026] a target value determination module, configured to determine a target value of a memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the Nth+1 test.

[0027] Optionally, the to-be-tested value determination module comprises:

[0028] a first number comparison submodule, configured to compare the number of errors in the first test result and the second test result;

[0029] a first to-be-tested value determination submodule, configured to, in a case where the number of errors in the two test results is not equal, take an average value of the first to-be-tested value and the second to-be-tested value and a to-be-tested value with a smaller number of errors in the first to-be-tested value and the second to-be-tested value as two to-be-tested values of the memory clock phase of the Nth+1 test;

[0030] a second to-be-tested value determination submodule, configured to, in a case where the number of errors in the two test results is equal, take an average value of the first to-be-tested value and the second to-be-tested value as the to-be-tested value of the memory clock phase of the Nth+1 test.

[0031] Optionally, in a case where the number of errors in the two test results is not equal, the target value determination module comprises:

[0032] a first test submodule, configured to perform a test on the memory according to the two to-be-tested values of the memory clock phase of the Nth+1 test, and obtain two corresponding test results;

[0033] a third to-be-tested value determining submodule, configured to, in a case where the number of errors in the two test results is equal, determine, as the to-be-tested value of the memory clock phase of the N+2th group of tests, an average value of the two to-be-tested values of the N+1th group of tests;

[0034] a target value determining submodule, configured to determine the target value according to the to-be-tested value of the memory clock phase of the N+2th group of tests.

[0035] Optionally, in a case where the number of errors in the two test results is equal, the target value determining module comprises:

[0036] a second test submodule, configured to test the memory according to the to-be-tested value of the memory clock phase of the N+1th group of tests, to obtain the test result of the N+1th group of tests;

[0037] a fifth to-be-tested value determining submodule, configured to, in a case where the test result of the N+1th group of tests indicates that the test fails, determine, in the preset to-be-tested value set, the to-be-tested value of the memory clock phase of the N+yth group of tests in an order from small to large according to the absolute value of the difference between the to-be-tested value of the N+1th group of tests; wherein the y is an integer greater than or equal to 2.

[0038] determine the target value according to the to-be-tested value of the memory clock phase of the N+yth group of tests.

[0039] Optionally, the N=1, and one of the first to-be-tested value and the second to-be-tested value is the maximum value in the preset to-be-tested value set, and the other is the minimum value in the preset to-be-tested value set.

[0040] The embodiment of the application further discloses an electronic device, characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.

[0041] The memory is used for storing a computer program.

[0042] The processor is used for executing the program stored on the memory, and realizes the method steps as described above.

[0043] The embodiment of the application further discloses a readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute one or more methods in the embodiment of the application.

[0044] According to the embodiment of the present application, the first test value and the second test value in the preset test value set of the memory clock phase are used to respectively perform the Nth group of tests on the memory, and the corresponding first test result and second test result are obtained. The test value of the memory clock phase of the N+1th group of tests is determined according to the number of errors in the first test result and the second test result and the first test value and the second test value. The target value of the memory clock phase that passes the test is determined according to the test value of the memory clock phase of the N+1th group of tests. In the multiple tests for finding the target value, the number of errors affected by the memory clock phase is used to automatically determine the test value of the N+1th group of tests according to the number of errors in the test result of the Nth group of tests, so that the test range is quickly narrowed, the target value is quickly found, the time consumption of the parameter debugging of the memory clock phase of the memory is reduced, and the problem that the automatic training cannot be performed on the SMD memory and the DDR2 memory is solved, so that the application range of the automatic adaptation of the memory clock phase is wider. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A step flowchart of a memory clock phase determination method provided by an embodiment of the present application is shown;

[0046] Figure 2 A schematic diagram of a modification command running flow is shown;

[0047] Figure 3 A step flowchart of a memory clock phase determination method provided by another embodiment of the present application is shown;

[0048] Figure 4 A schematic diagram of a firmware starting stage flow is shown;

[0049] Figure 5 A structure block diagram of a memory clock phase determination device embodiment provided by another embodiment of the present application is shown;

[0050] Figure 6 A structure block diagram of an electronic device for memory clock phase determination according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0051] In order to make the above-mentioned objects, features and advantages of the present application more apparent and easy to understand, the present application is further described in detail below with reference to the drawings and specific embodiments.

[0052] Reference Figure 1 A step flowchart of a memory clock phase determination method provided by an embodiment of the present application is shown, which can specifically include the following steps:

[0053] In step 101, according to a first to-be-tested value and a second to-be-tested value in a preset to-be-tested value set of the memory clock phase, the memory is tested for N groups of tests respectively, and a corresponding first test result and a second test result are obtained.

[0054] In the embodiment of the present application, in order to ensure that the memory of the electronic device can be normally accessed, it is often necessary to configure appropriate memory parameters for the memory. The memory clock phase is a memory parameter that determines the phase relationship of the memory clock relative to the command or address. Because the memory particle collects the address or command at the clock rising edge, the adjustment of the memory clock phase will result in the change of the Write leveling result. Sometimes, the Write leveling result is not ideal, and the adjustment of the memory clock phase will effectively solve the corresponding problem.

[0055] In the embodiment of the present application, the preset to-be-tested value set of the memory clock phase refers to a set composed of the to-be-tested values of the memory clock phase that are set in advance. The preset to-be-tested value set can include a plurality of to-be-tested values in a value range determined by hardware conditions, or can include a plurality of to-be-tested values set by a person. For example, the preset to-be-tested value set can include all available values in the value range 0x0-0x7F of the memory clock phase (DLL_CK*) recorded in the processor manual.

[0056] In the embodiment of the present application, the test on the memory refers to the configuration of various memory parameters (including the memory clock phase) of the memory after the initialization of the memory, the entering of the memory into the working state, and finally the output of the result reflecting the working state of the memory, which is recorded as the test result. For example, the memory test under the BIOS (Basic Input Output System, Basic Input Output System) program or the PMON (Prom Monitor, Programmable Read-Only Memory Monitor) program. After each test, a new memory clock phase is set, and the next test is restarted.

[0057] In the embodiment of the present application, in the process of searching for the target value of the memory clock phase in the preset to-be-tested value set, different to-be-tested values of the memory clock phase need to be used to test the memory for an uncertain number of times. In the Nth group of tests (N is an integer greater than or equal to 1), two to-be-tested values in the preset to-be-tested value set are recorded as a first to-be-tested value and a second to-be-tested value. The Nth group of tests includes 1 test on the memory using the first to-be-tested value as the memory clock phase, and 1 test on the memory using the second to-be-tested value as the memory clock phase. The test result obtained by using the first to-be-tested value for testing is recorded as the first test result. The test result obtained by using the second to-be-tested value for testing is recorded as the second test result.

[0058] In an optional embodiment of the present invention, N=1, where one of the first test value and the second test value is the maximum value in the preset set of test values, and the other is the minimum value in the preset set of test values.

[0059] When N=1, if the first test value is the maximum value in the preset set of test values, then the second test value is the minimum value in the preset set of test values. Alternatively, when N=1, if the second test value is the maximum value in the preset set of test values, then the first test value is the minimum value in the preset set of test values. In other words, the first set of tests starts with the maximum and minimum values ​​in the preset set of test values. Starting the test in this way usually narrows down the range of tests within the preset set of test values ​​more quickly, allowing for a faster determination of the memory clock phase.

[0060] For example, such as Figure 2 The diagram shows the test procedure (1) for the maximum and minimum values. The memory clock phase ranges from 0x0 to 0x7F. The minimum value (Min_ck) 0x0 is taken as the first test value, and the maximum value (Max_ck) 0x7F is taken as the second test value. These two parameters are tested, that is, the memory is tested once with the first test value as the memory clock phase, and then tested again with the second test value as the memory clock phase. Whether the memory tests of the two parameters pass or fail is determined. If one of the memory tests passes, the correct parameter, i.e., the target value, is obtained directly. If both memory tests fail, the number of errors reported in the test results of the two parameters is determined to be equal. If the number of errors is not equal, test procedure (2) is executed. If the number of errors is equal, test procedure (3) is executed.

[0061] In this embodiment of the invention, the first set of tests may not start with the maximum and minimum values ​​in the preset set of test values. For example, based on experience, the two endpoints of the range of memory clock phase values ​​most likely to pass the test can be selected from the preset set of test values ​​as the first test value and the second test value. Setting suitable first and second test values ​​for the first set of tests allows for a faster finding of the target value of the memory clock phase.

[0062] In this embodiment of the invention, when N is not equal to 1, the first test value and the second test value can be test values ​​determined based on the number of errors reported in the test results of the previous test group.

[0063] Step 102: Based on the number of errors reported in the first test result and the second test result, as well as the first test value and the second test value, determine the test value of the memory clock phase for the N+1th test group.

[0064] In the embodiment of the present application, it is found through research that the memory clock phase has certain regularity with the number of errors in the test results. The target value of the memory clock phase is usually closer to the test value used by the test result with less number of errors. Of course, if the number of errors in one of the first test result or the second test result is zero, the corresponding test value is directly determined as the target value of the test.

[0065] In the embodiment of the present application, the specific implementation of determining the test value of the memory clock phase of the N+1 group test according to the number of errors in the first test result and the second test result and the first test value and the second test value can include multiple modes. It can also include any applicable implementation mode, and the embodiment of the present application does not limit this.

[0066] In the embodiment of the present application, in one specific implementation of determining the test value of the memory clock phase of the N+1 test according to the number of errors in the first test result and the second test result and the first test value and the second test value, it includes: comparing the number of errors in the first test result and the second test result, in the case that the number of errors in the two test results is not equal, the average of the first test value and the second test value, and the test value with less number of errors in the first test value and the second test value, are taken as the two test values of the memory clock phase of the N+1 group test, in the case that the number of errors in the two test results is equal, the average of the first test value and the second test value is taken as the test value of the memory clock phase of the N+1 group test.

[0067] Comparing the number of errors in the first test result with the number of errors in the second test result.

[0068] If the number of errors in the first test result is more than the number of errors in the second test result, calculate the average of the first test value and the second test value, and take the average and the second test value as the two test values of the memory clock phase of the N+1 group test.

[0069] If the number of errors in the first test result is less than the number of errors in the second test result, calculate the average of the first test value and the second test value, and take the average and the first test value as the two test values of the memory clock phase of the N+1 group test.

[0070] The above-mentioned mode can quickly narrow the range of the test in the preset test value set, and quickly determine the target value of the memory clock phase, thereby reducing the time consumption of the parameter debugging of the memory clock phase of the memory.

[0071] For example, as Figure 3The schematic diagram of the test procedure (2) is shown. In the test procedure (2), if the number of errors in the test according to Max_ck is greater than the number of errors in the test according to Min_ck, Max_ck=(Max_ck+Min_ck) / 2, Min_ck=Min_ck. If the number of errors in the test according to Max_ck is less than the number of errors in the test according to Min_ck, Min_ck=(Min_ck+Max_ck) / 2, Max_ck=Max_ck. Then the new Max_ck and Min_ck are continued to be tested according to the test procedure (1). In the above description, Max_ck and Min_ck can not be the maximum and minimum of the initial range of the memory clock phase, but represent the maximum and minimum of the reduced range.

[0072] If the number of errors in the first test result and the second test result is equal, the average of the first to-be-tested value and the second to-be-tested value is calculated, and the average is taken as the to-be-tested value of the memory clock phase in the N+1th group of tests, so that the target value of the memory clock phase is approached faster, and the time consumption of the parameter debugging of the memory clock phase of the memory is reduced.

[0073] In step 103, the target value of the memory clock phase that passes the test is determined according to the to-be-tested value of the memory clock phase in the N+1th group of tests.

[0074] In the embodiment of the application, the memory is tested in the N+1th group of tests according to the to-be-tested value of the memory clock phase in the N+1th group of tests, and the corresponding test result is obtained. Specifically, a plurality of implementation manners can be included.

[0075] For example, when the to-be-tested value of the N+1th group of tests is two to-be-tested values, the memory is tested in the N+1th group of tests by using the two to-be-tested values respectively, and the corresponding two test results are obtained. If the number of errors in one of the two test results is zero, the corresponding to-be-tested value is directly determined as the target value that passes the test. If the number of errors in one of the two test results is not zero, the to-be-tested value of the memory clock phase in the N+2th group of tests is determined according to the number of errors in the two test results, and the target value of the memory clock phase that passes the test is determined according to the to-be-tested value of the memory clock phase in the N+2th group of tests. This is repeated until the target value is determined.

[0076] In an alternative embodiment of the present application, in the case that the number of errors in the two test results is not equal, a specific implementation of determining the target value of the memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the N+1th group of tests comprises: testing the memory according to the two to-be-tested values of the memory clock phase of the N+1th group of tests respectively to obtain two corresponding test results; in the case that the number of errors in the two test results is equal, taking the average of the two to-be-tested values of the N+1th group of tests as the to-be-tested value of the memory clock phase of the N+2th group of tests, and determining the target value according to the to-be-tested value of the memory clock phase of the N+2th group of tests.

[0077] As in step 101, the memory is tested according to the two to-be-tested values of the memory clock phase of the N+1th group of tests respectively to obtain two corresponding test results. The number of errors in the two test results is compared. If the number of errors in the two test results is equal, the average of the two to-be-tested values of the N+1th group of tests is calculated, and the average is taken as the to-be-tested value of the memory clock phase of the N+2th group of tests. Then the target value is determined according to the to-be-tested value of the memory clock phase of the N+2th group of tests, so as to quickly approach the target value of the memory clock phase, and the time-consuming of parameter debugging of the memory clock phase of the memory is reduced.

[0078] The specific implementation of determining the target value according to the to-be-tested value of the memory clock phase of the N+2th group of tests can be referred to the specific implementation of determining the target value of the memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the N+1th group of tests, which will not be described here.

[0079] Then, a specific implementation of determining the target value according to the to-be-tested value of the memory clock phase of the N+2th group of tests comprises: testing the memory according to the to-be-tested value of the memory clock phase of the N+2th group of tests to obtain the test result of the N+2th group of tests; in the case that the test result of the N+2th group of tests indicates that the test does not pass, determining the to-be-tested value of the memory clock phase of the N+xth group of tests in the preset to-be-tested value set in order of the absolute value of the difference between the to-be-tested value of the N+2th group of tests from small to large; wherein the x is an integer greater than or equal to 3; and determining the target value according to the to-be-tested value of the memory clock phase of the N+xth group of tests.

[0080] When the test value for the memory clock phase in the (N+2)th test group is a single value, the memory is tested based on this value to obtain the test result for the (N+2)th test group. If the number of errors in the test result is not zero, the test fails. Then, taking the test value of the (N+2)th test group as the center, new test values ​​are determined from the test values ​​on either side of the preset test value set. Specifically, in the preset test value set, test values ​​are determined sequentially in ascending order of the absolute value of the difference between the test value and the test value of the (N+2)th test group, serving as the test values ​​for the memory clock phase in the (N+x)th test group. Here, x is an integer greater than or equal to 3. The memory is then tested based on the test value for the memory clock phase of the (N+x)th test group to obtain the test result. If the number of errors in this test result is zero, the corresponding test value is directly determined as the target value for passing the test. If the number of errors in this test result is not zero, the next test value is determined sequentially in the above order, and the testing continues until the target value is determined.

[0081] For example, such as Figure 4 The diagram shows the test process (3). In test process (3), the average value Mid_ck = (Max_ck + Min_ck) / 2, and the test value of the memory clock phase in the N+x group is Ck_a or Ck_b. Initially, Ck_a = Mid_ck and Ck_b = Mid_ck. The test is performed first based on Mid_ck. If the test passes, it is determined as the target value. If the test fails, Ck_a = Ck_a + 1 and Ck_b = Ck_b - 1. The test is performed based on Ck_a or Ck_b. If the test passes, it is determined as the target value. Specifically, the test can be performed first based on Ck_a, and if the test fails, the test can be performed based on Ck_b. Or the test can be performed first based on Ck_b, and if the test fails, the test can be performed based on Ck_a. When the test is performed based on both Ck_a and Ck_b, neither test passes. Then execute Ck_a = Ck_a + 1 and Ck_b = Ck_b - 1 again. Then test according to Ck_a or Ck_b. If the test passes, it is determined as the target value. Continue in this way until the target value is determined.

[0082] For example, when the test value for group N+1 is a single test value, this single test value is used to perform the (N+1)th test on the memory, yielding a corresponding test result. If the number of errors in this test result is zero, then the corresponding test value is directly set as the target value for passing the test. If the number of errors in this test result is not zero, then a new test value is determined, and the memory is tested again until the target value for passing the test is determined.

[0083] In an alternative embodiment of the present application, in the case that the number of errors in the two test results is equal, the specific implementation of determining the target value of the memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the N+1th group of tests comprises: testing the memory according to the to-be-tested value of the memory clock phase of the N+1th group of tests to obtain the test result of the N+1th group of tests; in the case that the test result of the N+1th group of tests indicates that the test fails, determining the to-be-tested value of the memory clock phase of the N+yth group of tests in the preset to-be-tested value set in order of the absolute value of the difference between the to-be-tested value of the N+1th group of tests from small to large; wherein y is an integer greater than or equal to 2, and the target value is determined according to the to-be-tested value of the memory clock phase of the N+yth group of tests.

[0084] When the to-be-tested value of the memory clock phase of the N+1th group of tests is a value, the memory is tested according to the to-be-tested value to obtain the test result of the N+1th group of tests. If the number of errors in the test result is not zero, it indicates that the test fails. Then the to-be-tested value in the preset to-be-tested value set on both sides of the to-be-tested value of the N+1th group of tests is determined as a new to-be-tested value. Specifically, in the preset to-be-tested value set, the to-be-tested values are sequentially determined as the to-be-tested value of the memory clock phase of the N+yth group of tests in order of the absolute value of the difference between the to-be-tested value of the N+1th group of tests from small to large. Wherein y is an integer greater than or equal to 2. Then the memory is tested according to the to-be-tested value of the memory clock phase of the N+yth group of tests to obtain the test result. If the number of errors in the test result is zero, the corresponding to-be-tested value is directly determined as the target value that passes the test. If the number of errors in the test result is not zero, the next to-be-tested value is sequentially determined according to the above order, and the test is continued until the target value is determined.

[0085] According to the embodiment of the present application, the first test value and the second test value in the preset test value set of the memory clock phase are used to perform the Nth group of tests on the memory respectively, and the corresponding first test result and second test result are obtained; the test value of the memory clock phase in the N+1th group of tests is determined according to the number of errors in the first test result and the second test result and the first test value and the second test value; and the target value of the memory clock phase that passes the test is determined according to the test value of the memory clock phase in the N+1th group of tests, so that in the multiple tests for finding the target value, the test value of the N+1th group of tests is automatically determined according to the number of errors in the test result of the Nth group of tests by using the characteristic that the number of errors is affected by the memory clock phase, the range of the test is reduced more quickly, the target value is found more quickly, the time consumption of the parameter debugging of the memory clock phase of the memory is reduced, and the problem that the automatic training cannot be performed on the SMD particle memory and the DDR2 memory is solved, so that the application range of the automatic adaptation of the memory clock phase is wider.

[0086] It should be noted that, for the method embodiment, in order to simply describe, all are expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the action sequence described, because according to the embodiment of the present application, certain steps can be performed in other sequence or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiment of the present application.

[0087] Referring to Figure 5 , a structure block diagram of an embodiment of a memory clock phase determination apparatus provided by another embodiment of the present application is shown, and specifically can include the following modules:

[0088] The test module 201 is used to perform the Nth group of tests on the memory according to the first test value and the second test value in the preset test value set of the memory clock phase respectively, and obtain the corresponding first test result and second test result; wherein the N is an integer greater than or equal to 1;

[0089] The test value determination module 202 is used to determine the test value of the memory clock phase in the N+1th group of tests according to the number of errors in the first test result and the second test result and the first test value and the second test value;

[0090] The target value determination module 203 is used to determine the target value of the memory clock phase that passes the test according to the test value of the memory clock phase in the N+1th group of tests.

[0091] In an optional embodiment of the present application, the test value determination module includes:

[0092] a first quantity comparison submodule configured to compare the number of errors in the first test result and the second test result;

[0093] a first to-be-tested value determination submodule configured to, in a case where the number of errors in the two test results is not equal, take the average of the first to-be-tested value and the second to-be-tested value and the to-be-tested value with a smaller number of errors in the first to-be-tested value and the second to-be-tested value as the two to-be-tested values of the memory clock phase of the N+1th group of tests;

[0094] a second to-be-tested value determination submodule configured to, in a case where the number of errors in the two test results is equal, take the average of the first to-be-tested value and the second to-be-tested value as the to-be-tested value of the memory clock phase of the N+1th group of tests.

[0095] In an optional embodiment of the present application, in a case where the number of errors in the two test results is not equal, the target value determination module comprises:

[0096] a first test submodule configured to respectively test the memory according to the two to-be-tested values of the memory clock phase of the N+1th group of tests, to obtain two corresponding test results;

[0097] a third to-be-tested value determination submodule configured to, in a case where the number of errors in the two test results is equal, take the average of the two to-be-tested values of the N+1th group of tests as the to-be-tested value of the memory clock phase of the N+2th group of tests;

[0098] a target value determination submodule configured to determine the target value according to the to-be-tested value of the memory clock phase of the N+2th group of tests.

[0099] In an optional embodiment of the present application, in a case where the number of errors in the two test results is equal, the target value determination module comprises:

[0100] a second test submodule configured to test the memory according to the to-be-tested value of the memory clock phase of the N+1th group of tests, to obtain the test result of the N+1th group of tests;

[0101] a fifth to-be-tested value determination submodule configured to, in a case where the test result of the N+1th group of tests indicates that the test fails, determine the to-be-tested value of the memory clock phase of the N+yth group of tests in the preset to-be-tested value set in order of the absolute value of the difference from the to-be-tested value of the N+1th group of tests from small to large; wherein the y is an integer greater than or equal to 2.

[0102] determine the target value according to the to-be-tested value of the memory clock phase of the N+yth group of tests.

[0103] In an alternative embodiment of the present application, N=1, one of the first test value and the second test value is the maximum value in the preset test value set, and the other is the minimum value in the preset test value set.

[0104] According to the embodiment of the present application, the first test value and the second test value in the preset test value set of the memory clock phase are used to test the memory for the Nth time, and the corresponding first test result and the second test result are obtained. The test value of the memory clock phase for the N+1th test is determined according to the number of errors in the first test result and the second test result and the first test value and the second test value. The target value of the memory clock phase that passes the test is determined according to the test value of the memory clock phase for the N+1th test. In the multiple tests for finding the target value, the number of errors affected by the memory clock phase is used to automatically determine the test value for the N+1th test according to the number of errors in the test result of the Nth test, so as to quickly narrow the test range and find the target value more quickly, reduce the time consumption of the parameter debugging of the memory clock phase of the memory, and solve the problem that the automatic training cannot be performed on the SMD memory and the DDR2 memory, so that the application range of the automatic adaptation of the memory clock phase is wider.

[0105] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0106] Figure 6 FIG. 7 is a structural block diagram of an electronic device 700 for memory clock phase determination according to an exemplary embodiment. The electronic device 700 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0107] Referring to Figure 6 , the electronic device 700 can include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0108] The processing component 702 generally controls the overall operations of the electronic device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 can include one or more processors 720 to execute instructions to complete the steps of the methods described above, in whole or in part. Moreover, the processing component 702 can include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 can include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0109] The memory 704 is configured to store various types of data to support operations of the electronic device 700. Examples of these data include instructions to operate any applications or methods on the electronic device 700, contact data, phonebook data, messages, pictures, videos, and so on. The memory 704 can be realized by any type of volatile or non-volatile storage devices, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disc, or optical disc.

[0110] The power component 704 provides power to various components of the electronic device 700. The power component 704 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 700.

[0111] The multimedia component 708 includes a screen to provide an output interface between the electronic device 700 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 708 includes a front camera and / or a back camera. The front camera and / or the back camera can receive external multimedia data when the electronic device 700 is in an operating mode, such as a shooting mode or a video mode. Each of the front camera and the back camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0112] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC) that is configured to receive an external audio signal when the electronic device 700 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0113] The I / O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0114] The sensor component 714 includes one or more sensors for providing status assessments of various aspects of the electronic device 700. For example, the sensor component 714 can detect an open / closed position of the device 700, relative positioning of components, such as a display and a keypad of the electronic device 700, a change of position of the electronic device 700 or a component of the electronic device 700, presence or absence of user contact with the electronic device 700, orientation or acceleration / deceleration of the electronic device 700, and a temperature change of the electronic device 700. The sensor component 714 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 714 can also include a light sensor, such as a CMOS or CCD image sensor, for use in an imaging application. In some embodiments, the sensor component 714 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0115] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an example embodiment, the communication component 714 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 714 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technology.

[0116] In an exemplary embodiment, the electronic device 700 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for performing the above-described methods.

[0117] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 704 including instructions, is also provided, which can be executed by the processor 720 of the electronic device 700 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0118] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a terminal, enables the terminal to perform a memory clock phase determination method, the method comprising:

[0119] According to a first test value and a second test value in a preset test value set of a memory clock phase, performing an Nth group of tests on the memory, respectively, to obtain a corresponding first test result and a second test result; wherein N is an integer greater than or equal to 1;

[0120] According to the number of errors in the first test result and the second test result and the first test value and the second test value, determining a test value of the memory clock phase for an N+1th group of tests;

[0121] According to the test value of the memory clock phase for the N+1th group of tests, determining a target value of the memory clock phase that passes the test.

[0122] Optionally, the determining of the test value of the memory clock phase for the N+1th group of tests according to the number of errors in the first test result and the second test result and the first test value and the second test value comprises:

[0123] Comparing the number of errors in the first test result and the second test result;

[0124] In the case that the number of errors in the two test results is not equal, taking an average of the first test value and the second test value and the test value with fewer errors in the first test value and the second test value as two test values of the memory clock phase for the N+1th group of tests;

[0125] In a case where the number of errors in the two test results is equal, an average of the first to-be-tested value and the second to-be-tested value is determined as the to-be-tested value of the memory clock phase of the N+1th test.

[0126] Optionally, in a case where the number of errors in the two test results is not equal, the determining the target value of the memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the N+1th test comprises:

[0127] The memory is tested according to the two to-be-tested values of the memory clock phase of the N+1th test respectively, and two corresponding test results are obtained;

[0128] In a case where the number of errors in the two test results is equal, an average of the two to-be-tested values of the N+1th test is determined as the to-be-tested value of the memory clock phase of the N+2th test.

[0129] The target value is determined according to the to-be-tested value of the memory clock phase of the N+2th test.

[0130] Optionally, in a case where the number of errors in the two test results is equal, the determining the target value of the memory clock phase that passes the test according to the to-be-tested value of the memory clock phase of the N+1th test comprises:

[0131] The memory is tested according to the to-be-tested value of the memory clock phase of the N+1th test, and a test result of the N+1th test is obtained.

[0132] In a case where the test result of the N+1th test indicates that the test fails, to-be-tested values of memory clock phases of N+yth tests are determined in the preset to-be-tested value set in a sequence from small to large of absolute values of differences between the to-be-tested values of the N+1th test; wherein, the y is an integer greater than or equal to 2.

[0133] The target value is determined according to the to-be-tested value of the memory clock phase of the N+yth test.

[0134] Optionally, the N=1, one of the first to-be-tested value and the second to-be-tested value is the maximum value in the preset to-be-tested value set, and the other is the minimum value in the preset to-be-tested value set.

[0135] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0136] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer readable program code.

[0137] Embodiments of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0138] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing terminal apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal apparatus to cause a series of operational steps to be performed on the computer or other programmable terminal apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0140] While preferred embodiments of the present application have been described, modifications and alterations thereto will occur to those skilled in the art upon reading the preceding description. In particular, it will be apparent to those skilled in the art that parts can be added to, or substituted for, parts of the described embodiments of the present application. Accordingly, the application is intended to be

[0141] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0142] The above describes in detail the memory clock phase determination method and the memory clock phase determination device provided by the present application. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A method for memory clock phase determination, the method comprising: The method comprises the following steps: According to the first test value and the second test value in the preset test value set of the memory clock phase, the memory is tested respectively to obtain the corresponding first test result and the second test result; wherein, N is an integer greater than or equal to 1; According to the number of errors in the first test result and the second test result and the first test value and the second test value, the test value of the memory clock phase of the N+1 test is determined; According to the test value of the memory clock phase of the N+1 test, the target value of the memory clock phase that passes the test is determined; The method comprises the following steps: Compare the number of errors in the first test result and the second test result; In the case that the number of errors in the two test results is not equal, the average of the first test value and the second test value, and the test value with fewer errors in the first test value and the second test value, are taken as the two test values of the memory clock phase of the N+1 test; In the case that the number of errors in the two test results is equal, the average of the first test value and the second test value is taken as the test value of the memory clock phase of the N+1 test.

2. The method of claim 1, wherein, In the case that the number of errors in the two test results is not equal, the method comprises the following steps: According to the two test values of the memory clock phase of the N+1 test, the memory is tested respectively to obtain the corresponding two test results; In the case that the number of errors in the two test results is equal, the average of the two test values of the N+1 test is taken as the test value of the memory clock phase of the N+2 test; According to the test value of the memory clock phase of the N+2 test, the target value is determined.

3. The method of claim 1, wherein, In the case that the number of errors in the two test results is equal, the method comprises the following steps: According to the test value of the memory clock phase of the N+1 test, the memory is tested to obtain the test result of the N+1 test; In the case that the test result of the N+1 test indicates that the test fails, the test values of the memory clock phase of the N+y test are determined in the preset test value set in the order of the absolute value of the difference from the test value of the N+1 test from small to large; wherein, y is an integer greater than or equal to 2; According to the test value of the memory clock phase of the N+y test, the target value is determined.

4. The method according to any one of claims 1 to 3, characterized in that, The N=1, one of the first test value and the second test value is the maximum value in the preset test value set, and the other is the minimum value in the preset test value set.

5. A memory clock phase determination apparatus, comprising: The method comprises the following steps: The test module is configured to perform N sets of tests on the memory according to a first test value and a second test value in a preset test value set of the memory clock phase, and obtain a first test result and a second test result respectively, wherein N is an integer greater than or equal to 1; The test value determination module is configured to determine a test value of the memory clock phase for the N+1th set of tests according to the number of errors in the first test result and the second test result and the first test value and the second test value; The target value determination module is configured to determine the target value of the memory clock phase that passes the test according to the test value of the memory clock phase for the N+1th set of tests; The test value determination module includes: The first number comparison submodule is configured to compare the number of errors in the first test result and the second test result; The first test value determination submodule is configured to, in a case where the number of errors in the two test results is not equal, take an average of the first test value and the second test value and a test value with a smaller number of errors in the first test value and the second test value as the two test values of the memory clock phase for the N+1th set of tests; The second test value determination submodule is configured to, in a case where the number of errors in the two test results is equal, take an average of the first test value and the second test value as the test value of the memory clock phase for the N+1th set of tests.

6. The apparatus of claim 5, wherein, In a case where the number of errors in the two test results is not equal, the target value determination module includes: The first test submodule is configured to perform tests on the memory according to the two test values of the memory clock phase for the N+1th set of tests, and obtain two test results respectively; The third test value determination submodule is configured to, in a case where the number of errors in the two test results is equal, take an average of the two test values of the N+1th set of tests as a test value of the memory clock phase for the N+2th set of tests; The target value determination submodule is configured to determine the target value according to the test value of the memory clock phase for the N+2th set of tests.

7. The apparatus of claim 5, wherein, In a case where the number of errors in the two test results is equal, the target value determination module includes: The second test submodule is configured to perform a test on the memory according to the test value of the memory clock phase for the N+1th set of tests, and obtain a test result of the N+1th set of tests; The fifth test value determination submodule is configured to, in a case where the test result of the N+1th set of tests indicates that the test fails, determine test values of the memory clock phase for N+y sets of tests in the preset test value set in order of absolute values of differences from the test value of the N+1th set of tests from small to large, wherein y is an integer greater than or equal to 2; The target value is determined according to the test value of the memory clock phase for the N+y sets of tests.

8. The apparatus of any one of claims 5-7, wherein, The N=1, one of the first test value and the second test value is the maximum value in the preset test value set, and the other is the minimum value in the preset test value set.

9. An electronic device, comprising: The application comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is used for storing a computer program; The processor is used for executing the program stored in the memory to realize the method steps in any one of claims 1-4.

10. A readable storage medium, characterized by, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device can execute the memory clock phase determination method as claimed in any one of claims 1-4.

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