Gate driver

Abstract

A gate driver. The gate driver includes a plurality of gate drive circuits. The gate drive circuits are to provide a plurality of gate signals to a pixel array and each include a primary drive block and a secondary drive block. The primary drive block is to set a corresponding gate signal to a write voltage level in a corresponding enable period during an active area of a frame period. The secondary drive block is to set the corresponding gate signal to the write voltage level in a write black period of a blank period of the frame period and to set the corresponding gate signal to a discharge voltage level in a discharge period of the blank period, where the discharge period is subsequent to the write black period.

Description

TECHNICAL FIELD

[0001] The present application relates to a driver, and particularly relates to a gate driver. BACKGROUND

[0002] With the advancement of semiconductor technology, the size of display panel is getting larger and larger, and the resolution of display panel is getting higher and higher. Under the condition that the resolution of display panel is continuously improved, the application of resolution conversion is proposed to correspond to the display image of different aspect ratios. In some applications, part of the area of the display panel is not the area of the display image, so it is necessary to write a pure black image (or color) to create the overall display environment.

[0003] When writing black to part of the display panel, the corresponding gate signal is enabled at the same time to turn on the corresponding pixel, and the gate driver is turned off, so that the gate line is in a floating state. However, in the state that the gate line is in a floating state, the charge of the gate line is released by coupling, which is very slow, so that the voltage on the gate line causes the transistor in the pixel to suffer stress effect, which affects the operation of the display panel. SUMMARY

[0004] The present application provides a gate driver which can quickly release the charge of the gate line of the black writing area on the display panel to avoid the transistor of the pixel of the black writing area on the panel suffering stress effect.

[0005] The gate driver of the present application includes a plurality of gate driving circuits. These gate driving circuits are used to provide a plurality of gate signals to a pixel array, and each includes a main driving block and a secondary driving block. The main driving block is used to set the corresponding gate signal to a writing voltage level in the corresponding enable period during the active area during the frame period. The secondary driving block is used to set the corresponding gate signal to a writing voltage level during the black writing period during the blank period of the frame period, and set the corresponding gate signal to a discharge voltage level during the discharge period of the blank period, wherein the discharge period is located after the black writing period.

[0006] Based on the above, the gate driver of the embodiment of the present application sets the corresponding gate signal to a writing voltage level during the black writing period of the blank period of the frame period, and sets the corresponding gate signal to a discharge voltage level during the discharge period of the blank period. Therefore, the gate driving circuit can quickly release the charge of the gate line of the pixel of the non-display image on the display panel to avoid the transistor of the pixel of the non-display image on the display panel suffering stress effect.

[0007] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the detailed description is described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A Circuit diagram of a gate drive circuit according to a first embodiment of the present application.

[0009] Figure 1A Operation waveform diagram of a gate drive circuit according to the first embodiment of the present application.

[0010] Figure 2 Circuit diagram of a gate drive circuit according to a second embodiment of the present application.

[0011] Figure 3A Circuit diagram of a gate drive circuit according to a third embodiment of the present application.

[0012] Figure 3B Operation waveform diagram of a gate drive circuit according to the third embodiment of the present application.

[0013] Figure 4A Circuit diagram of a gate drive circuit according to a fourth embodiment of the present application.

[0014] Figure 4B Operation waveform diagram of a gate drive circuit according to the fourth embodiment of the present application.

[0015] Figure 5 Circuit diagram of a gate drive circuit according to a fifth embodiment of the present application.

[0016] Figure 6A Circuit diagram of a gate drive circuit according to a sixth embodiment of the present application.

[0017] Figure 6B Operation waveform diagram of a gate drive circuit according to the sixth embodiment of the present application.

[0018] Figure 7 System diagram of a pixel array coupled with a gate driver according to an embodiment of the present application.

[0019] Figure 8 System diagram of a pixel array coupled with a gate driver according to another embodiment of the present application.

[0020] REFERENCE NUMERALS

[0021] 100, 200, 300, 400, 500, 600, CTG, CTGa: gate drive circuit

[0022] 110: primary drive block

[0023] 120, 220, 320, 420, 520, 620: secondary drive block

[0024] BW: write black period

[0025] C1: capacitor

[0026] Data: display data

[0027] DCH: discharge period

[0028] DLE: data line

[0029] G(n), G(n-4), SG: gate signal

[0030] GCG1-GCG6, GCG1a-GCG6a: gate driver

[0031] GLE: gate line

[0032] HCn: clock signal

[0033] LC1, LC2: low frequency clock signal

[0034] P(n), K(n): control signal

[0035] P_ACT: active area period

[0036] P_BLK: blank period

[0037] PD: disable period

[0038] PE: enable period

[0039] PX: pixel

[0040] PXA: pixel array

[0041] Q(n): control voltage

[0042] ST(n-4), ST(n), ST(n+4): drive signal

[0043] TB1, TB1a: first blank transistor

[0044] TB2: second blank transistor

[0045] TB3: third blank transistor

[0046] TB4, TB4a: fourth blank transistor

[0047] TB5: fifth blank transistor

[0048] TB6: sixth blank transistor

[0049] Vcom: common voltage

[0050] VGH: gate high voltage

[0051] VSS: gate low voltage

[0052] XOFF: discharge control signal

[0053] XON(D), XON(D)-1 ~ XON(D)-6: first write control signal XON(G): second write control signal

[0054] XON, XON1 ~ XON6: write control signal DETAILED DESCRIPTION

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“component,”“region,”“layer” or“section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms, including“at least one,” unless the content clearly indicates otherwise. “Or” means“and / or.” As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms“comprises” and / or“comprising,” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0058] Figure 1A is a circuit schematic diagram of a gate drive circuit according to a first embodiment of the present application. Please refer to Figure 1A In the embodiments of the present application, a plurality of gate drive circuits 100 can be connected in series to form a gate driver (e.g.Figure 7 the gate driver GDR or Figure 8 the gate driver GDRa), and these gate driving circuits 100 provide a plurality of gate signals G(n) (or, as Figure 7 or Figure 8 to a pixel array (such as Figure 7 or Figure 8 the pixel array PXA).

[0059] In this embodiment, the gate driving circuit 100 includes at least a main driving block 110 and a sub-driving block 120. The main driving block 110 is configured to set a corresponding gate signal G(n) to a write voltage level in a corresponding enable period during an active period of a frame period. The sub-driving block 120 is configured to set the corresponding gate signal G(n) to the write voltage level in a write black period during a blank period of the frame period, and set the corresponding gate signal G(n) to a discharge voltage level in a discharge period during the blank period. The active period mainly corresponds to a time period during which pixels displaying an image are written, the blank period mainly corresponds to a time period during which pixels displaying no image (i.e., displaying black) are written, and the discharge period is located after the write black period. The above timing can be referred to Figure 1B as shown in FIG. 1, and will be described later. Thus, the gate driving circuit 100 can quickly release the charge of the gate line of the pixel displaying no image on the display panel, so as to avoid the transistor of the pixel displaying no image on the display panel from suffering from a stress effect.

[0060] In this embodiment, the blank period is different from the existing vertical blank period, and the blank period can be connected to the vertical blank period or separated from the vertical blank period. The embodiment of the present application is not limited in this regard.

[0061] In this embodiment, the main driving block 110 includes transistors T1-T18 and a capacitor C1, where the transistors T1-T18 are taken as N-type transistors. The first end of the transistor T1 receives a gate signal G(n-4) (i.e., a gate signal of a horizontal line (or a gate line) 4 levels (or 4 lines) earlier), the control end of the transistor T1 receives a driving signal ST(n-4) (i.e., a driving signal of the horizontal line (or the gate line) 4 levels (or 4 lines) earlier), and the second end of the transistor T1 provides a control voltage Q(n). Wherein, n is a positive integer.

[0062] The first end of the transistor T2 receives the clock signal HCn, the control end of the transistor T2 receives the control voltage Q(n), and the second end of the transistor T2 provides the corresponding driving signal ST(n). The first end of the transistor T3 (i.e., the driving transistor) receives the clock signal HCn, the control end of the transistor T3 receives the control voltage Q(n), and the second end of the transistor T3 provides the corresponding gate signal G(n).

[0063] The first end of the transistor T4 receives the low-frequency clock signal LC1, and the control end of the transistor T4 receives the low-frequency clock signal LC1. The first end of the transistor T5 is coupled to the second end of the transistor T4, the control end of the transistor T5 receives the control voltage Q(n), and the second end of the transistor T5 receives the gate low voltage VSS. The first end of the transistor T6 receives the low-frequency clock signal LC1, the control end of the transistor T6 is coupled to the second end of the transistor T4, and the second end of the transistor T6 provides the control signal P(n). The first end of the transistor T7 is coupled to the second end of the transistor T6, the control end of the transistor T7 receives the control voltage Q(n), and the second end of the transistor T7 receives the gate low voltage VSS.

[0064] The capacitor C1 is coupled between the control voltage Q(n) and the corresponding gate signal G(n). The first end of the transistor T8 receives the corresponding gate signal G(n), the control end of the transistor T8 receives the control signal P(n), and the second end of the transistor T8 receives the gate low voltage VSS. The first end of the transistor T9 receives the control voltage Q(n), the control end of the transistor T9 receives the control signal P(n), and the second end of the transistor T9 receives the gate low voltage VSS. The first end of the transistor T10 receives the corresponding driving signal ST(n), the control end of the transistor T10 receives the control signal P(n), and the second end of the transistor T10 receives the gate low voltage VSS.

[0065] The first end of the transistor T11 receives the low-frequency clock signal LC2, and the control end of the transistor T11 receives the low-frequency clock signal LC2, which is inverted from the low-frequency clock signal LC1. The first end of the transistor T12 is coupled to the second end of the transistor T11, the control end of the transistor T12 receives the control voltage Q(n), and the second end of the transistor T12 receives the gate low voltage VSS. The first end of the transistor T13 receives the low-frequency clock signal LC2, the control end of the transistor T13 is coupled to the second end of the transistor T11, and the second end of the transistor T13 provides the control signal K(n). The first end of the transistor T14 is coupled to the second end of the transistor T13, the control end of the transistor T14 receives the control voltage Q(n), and the second end of the transistor T14 receives the gate low voltage VSS.

[0066] The first end of the transistor T15 receives a corresponding gate signal G(n), the control end of the transistor T15 receives a control signal K(n), and the second end of the transistor T15 receives a gate low voltage VSS. The first end of the transistor T16 receives a control voltage Q(n), the control end of the transistor T16 receives the control signal K(n), and the second end of the transistor T16 receives the gate low voltage VSS. The first end of the transistor T17 receives a corresponding drive signal ST(n), the control end of the transistor T17 receives the control signal K(n), and the second end of the transistor T17 receives the gate low voltage VSS. The first end of the transistor T18 receives the control voltage Q(n), the control end of the transistor T18 receives a drive signal ST(n+4) (i.e., the drive signal of the horizontal line (or gate line) four stages (or lines) later), and the second end of the transistor T18 receives the gate low voltage VSS.

[0067] In the present embodiment, the secondary drive block 120 includes a first blank transistor TB1 and a second blank transistor TB2. The first blank transistor TB1 has a first end receiving a write control signal XON, a control end receiving the write control signal XON, and a second end coupled to a corresponding gate signal G(n). The second blank transistor TB2 has a first end coupled to the corresponding gate signal G(n), a control end receiving a discharge control signal XOFF, and a second end receiving a discharge voltage level (e.g., the gate low voltage VSS in the present embodiment).

[0068] Figure 1B FIG. 6 shows an operation waveform diagram of the gate drive circuit according to the first embodiment of the present application. Please refer to FIG. 6. Figure 1A and Figure 1B In the present embodiment, a frame period includes at least an active region period P ACT and a blank period P BLK. The time length of the active region period P ACT is adjusted according to the number of horizontal lines of the display image of the pixel array (e.g., the pixel array PXA shown in FIG. 1), and the sum of the time lengths of the active region period P ACT and the blank period P BLK is equal to the total number of horizontal lines of the pixel array (e.g., the pixel array PXA shown in FIG. 1). Figure 7 or Figure 8 Figure 7 or Figure 8

[0069] The main drive block 110 sets the corresponding gate signal G(n) to the write voltage level (e.g., the gate high voltage VGH) in the corresponding enabled period of the active region period P ACT, so as to write the corresponding pixel voltage in the display data Data to the pixel (e.g., the pixel PXL shown in FIG. 1). Figure 7 or Figure 8 ​​The corresponding pixel PX is set to black. Also, the write control signal XON and the discharge control signal XOFF are enabled during the write black period BW and the discharge period DCH, respectively, i.e. the first blanking transistor TB1 is turned on during the write black period BW and the second blanking transistor TB2 is turned on during the discharge period DCH, wherein the discharge period DCH is located after the write black period BW, and the time length of the write black period BW and the discharge period DCH can be determined according to the circuit requirement.

[0070] During the blank period P_BLK, the display data Data is set to the common voltage Vcom (which can be regarded as the lowest luminance gray scale voltage, or the 0th gray scale voltage), so as to set the corresponding pixel (such as the pixel PX shown in the figure) to black. Also, the write control signal XON and the discharge control signal XOFF are enabled during the write black period BW and the discharge period DCH, respectively, i.e. the first blanking transistor TB1 is turned on during the write black period BW and the second blanking transistor TB2 is turned on during the discharge period DCH, wherein the discharge period DCH is located after the write black period BW, and the time length of the write black period BW and the discharge period DCH can be determined according to the circuit requirement. Figure 7 Figure 8 The corresponding pixel PX is set to black. Also, the write control signal XON and the discharge control signal XOFF are enabled during the write black period BW and the discharge period DCH, respectively, i.e. the first blanking transistor TB1 is turned on during the write black period BW and the second blanking transistor TB2 is turned on during the discharge period DCH, wherein the discharge period DCH is located after the write black period BW, and the time length of the write black period BW and the discharge period DCH can be determined according to the circuit requirement.

[0071] The first end of the first blanking transistor TB1 receives the write control signal XON as the write voltage level (i.e. the gate high voltage VGH) during the write black period BW, and receives the write control signal XON as the discharge voltage level (i.e. the gate low voltage VSS) during the discharge period DCH. In other words, the corresponding gate signal G(n) of the secondary driving block 120 is set to the write voltage level (i.e. the gate high voltage VGH) during the write black period BW of the blank period P_BLK, and is set to the discharge voltage level (i.e. the gate low voltage VSS) during the discharge period DCH of the blank period P_BLK.

[0072] Figure 2 The circuit schematic diagram of the gate driving circuit according to the second embodiment of the present application is shown in FIG. 2. Please refer to FIG. 2 and FIG. 1, the gate driving circuit 200 is substantially the same as the gate driving circuit 100, except that the first blanking transistor TB1a of the secondary driving block 220, wherein the same or similar elements use the same or similar reference numerals. In this embodiment, the first blanking transistor TB1a has a first end receiving the write voltage level (i.e. the gate high voltage VGH), a control end receiving the write control signal XON, and a second end coupled to the corresponding gate signal G(n). Figure 1A Figure 2 The circuit schematic diagram of the gate driving circuit according to the third embodiment of the present application is shown in FIG. 3. Please refer to FIG. 3 and FIG. 1, the gate driving circuit 300 is substantially the same as the gate driving circuit 100, except that the first blanking transistor TB1b of the secondary driving block 320, wherein the same or similar elements use the same or similar reference numerals. In this embodiment, the first blanking transistor TB1b has a first end receiving the write voltage level (i.e. the gate high voltage VGH), a control end receiving the write control signal XON, and a second end coupled to the corresponding gate signal G(n).

[0073] Figure 3A The circuit schematic diagram of the gate driving circuit according to the third embodiment of the present application is shown in FIG. 3. Please refer to FIG. 3 and FIG. 1, the gate driving circuit 300 is substantially the same as the gate driving circuit 100, except that the first blanking transistor TB1b of the secondary driving block 320, wherein the same or similar elements use the same or similar reference numerals. In this embodiment, the first blanking transistor TB1b has a first end receiving the write voltage level (i.e. the gate high voltage VGH), a control end receiving the write control signal XON, and a second end coupled to the corresponding gate signal G(n). Figure 1A Figure 3A ​​​The gate drive circuit 300 is substantially the same as the gate drive circuit 100, except that the secondary drive block 320 only includes a third blank transistor TB3, wherein the same or similar elements are labeled with the same or similar designations. In this embodiment, the third blank transistor TB3 has a first terminal receiving a first write control signal XON(D), a control terminal receiving a second write control signal XON(G), and a second terminal coupled to the corresponding gate signal G(n).

[0074] Figure 3B This is a schematic diagram of the operation waveforms of the gate drive circuit according to the third embodiment of the present invention. Please refer to... Figure 1B , Figure 3A and Figure 3B In this embodiment, the second write control signal XON(G) is enabled during the blank period P_BLK, and the first write control signal XON(D) is at the write voltage level (i.e., gate high voltage VGH) during the write black period BW and at the discharge voltage level (i.e., gate low voltage VSS) during the discharge period DCH.

[0075] Figure 4A This is a circuit diagram of a gate driving circuit according to a fourth embodiment of the present invention. Please refer to... Figure 1A and Figure 4A The gate drive circuit 400 is largely the same as the gate drive circuit 100, except for the secondary drive block 420. In this embodiment, the secondary drive block 420 includes a fourth blanking transistor TB4 and a fifth blanking transistor TB5. The fourth blanking transistor TB4 has a first terminal for receiving a write control signal XON, a control terminal for receiving the write control signal XON, and a second terminal for receiving a control terminal coupled to transistor T3. The fifth blanking transistor TB5 has a first terminal for receiving a control terminal coupled to transistor T3, a control terminal for receiving a discharge control signal XOFF, and a second terminal for receiving a discharge voltage level (i.e., gate low voltage VSS).

[0076] In this embodiment, the fourth blank transistor TB4 is only used to control transistor T3, meaning it does not require a large driving capability, thus reducing the transistor's circuit area. However, the circuit area of ​​the first blank transistor TB1 is approximately equal to that of transistor T3 to have sufficient driving capability to drive the corresponding gate signal G(n).

[0077] Figure 4B This is a schematic diagram of the operation waveforms of the gate drive circuit according to the fourth embodiment of the present invention. Please refer to... Figure 1A , Figure 1B , Figure 4A and Figure 4Bwherein the write control signal XON and the discharge control signal XOFF are enabled during the write black period BW and the discharge period DCH, respectively, and in the blank period P_BLK, the enable period PE of the clock signal HCn corresponds to the write black period BW, and the disable period PD of the clock signal HCn corresponds to the discharge period DCH. In this embodiment, the time length of the write black period BW, the discharge period DCH, the enable period PE, and the disable period PD can be determined according to the circuit requirement.

[0078] Figure 5 FIG. 6 is a circuit schematic diagram of a gate drive circuit according to a sixth embodiment of the present application. Please refer to Figure 4A and Figure 5 The gate drive circuit 600 is substantially the same as the gate drive circuit 100, except that the secondary drive block 620 only includes the sixth blank transistor TB6, wherein the same or similar elements use the same or similar reference numerals. In this embodiment, the sixth blank transistor TB6 has a first terminal receiving the first write control signal XON(D), a control terminal receiving the second write control signal XON(G), and a second terminal coupled to the control terminal of the transistor T3.

[0079] Figure 6A FIG. 6 is a circuit schematic diagram of a gate drive circuit according to a sixth embodiment of the present application. Please refer to Figure 1A and Figure 6A The gate drive circuit 600 is substantially the same as the gate drive circuit 100, except that the secondary drive block 620 only includes the sixth blank transistor TB6, wherein the same or similar elements use the same or similar reference numerals. In this embodiment, the sixth blank transistor TB6 has a first terminal receiving the first write control signal XON(D), a control terminal receiving the second write control signal XON(G), and a second terminal coupled to the control terminal of the transistor T3.

[0080] Figure 6B FIG. 6 is a circuit schematic diagram of a gate drive circuit according to a sixth embodiment of the present application. Please refer to Figure 3A , Figure 3B , Figure 6A and Figure 6B The second write control signal XON(G) is enabled in the blank period P_BLK, and the first write control signal XON(D) is the write voltage level (i.e. the gate high voltage VGH) in the write black period BW and is the discharge voltage level (i.e. the gate low voltage VSS) in the discharge period DCH. And in the blank period P_BLK, the enable period PE of the clock signal HCn corresponds to the write black period BW, and the disable period PD of the clock signal HCn corresponds to the discharge period DCH. In this embodiment, the time length of the write black period BW, the discharge period DCH, the enable period PE, and the disable period PD can be determined according to the circuit requirement.

[0081] Figure 7 FIG. 1 shows a system diagram of a pixel array coupled with a gate driver according to an embodiment of the present application. Please refer to FIG. 1, which shows a system diagram of a pixel array coupled with a gate driver according to an embodiment of the present application. In this embodiment, the gate driver GDR includes a plurality of gate drive circuits CTG, and the gate drive circuits CTG can be one of the gate drive circuit 100, the gate drive circuit 200, the gate drive circuit 400, and the gate drive circuit 500. Moreover, the gate drive circuits CTG are divided into a plurality of gate drive circuit groups GCG1-GCG6, wherein each of the gate drive circuit groups GCG1-GCG6 receives a corresponding one of the write control signals XON1-XON6, and the gate drive circuit groups GCG1-GCG6 commonly receive the discharge control signal XOFF. Figure 1A Figure 2 Figure 4A Figure 5 Figure 7 In this embodiment, the gate driver GDRa includes a plurality of gate drive circuits CTGa, and the gate drive circuits CTGa can be one of the gate drive circuit 300 and the gate drive circuit 600. Moreover, the gate drive circuits CTGa are divided into a plurality of gate drive circuit groups GCG1a-GCG6a, wherein each of the gate drive circuit groups GCG1a-GCG6a receives a corresponding one of the first write control signals XON(D)-1-XON(D)-6, and the gate drive circuit groups GCG1a-GCG6a commonly receive the second write control signal XON(G).

[0082] The gate drive circuit CTG provides a plurality of gate signals SG to the pixel array PXA, and the pixels PX in the pixel array PXA are coupled with corresponding data lines DLE to receive corresponding display data Data and coupled with corresponding gate lines GLE to receive corresponding gate signals SG.

[0083] Figure 8 FIG. 2 shows a system diagram of a pixel array coupled with a gate driver according to another embodiment of the present application. Please refer to FIG. 2, which shows a system diagram of a pixel array coupled with a gate driver according to another embodiment of the present application. In this embodiment, the gate driver GDRa includes a plurality of gate drive circuits CTGa, and the gate drive circuits CTGa can be one of the gate drive circuit 300 and the gate drive circuit 600. Moreover, the gate drive circuits CTGa are divided into a plurality of gate drive circuit groups GCG1a-GCG6a, wherein each of the gate drive circuit groups GCG1a-GCG6a receives a corresponding one of the first write control signals XON(D)-1-XON(D)-6, and the gate drive circuit groups GCG1a-GCG6a commonly receive the second write control signal XON(G). Figure 3A Figure 6A Figure 8 In this embodiment, the gate driver GDRa includes a plurality of gate drive circuits CTGa, and the gate drive circuits CTGa can be one of the gate drive circuit 300 and the gate drive circuit 600. Moreover, the gate drive circuits CTGa are divided into a plurality of gate drive circuit groups GCG1a-GCG6a, wherein each of the gate drive circuit groups GCG1a-GCG6a receives a corresponding one of the first write control signals XON(D)-1-XON(D)-6, and the gate drive circuit groups GCG1a-GCG6a commonly receive the second write control signal XON(G).

[0084] The gate drive circuit CTG provides a plurality of gate signals SG to the pixel array PXA, and the pixels PX in the pixel array PXA are coupled with corresponding data lines DLE to receive corresponding display data Data and coupled with corresponding gate lines GLE to receive corresponding gate signals SG.

[0085] ​​​​​​In summary, the gate driver of the embodiment of the present application sets the corresponding gate signal as a write voltage level during the write black period of the blank period of the secondary driving block in the picture period, and sets the corresponding gate signal as a discharge voltage level during the discharge period of the blank period. Therefore, the gate driving circuit can quickly release the charge of the gate line of the pixel of the non-display image on the display panel, so as to avoid that the transistor of the pixel of the non-display image on the display panel suffers from the stress effect.

[0086] Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A gate driver, comprising: Multiple gate driving circuits are used to provide multiple gate signals to a pixel array, and each includes: A main drive block is used to set the corresponding gate signal to a write voltage level during the corresponding enable period of an active region during a frame; and A drive block is used to set the corresponding gate signal to the write voltage level during a write black period in a blank period of the screen, and to set the corresponding gate signal to a discharge voltage level during a discharge period in the blank period, wherein the discharge period is after the write black period.

2. The gate driver of claim 1, wherein the secondary driving block comprises: A first blanking transistor has a first terminal for receiving the write voltage level, a control terminal for receiving a write control signal, and a second terminal coupled to a corresponding gate signal; and A second blanking transistor has a first terminal coupled to a corresponding gate signal, a control terminal for receiving a discharge control signal, and a second terminal for receiving the discharge voltage level. The write control signal and the discharge control signal are respectively enabled during the write black period and the discharge period.

3. The gate driver of claim 2, wherein the first terminal of the first blanking transistor receives the write control signal to receive the write control signal at the write voltage level.

4. The gate driver of claim 2, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives a corresponding write control signal, and the gate driving circuit groups collectively receive the discharge control signal.

5. The gate driver of claim 1, wherein the secondary driving block comprises: A third blanking transistor has a first terminal for receiving a first write control signal, a control terminal for receiving a second write control signal, and a second terminal coupled to a corresponding gate signal. The first write control signal is the write voltage level during the write black period and the discharge voltage level during the discharge period. The second write control signal is enabled during the blank period.

6. The gate driver of claim 5, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives a corresponding first write control signal, and the gate driving circuit groups collectively receive the second write control signal.

7. The gate driver of claim 1, wherein the main driving block comprises: A driving transistor has a first terminal for receiving a clock signal, a control terminal for receiving a control voltage, and a second terminal coupled to a corresponding gate signal.

8. The gate driver of claim 7, wherein the secondary driving block comprises: A fourth blanking transistor has a first terminal for receiving the write voltage level, a control terminal for receiving a write control signal, and a second terminal coupled to the control terminal of the driving transistor; and A fifth blanking transistor has a first terminal coupled to the control terminal of the driving transistor, a control terminal for receiving a discharge control signal, and a second terminal for receiving the discharge voltage level; The write control signal and the discharge control signal are respectively enabled during the write black period and the discharge period.

9. The gate driver of claim 8, wherein the first terminal of the fourth blanking transistor receives the write control signal to receive the write control signal at the write voltage level.

10. The gate driver of claim 8, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives a corresponding write control signal, and the gate driving circuit groups collectively receive the discharge control signal.

11. The gate driver of claim 7, wherein the secondary driving block comprises: A sixth blanking transistor has a first terminal for receiving a first write control signal, a control terminal for receiving a second write control signal, and a second terminal coupled to the control terminal of the driving transistor. The first write control signal is the write voltage level during the write black period and the discharge voltage level during the discharge period, and The second write control signal is enabled during the blank period.

12. The gate driver of claim 11, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives a corresponding first write control signal, and the gate driving circuit groups collectively receive the second write control signal.

13. The gate driver of claim 1, wherein the active region period is adjusted in response to the number of a plurality of horizontal lines of a display image of the pixel array, and the sum of the active region period and the blank period in response to the total number of a plurality of horizontal lines of the pixel array.

Images