Ultraviolet light emitting diode and method of fabricating the same

Abstract

The present disclosure provides a kind of ultraviolet light emitting diode and its preparation method, belong to optoelectronic manufacturing technical field.The light emitting diode includes: substrate, epitaxial layer, first ohmic contact layer and first electrode;The epitaxial layer is stacked on the substrate, the epitaxial layer includes first semiconductor layer, multiple quantum well layer and second semiconductor layer successively stacked, the surface of the second semiconductor layer has the recess of exposing the first semiconductor layer;The first ohmic contact layer and the first electrode are all located in the recess, the first ohmic contact layer partial region is hollowed out, the first ohmic contact layer and the first electrode are successively stacked on the surface of the first semiconductor layer, and the first electrode is reflective electrode.The present disclosure can improve the light emitting effect of light emitting diode.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an ultraviolet light-emitting diode and its preparation method. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, a light-emitting diode (LED) typically comprises a substrate, an n-type layer, a multiple quantum well layer, and a p-type layer stacked sequentially. The p-type layer has a groove exposing the n-type layer, and electrodes are disposed both inside the groove and on the surface of the p-type layer. The side containing the substrate is usually the light-emitting surface of the LED. To improve the LED's luminous efficiency, an ohmic contact layer with reflective properties is disposed on the surface of the groove, reflecting light towards the light-emitting surface through the ohmic contact layer and the electrodes.

[0004] Because the reflective ohmic contact layer requires a high-temperature alloy with an operating temperature of 800℃ to 1100℃ to form ohmic characteristics with the n-type layer, the high-temperature alloy has poor reflectivity to violet light and will absorb most of the violet light, thus reducing the light emission effect of the ultraviolet light-emitting diode. Summary of the Invention

[0005] This disclosure provides an ultraviolet light-emitting diode and its fabrication method, which can improve the luminous efficacy of the ultraviolet light-emitting diode. The technical solution is as follows:

[0006] This disclosure provides a light-emitting diode (LED) comprising: a substrate, an epitaxial layer, a first ohmic contact layer, and a first electrode; the epitaxial layer is stacked on the substrate, and the epitaxial layer includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; the first ohmic contact layer and the first electrode are both located within the groove, a portion of the first ohmic contact layer is hollowed out, the first ohmic contact layer and the first electrode are stacked sequentially on the surface of the first semiconductor layer, and the first electrode is a reflective electrode.

[0007] In another implementation of the present disclosure, the first ohmic contact layer includes a plurality of spaced-apart block structures.

[0008] In another implementation of the present disclosure, the spacing between two adjacent block structures is 2 μm to 20 μm.

[0009] In another implementation of the present disclosure, the orthographic projection of the block structure onto the bearing surface of the substrate is rectangular, elliptical, circular, or triangular.

[0010] In one implementation of this disclosure, the distance between the two furthest points on the outer contour of the block structure projected onto the bearing surface is 2 μm to 20 μm.

[0011] In another implementation of the present disclosure, the first ohmic contact layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially stacked on the surface of the first semiconductor layer. The first metal layer includes a Cr layer or a Ti layer, the second metal layer includes an Al layer, the third metal layer includes a Ti layer or a Ni layer, and the fourth metal layer includes an Au layer.

[0012] In another implementation of the present disclosure, the light-emitting diode further includes a second ohmic contact layer and a second electrode, wherein the second ohmic contact layer and the second electrode are sequentially stacked on the surface of the second semiconductor layer, and the second ohmic contact layer is a light-transmitting layer.

[0013] In another implementation of the present disclosure, the orthographic projection of the second semiconductor layer onto the bearing surface of the substrate includes at least two spaced H-shaped structures, and the bearing surface is the side of the substrate that bears the epitaxial layer.

[0014] In another implementation of the present disclosure, a plurality of the block structures are arranged at intervals around the H-shaped structure.

[0015] This disclosure provides a method for fabricating a light-emitting diode (LED). The method includes: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer comprising a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; forming a first ohmic contact layer on the surface of the first semiconductor layer within the groove, the first ohmic contact layer having a partially hollowed-out area; and fabricating a first electrode on the surface of the first ohmic contact layer, the first electrode being a reflective electrode.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] This disclosure provides a light-emitting diode (LED) with a patterned first ohmic contact layer, where a portion of the first ohmic contact layer is designed as a hollow structure. This hollow structure prevents the first ohmic contact layer from blocking and absorbing light. Since the first electrode covers both the first ohmic contact layer and the hollow structure within it, violet light can still be reflected through the first electrode to the light-emitting surface of the LED. Compared to a full-surface ohmic contact layer, the hollow design significantly reduces the area of ​​the ohmic contact layer that receives violet light, thereby reducing the absorption of violet light and allowing more violet light to be reflected through the first electrode, thus improving the luminous efficacy of the ultraviolet LED. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0020] Figure 2 yes Figure 1 An AA cross-sectional view is provided;

[0021] Figure 3 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure;

[0022] Figure 4 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0023] Figure 5 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0024] Figure 6 yes Figure 5 A top view of a light-emitting diode is provided;

[0025] Figure 7 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure;

[0026] Figure 8 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure.

[0027] The markings in the diagram are explained as follows:

[0028] 10. Substrate;

[0029] 20. Epitaxial layer; 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor layer; 24. Groove; 25. Isolation trench;

[0030] 31. First electrode; 32. Second electrode;

[0031] 41. First ohmic contact layer; 411. Block structure; 42. Second ohmic contact layer;

[0032] 50. Insulating layer; 51. Through hole;

[0033] 61. First solder joint block; 62. Second solder joint block;

[0034] 70. AlN buffer layer. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 yes Figure 1 An AA cross-sectional view is provided. For example... Figure 1 , 2 As shown, the light-emitting diode includes: a substrate 10, an epitaxial layer 20, a first ohmic contact layer 41, and a first electrode 31.

[0037] like Figure 2 As shown, the epitaxial layer 20 is stacked on the substrate 10. The epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22 and a second semiconductor layer 23 stacked sequentially. The surface of the second semiconductor layer 23 has a groove 24 that exposes the first semiconductor layer 21.

[0038] like Figure 2 As shown, the first ohmic contact layer 41 and the first electrode 31 are both located in the groove 24, and the first ohmic contact layer 41 and the first electrode 31 are sequentially stacked on the surface of the first semiconductor layer 21.

[0039] like Figure 1 As shown, a portion of the first ohmic contact layer 41 is hollowed out, and the first electrode 31 covers the surface of the block structure 411 and the surface of the first semiconductor layer 21. The first electrode 31 is a reflective electrode.

[0040] Because a portion of the first ohmic contact layer is hollowed out, part of the first electrode is connected to the first ohmic contact layer, and another part is in contact with the first semiconductor layer.

[0041] This embodiment of the light-emitting diode (LED) provides a patterned design for the first ohmic contact layer 41, with a portion of the first ohmic contact layer 41 configured as a hollow structure. This hollow structure prevents the first ohmic contact layer 41 from blocking and absorbing light. Since the first electrode 31 covers both the first ohmic contact layer 41 and the hollow structure, violet light can still be reflected through the first electrode 31 to the light-emitting surface of the LED. Compared to a full-surface ohmic contact layer, the hollow design significantly reduces the area of ​​the ohmic contact layer that receives violet light, thereby reducing the absorption of violet light by the ohmic contact layer and allowing more violet light to be reflected through the first electrode 31, thus improving the luminous efficacy of the ultraviolet LED.

[0042] In this embodiment of the disclosure, a reflective electrode refers to an electrode that has a reflective effect. For example, a reflective electrode can be an electrode made of metal, especially an electrode made of metal with a high reflectivity to violet light.

[0043] Optionally, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0044] As an example, in this embodiment of the disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a flat sapphire substrate 10.

[0045] In this embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0046] As an example, the first semiconductor layer 21 is an n-type layer, and the first electrode 31 is an n-type electrode. The second semiconductor layer 23 is a p-type layer.

[0047] In this embodiment, to achieve ohmic properties between the n-type layer and the ohmic contact layer, the ohmic contact layer needs to be made of a high-temperature alloy with a temperature range of 800°C to 1100°C. Since the ohmic contact layer of the high-temperature alloy has extremely poor reflectivity for violet light, especially light with wavelengths from 200nm to 330nm, where the absorption rate is as high as 77% or more, when the first semiconductor layer 21 is an n-type layer, the first ohmic contact layer 41 is disposed on the surface of the first semiconductor layer 21 through a groove 24. This significantly reduces the area of ​​the first ohmic contact layer 41 that receives violet light due to its hollow design, thereby reducing the absorption of violet light by the ohmic contact layer.

[0048] It should be noted that when the first semiconductor layer 21 is a p-type layer and the second semiconductor layer 23 is an n-type layer, the hollowed-out ohmic contact layer can be directly disposed on the surface of the second semiconductor layer 23.

[0049] Optionally, the n-type layer can be an n-type AlGaN layer, and the thickness of the n-type AlGaN layer can be from 0.5 μm to 3 μm.

[0050] Optionally, the multi-quantum well layer 22 includes 3 to 8 Al x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layers, where 0 < x < y < 1. That is, the multi-quantum well layer 22 comprises alternating stacked Al phases of 3 to 8 periods. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0051] As an example, in this embodiment of the disclosure, the multi-quantum well layer 22 includes five alternating stacked periods of Al. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0052] For example, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0053] Optionally, the p-type layer can be a p-type AlGaN layer. The thickness of the p-type AlGaN layer can be from 0.5 μm to 3 μm.

[0054] Optionally, such as Figure 1 As shown, the first ohmic contact layer 41 includes a plurality of spaced block structures 411.

[0055] By designing the hollow first ohmic contact layer 41 into multiple spaced block structures 411, the gaps between the multiple block structures 411 will not block and absorb light. Since the gaps between the block structures 411 are provided with the first electrode 31, the violet light can also be reflected through the first electrode 31 and reflected to the light-emitting surface of the light-emitting diode.

[0056] Optionally, such as Figure 1 As shown, the spacing L between two adjacent block structures 411 is 2μm to 20μm.

[0057] By setting the spacing between two adjacent block structures within the aforementioned range, it is possible to avoid the light transmittance being affected by setting the spacing between the block structures too small, which would affect the amount of light reflected on the first electrode 31; it is also possible to avoid the ohmic characteristics between the first ohmic contact layer 41 and the semiconductor layer being affected by setting the spacing between the block structures too large, thus ensuring that the current spreads well on the semiconductor layer.

[0058] For example, the distance L between two adjacent block structures 411 is 10 μm.

[0059] Optionally, the orthographic projection of the block structure 411 onto the bearing surface of the substrate 10 is rectangular, elliptical, circular, or triangular.

[0060] The bearing surface is the side surface on the substrate 10 that bears the epitaxial layer 20.

[0061] For example, such as Figure 1 As shown, the orthographic projection of the block structure 411 onto the bearing surface of the substrate 10 is rectangular. Multiple rectangular blocks are arranged at intervals in the groove 24.

[0062] Optionally, the distance between the two furthest points on the outer contour of the block structure's orthographic projection onto the bearing surface is 2 μm to 20 μm.

[0063] For example, such as Figure 1 As shown, when the block structure 411 is rectangular, the distance between the two farthest points on the rectangle is the length of the rectangle's diagonal. For example, the length of the rectangle's diagonal can be 15 μm.

[0064] For example, when the block structure is elliptical, the distance between the two farthest points on the ellipse is the length of the ellipse's major axis. For instance, the length of the ellipse's major axis could be 12 μm.

[0065] For example, when the block structure is circular, the distance between the two farthest points on the circle is the diameter of the circle. For example, the diameter of the circle could be 12 μm.

[0066] For example, when the block structure is triangular, the distance between the two points farthest apart on the triangle is the length of the longest side of the triangle. For instance, the length of the longest side of the triangle could be 15 μm.

[0067] Optionally, the first ohmic contact layer 41 includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially stacked on the surface of the first semiconductor layer 21. The first metal layer includes a Cr layer or a Ti layer, the second metal layer includes an Al layer, the third metal layer includes a Ti layer or a Ni layer, and the fourth metal layer includes an Au layer.

[0068] In addition to forming a good ohmic contact with the first semiconductor layer 21, the first ohmic contact layer 41, made of the above four metal layers, can also have a certain reflective effect, reflecting light towards the light-emitting surface.

[0069] For example, the first ohmic contact layer 41 may include a Ti layer, an Al layer, a Ti layer and an Au layer stacked sequentially.

[0070] The thickness of the Cr or Ti layer in the first metal layer is 3 to 30 angstroms, the thickness of the Al layer in the second metal layer is 500 to 2000 angstroms, the thickness of the Ni or Ti layer in the third metal layer is 200 to 1000 angstroms, and the thickness of the Au layer in the fourth metal layer is 300 to 1200 angstroms.

[0071] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a second ohmic contact layer 42 and a second electrode 32. The second ohmic contact layer 42 and the second electrode 32 are sequentially stacked on the surface of the second semiconductor layer 23. The second ohmic contact layer 42 is a light-transmitting layer.

[0072] The light transmittance of the light-transmitting layer can be 80% to 100%, so that the second ohmic contact layer 42 can transmit most of the light, which is beneficial for the second electrode 32 to reflect light to the light-emitting surface.

[0073] For example, the second semiconductor layer 23 is a p-type layer, and the second electrode 32 is a p-electrode.

[0074] Optionally, both the first electrode 31 and the second electrode 32 may comprise, from bottom to top, a Cr or Ti layer, an Al layer, a Ti or Ni layer, a Pt layer, a Ti or Ni layer, a Pt layer, an Au layer, and a Ti layer. This type of electrode has excellent reflectivity, reflecting most of the light towards the light-emitting surface, thus improving the luminous efficacy of the LED.

[0075] In the above implementation, setting the second ohmic contact layer 42 as a light-transmitting layer is beneficial to improving the light transmittance, allowing more light to pass through the second ohmic contact layer 42 and be directed to the second electrode 32, thereby reflecting most of the light towards the light-emitting surface and improving the light-emitting effect of the light-emitting diode.

[0076] Optionally, the second ohmic contact layer 42 is a metal oxide layer, wherein the metal in the metal oxide layer includes at least one of nickel, indium, tin, chromium, gold, zinc, rhodium and platinum.

[0077] As an example, the second ohmic contact layer 42 can be an indium tin oxide (ITO) layer. The thickness of the ITO layer is from 10 angstroms to 1000 angstroms.

[0078] In some other implementations, the second ohmic contact layer 42 can also be a reflective material layer.

[0079] For example, the reflective material layer may be a Cr layer or Ti layer, an Al layer, a Ni layer or a Ti layer and an Au layer stacked sequentially.

[0080] The thickness of the Cr or Ti layer is 3 to 30 angstroms, the thickness of the Al layer is 500 to 2000 angstroms, the thickness of the Ni or Ti layer is 200 to 1000 angstroms, and the thickness of the Au layer is 300 to 1200 angstroms.

[0081] Optionally, such as Figure 1 As shown, the orthographic projection of the second semiconductor layer 23 onto the bearing surface of the substrate 10 includes at least two spaced H-shaped structures.

[0082] For example, the orthographic projection of the second semiconductor layer 23 onto the bearing surface of the substrate 10 includes two spaced-apart H-shaped structures.

[0083] The second semiconductor layer 23 is arranged in a meandering pattern on the substrate 10, so that the second semiconductor layer 23 has a larger area, and the light-emitting area of ​​the epitaxial layer 20 is also larger. Since the area of ​​the second semiconductor layer 23 is larger, the current density on the second semiconductor layer 23 can be reduced, the heat generation of the light-emitting diode is reduced, and the light-emitting diode has a larger current driving space.

[0084] Optionally, such as Figure 1 As shown, multiple block structures 411 are arranged at intervals around the H-shaped structure. Designing the block structures to be arranged around the H-shaped structure allows the block structures to cover most of the groove area, enabling the first electrode to form an effective ohmic contact with most of the exposed surface of the first semiconductor layer, facilitating the spread of current through the first electrode to the first semiconductor layer.

[0085] Optionally, such as Figure 2 As shown, the first electrode 31 is located on the first ohmic contact layer 41, and the orthographic projection of the first ohmic contact layer 41 on the surface of the first semiconductor layer 21 is located within the orthographic projection of the first electrode 31 on the surface of the first semiconductor layer 21.

[0086] like Figure 2 As shown, the second electrode 32 is located on the second ohmic contact layer 42, and the orthographic projection of the second electrode 32 on the surface of the second semiconductor layer 23 is located within the orthographic projection of the second ohmic contact layer 42 on the surface of the second semiconductor layer 23.

[0087] Extending the first electrode 31 from the first ohmic contact layer 41 to the first semiconductor layer 21 reduces voltage and improves chip stability. The second electrode 32 does not extend from the second ohmic contact layer 42 to the second semiconductor layer 23 to avoid an excessively large area of ​​the second electrode 32, which would increase manufacturing costs.

[0088] Optionally, such as Figure 2As shown, the light-emitting diode also includes an insulating layer 50, a first solder joint block 61, and a second solder joint block 62. The insulating layer 50 is located at least on the first semiconductor layer 21, the groove 24, the first electrode 31, the second semiconductor layer 23, the second ohmic contact layer 42, and the second electrode 32. The insulating layer 50 has through holes 51 exposing the first electrode 31 and the second electrode 32. The first solder joint block 61 and the second solder joint block 62 are both located on the insulating layer 50. The first solder joint block 61 is connected to the first electrode 31 through the through hole 51, and the second solder joint block 62 is connected to the second electrode 32 through the through hole 51. The solder joint blocks are provided to facilitate chip power supply.

[0089] For example, the first solder joint block 61 and the second solder joint block 62 have the same layer structure. Both the first solder joint block 61 and the second solder joint block 62 include Ti layer, Al layer, Ti layer or Ni layer, Pt layer, Au layer stacked in sequence, and 8 to 15 pairs of Sn layers and Au layer stacked on Au layer to form a superimposed layer.

[0090] The thickness of the first solder joint block 61 and the second solder joint block 62 is 5μm to 8μm.

[0091] For example, the insulating layer 50 is a SiO2 film or a SiN film. x The thickness ranges from 6,000 angstroms to 15,000 angstroms. As an example, the thickness of insulation layer 50 is 10,000 angstroms.

[0092] Optionally, such as Figure 2 As shown, the second semiconductor layer 23 also includes an isolation trench 25 exposing the substrate 10, and the isolation trench 25 surrounds the epitaxial layer 20. Specifically, the isolation trench 25 surrounds the first semiconductor layer 21, the multiple quantum well layer 22, and the second semiconductor layer 23. The isolation trench 25 facilitates subsequent slicing after fabrication.

[0093] For example, the width of the isolation groove 25 is from 5 μm to 50 μm. For instance, the width of the isolation groove 25 is 10 μm.

[0094] Optionally, such as Figure 2 As shown, an AlN buffer layer 70 is also provided between the substrate 10 and the first semiconductor layer 21, which can provide a good foundation for subsequent growth and is beneficial to improving the crystal quality of the epitaxial wafer.

[0095] For example, the thickness of the AlN buffer layer 70 is 1 μm to 5 μm. The thickness of the AlN buffer layer 70 affects the quality of the epitaxial wafer. If the AlN buffer layer 70 is too thin, the surface of the AlN buffer layer 70 will be relatively loose and rough, which cannot provide a good template for the growth of subsequent structures. Within this thickness range, the surface of the AlN buffer layer 70 is relatively dense and flat, which is beneficial to the growth of subsequent structures.

[0096] Examples of implementations of this disclosure are as follows:

[0097] In Example 1, the first ohmic contact layer comprises multiple spaced-apart block structures. Each block structure is rectangular in shape, with a 10 μm spacing between adjacent blocks and a 10 μm diagonal distance between the blocks. Five LED chips were tested at a test voltage of 5.2V, and the average optical power of the LEDs was 7.40 mW.

[0098] In Example 2, the first ohmic contact layer comprises multiple spaced-apart block structures. Each block structure is rectangular in shape, with a spacing of 15 μm between adjacent blocks and a diagonal distance of 10 μm between the blocks. Five LED chips were tested at a test voltage of 5.2V, and the average optical power of the LEDs was 7.44 mW.

[0099] In Example 3, the first ohmic contact layer comprises multiple spaced-apart block structures. Each block structure is rectangular in shape, with a spacing of 10 μm between adjacent blocks and a diagonal distance of 15 μm between the blocks. Five LED chips were tested at a test voltage of 5.2V, and the average optical power of the LEDs was 7.3 mW.

[0100] In Example 4, the first ohmic contact layer is a solid film layer (without cutouts). Five LED chips were tested at a test voltage of 5.2V, and the average optical power of the LEDs was 7mW.

[0101] According to the comparative embodiments, the light-emitting diode provided in this disclosure, compared with a light-emitting diode having a full-layer ohmic contact layer (without cutouts), can increase the light power of the light-emitting diode by an average of more than 4.28% under the condition of ensuring the same voltage.

[0102] Figure 3 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 3 As shown, the preparation method includes:

[0103] Step S11: Provide a substrate 10.

[0104] The substrate 10 is a sapphire substrate 10. The sapphire substrate 10 can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment, the sapphire substrate 10 is baked for 15 minutes.

[0105] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0106] Step S12: Form an epitaxial layer 20 on the substrate 10.

[0107] like Figure 4 As shown, before step S12, the method further includes growing an AlN buffer layer 70 on the substrate 10.

[0108] AlN buffer layers 70 were grown using MOCVD. The growth temperature was 1000℃ to 1500℃, the growth pressure was 50 mbar to 100 mbar, ammonia and trimethylaluminum were used as reactants, the V / III molar ratio was 350 to 3500, and the growth time was 500 s to 5000 s.

[0109] like Figure 4 As shown, step S12 may include: growing a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 sequentially on the AlN buffer layer 70.

[0110] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0111] Optionally, the n-type layer can be an n-type AlGaN layer, and the thickness of the n-type AlGaN layer can be from 0.5 μm to 3 μm.

[0112] Optionally, the multi-quantum well layer 22 includes 3 to 8 Al x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layers, where 0 < x < y < 1. That is, the multi-quantum well layer 22 comprises alternating stacked Al phases of 3 to 8 periods. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0113] For example, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0114] Optionally, the p-type layer can be a p-type AlGaN layer. The thickness of the p-type AlGaN layer can be from 0.5 μm to 3 μm.

[0115] like Figure 4 As shown, in step S12, the fabrication method further includes: etching the patterned epitaxial wafer surface using photolithography and dry etching techniques to etch through the p-type layer, the multiple quantum well layer 22, and part of the n-type layer, so that the n-type layer is exposed on the surface of the p-type layer.

[0116] Before step S13, the process may further include: after photolithography and development on the n-type AlGaN layer of the light-emitting diode, using ICP dry etching technology to create an isolation trench 25 on the n-type AlGaN layer that extends from the n-type AlGaN layer through the AlN buffer layer 70 to the sapphire substrate 10.

[0117] Step S13: Form a first ohmic contact layer on the surface of the first semiconductor layer within the groove.

[0118] In particular, a portion of the first ohmic contact layer is hollowed out.

[0119] like Figure 5 As shown, step S13 may include: preparing a first ohmic contact layer 41 in the groove 24 using photolithography, vacuum deposition and rapid annealing techniques.

[0120] The first ohmic contact layer 41 may be a Cr layer or Ti layer, an Al layer, a Ni layer or a Ti layer and an Au layer stacked sequentially on the surface of the groove 24.

[0121] For example, such as Figure 6 As shown, the first ohmic contact layer 41 includes a plurality of spaced block structures 411.

[0122] Optionally, such as Figure 6 As shown, the spacing L between two adjacent block structures 411 is 2μm to 20μm.

[0123] For example, the distance L between two adjacent block structures 411 is 10 μm.

[0124] Optionally, the orthographic projection of the block structure onto the bearing surface of the substrate 10 is rectangular, elliptical, circular, or triangular. The bearing surface is the side of the substrate 10 with the epitaxial layer 20.

[0125] For example, such as Figure 6 As shown, the orthographic projection of the block structure 411 onto the bearing surface of the substrate 10 is rectangular. Multiple rectangular blocks are arranged at intervals in the groove 24.

[0126] Optionally, the distance between the two furthest points on the outer contour of the block structure's orthographic projection onto the bearing surface is 2 μm to 20 μm.

[0127] For example, such as Figure 6 As shown, when the block structure 411 is rectangular, the distance between the two farthest points on the rectangle is the length of the rectangle's diagonal. For example, the length of the rectangle's diagonal can be 15 μm.

[0128] like Figure 7As shown, after the first ohmic contact layer 41 is fabricated, the fabrication method may further include: fabricating a second ohmic contact layer 42 with high transmittance in the ultraviolet band on the surface of the second semiconductor layer 23 by photolithography, vacuum deposition and rapid annealing.

[0129] Optionally, the second ohmic contact layer 42 is a metal oxide layer, and the metal in the metal oxide layer includes nickel, indium, tin, chromium, gold, zinc, rhodium and platinum.

[0130] As an example, the second ohmic contact layer 42 can be an indium tin oxide (ITO) layer. The thickness of the ITO layer is from 10 angstroms to 1000 angstroms.

[0131] Step S14: Fabricate the first electrode on the surface of the first ohmic contact layer.

[0132] like Figure 7 As shown, the first electrode 31 is located at least on the surface of the bulk structure 411 and the surface of the semiconductor layer.

[0133] Step S14 includes: fabricating a first electrode 31 with high reflectivity in the ultraviolet band in the first ohmic contact layer 41 by photolithography and vacuum deposition techniques.

[0134] like Figure 7 As shown, after step S14, a second electrode 32 with high reflectivity in the ultraviolet band may also be prepared on the second ohmic contact layer 42.

[0135] After fabricating the first electrode 31 and the second electrode 32, the following steps can be taken:

[0136] First step, such as Figure 8 As shown, a SiO2 film, i.e., the insulating layer 50, is deposited on the chip surface by plasma-enhanced chemical vapor deposition.

[0137] During the deposition of insulating layer 50, the deposition rate can be controlled in stages, with slow growth in the early stage, rapid growth in the middle stage, and slow growth in the later stage. The thickness of insulating layer 50 can be from 6000 angstroms to 15000 angstroms.

[0138] The second step is to etch through-hole 51 on the insulating layer 50 using photolithography and dry etching techniques, so that the through-hole 51 exposes the first electrode 31 and the second electrode 32.

[0139] The third step involves forming a symmetrical and mutually isolated first solder block 61 and second solder block 62 on the insulating layer 50 using photolithography and vacuum deposition techniques.

[0140] The first solder joint block 61 is in contact with the first electrode 31 through a through hole 51, and the second solder joint block 62 is in contact with the second electrode 32 through a through hole 51.

[0141] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes: a substrate (10), an epitaxial layer (20), a first ohmic contact layer (41), and a first electrode (31); The epitaxial layer (20) is stacked on the substrate (10). The epitaxial layer (20) includes a first semiconductor layer (21), a multiple quantum well layer (22), and a second semiconductor layer (23) stacked sequentially. The surface of the second semiconductor layer (23) has a groove (24) that exposes the first semiconductor layer (21). The first ohmic contact layer (41) and the first electrode (31) are both located in the groove (24). The first ohmic contact layer (41) has a partially hollowed-out area. The first ohmic contact layer (41) is an alloy layer. The first ohmic contact layer (41) includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked sequentially on the surface of the first semiconductor layer (21). The first metal layer includes a Cr layer or a Ti layer, the second metal layer includes an Al layer, the third metal layer includes a Ti layer or a Ni layer, and the fourth metal layer includes an Au layer. The first ohmic contact layer (41) and the first electrode (31) are stacked sequentially on the surface of the first semiconductor layer (21). The first electrode (31) is a reflective electrode.

2. The light-emitting diode according to claim 1, characterized in that, The first ohmic contact layer (41) includes a plurality of spaced block structures (411).

3. The light-emitting diode according to claim 2, characterized in that, The spacing between two adjacent block structures (411) is 2 μm to 20 μm.

4. The light-emitting diode according to claim 2, characterized in that, The orthographic projection of the block structure (411) onto the bearing surface of the substrate (10) is rectangular, elliptical, circular, or triangular.

5. The light-emitting diode according to claim 4, characterized in that, The distance between the two furthest points on the outer contour of the block structure (411) projected onto the bearing surface is 2 μm to 20 μm.

6. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The light-emitting diode further includes a second ohmic contact layer (42) and a second electrode (32), the second ohmic contact layer (42) and the second electrode (32) being stacked sequentially on the surface of the second semiconductor layer (23), and the second ohmic contact layer (42) being a light-transmitting layer.

7. The light-emitting diode according to any one of claims 2 to 5, characterized in that, The orthographic projection of the second semiconductor layer (23) onto the bearing surface of the substrate (10) includes at least two spaced H-shaped structures, the bearing surface being the side of the substrate (10) that bears the epitaxial layer (20).

8. The light-emitting diode according to claim 7, characterized in that, Multiple block structures (411) are arranged at intervals around the H-shaped structure.

9. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Provide a substrate; An epitaxial layer is formed on the substrate, the epitaxial layer comprising a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked sequentially, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; A first ohmic contact layer is formed on the surface of the first semiconductor layer within the groove. A portion of the first ohmic contact layer is hollowed out. The first ohmic contact layer is an alloy layer. The first ohmic contact layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially stacked on the surface of the first semiconductor layer. The first metal layer includes a Cr layer or a Ti layer, the second metal layer includes an Al layer, the third metal layer includes a Ti layer or a Ni layer, and the fourth metal layer includes an Au layer. A first electrode is fabricated on the surface of the first ohmic contact layer, and the first electrode is a reflective electrode.

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