Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate, a gate structure, source / drain doped regions in the substrate on both sides of the gate structure, and a bottom dielectric layer on the substrate on the sides of the gate structure; forming a source / drain interconnection layer extending through the top of the source / drain doped regions; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact hole extending through the top dielectric layer on the top of the gate structure and a source / drain contact hole extending through the top dielectric layer on the top of the source / drain interconnection layer; forming a sacrificial sidewall layer on the sidewalls of the gate contact hole and the source / drain contact hole; forming a gate plug filling the gate contact hole and a source / drain plug filling the source / drain contact hole; removing the sacrificial sidewall layer to form a first gap; and forming a sealing layer to seal the first gap, so that at least one of the first gaps on the sidewalls of the source / drain plug and the sidewalls of the gate plug forms a first air gap with the sealing layer. Embodiments of the present invention are advantageous for reducing parasitic capacitance between the gate plug and the source / drain plug.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the requirements for integrated circuit integration and performance are becoming increasingly stringent. To increase integration and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density within integrated circuits is increasing. This development has resulted in insufficient surface area on the wafer to produce the required interconnects.

[0003] To meet the interconnect requirements of shrinking critical dimensions, current interconnect structures are used to connect different metal layers, or between a metal layer and a substrate. These structures include interconnects and contact plugs formed within contact openings. The contact plugs connect to the semiconductor device, while the interconnects connect the contact plugs to each other, thus forming a circuit. Contact plugs within transistor structures include gate contact plugs located on the gate structure, which connect the gate structure to external circuits, and source / drain contact plugs located on the source / drain doped regions, which connect the source / drain doped regions to external circuits.

[0004] Currently, to further reduce transistor area, the Contact Over Active Gate (COAG) process has been introduced. Compared to the traditional gate contact plug located above the gate structure in the isolation area, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a gate structure located on the substrate, source-drain doped regions in the substrate on both sides of the gate structure, and a bottom dielectric layer located on the substrate on the side of the gate structure and covering the source-drain doped regions; forming a bottom dielectric layer passing through the top of the source-drain doped regions and a source-drain interconnection layer in contact with the source-drain doped regions; forming a top dielectric layer on the bottom dielectric layer, covering the gate structure and the source-drain interconnection layer; forming a gate contact hole passing through the top of the gate structure and exposing the top of the gate structure, and a gate contact hole passing through the top dielectric layer; forming a gate contact hole passing through the top dielectric layer and exposing the top of the gate structure. A top dielectric layer is formed on top of the source-drain interconnection layer, exposing the source-drain contact hole on top of the source-drain interconnection layer; a sacrificial sidewall layer is formed on the sidewalls of the gate contact hole and the source-drain contact hole; a gate plug filling the gate contact hole and a source-drain plug filling the source-drain contact hole are formed on the sacrificial sidewall layer; the sacrificial sidewall layer is removed to form a first gap exposing the sidewalls of the gate plug and the sidewalls of the source-drain plug; a sealing layer is formed to seal the first gap, so that at least one of the first gap located on the sidewall of the source-drain plug and the first gap located on the sidewall of the gate plug forms a first air gap with the sealing layer.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source-drain doped regions located in the substrate on both sides of the gate structure; a source-drain interconnection layer located on top of the source-drain doped regions and in contact with the source-drain doped regions; a gate plug located on top of the gate structure and in contact with the gate structure; a source-drain plug located on top of the source-drain interconnection layer and in contact with the source-drain plug; a dielectric layer covering the sidewalls of the gate plug and the source-drain plug, and filling a gap between the gate plug and the source-drain plug; a first gap located between the sidewall of the gate plug and the dielectric layer, and between the sidewall of the source-drain plug and the dielectric layer; a sealing layer located on the dielectric layer and sealing the first gap, wherein at least one of the first gap located on the sidewall of the source-drain plug and the first gap located on the sidewall of the gate plug and the sealing layer forms a first air gap.

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the gate contact hole and the source-drain contact hole, a sacrificial sidewall layer is formed on the sidewalls of the gate contact hole and the source-drain contact hole, and then a gate plug filling the gate contact hole and a source-drain plug filling the source-drain contact hole are formed on the sacrificial sidewall layer, and the sacrificial sidewall layer is removed to form a first gap exposing the sidewalls of the gate plug and the sidewalls of the source-drain plug, and then a sealing layer is formed on the gate plug and the source-drain plug to seal the first gap, so that the sidewalls of the source-drain plug are At least one of the first gap and the first gap located on the sidewall of the gate plug forms a first air gap with the sealing layer. In this embodiment of the present invention, a sacrificial sidewall layer is first formed to occupy the first gap. After forming the gate plug and the source / drain plug, the sacrificial sidewall layer is removed, thereby forming a first gap on the sidewall of the gate plug and the sidewall of the source / drain plug. The top of the first gap is then sealed, so that at least one of the first gap located on the sidewall of the source / drain plug and the first gap located on the sidewall of the gate plug forms a first air gap with the sealing layer. The air gap has a lower dielectric constant than commonly used dielectric materials (e.g., low-k dielectric materials or ultra-low-k dielectric materials) in semiconductor processes, thereby reducing parasitic capacitance (Parasitic Capacitance) between the gate plug and the source / drain plug, reducing RC (resistance-capacitance) delay, and thereby improving the performance of the semiconductor structure.

[0009] In an optional solution, the substrate includes an active area; the formation method further includes: after providing the substrate and before forming the source-drain interconnection layer, removing a portion of the thickness of the gate structure and forming a gate cap layer on top of the remaining gate structure; the gate contact hole penetrates the gate cap layer and the top dielectric layer on top of the gate structure in the active area; accordingly, in the step of forming the gate plug, the gate plug is located above the gate structure in the active area, and the gate plug is a contact over active gate (COAG). Compared with a traditional gate plug located in an isolation area, the distance between the gate plug and the source-drain plug in the embodiment of the present invention is closer. By forming a first gap on the sidewalls of the gate plug and the sidewalls of the source-drain plug, and sealing the first gap to form a first air gap on at least one sidewall of the source-drain plug and the gate plug, the parasitic capacitance between the gate plug and the source-drain plug is significantly reduced, the RC delay is reduced, and the performance of the semiconductor structure is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] As can be seen from the background art, the COAG process is beneficial for saving chip area. However, the devices currently formed still have the problem of poor performance. Specifically, in the COAG process, the gate contact plug formed by the COAG process is located above the gate structure in the active area (AA). Compared with the traditional gate contact plug located above the gate structure in the isolation area, the distance between the gate contact plug and the source and drain contact plugs is closer, which can easily lead to excessive parasitic capacitance between the gate contact plug and the source and drain contact plugs, resulting in poor device performance.

[0012] To solve the technical problem, in a method for forming a semiconductor structure provided in an embodiment of the present invention, a sacrificial sidewall layer is first formed to occupy a position for a first gap. After forming a gate plug and a source / drain plug, the sacrificial sidewall layer is removed, thereby forming a first gap on the sidewall of the gate plug and the sidewall of the source / drain plug. The top of the first gap is then sealed, so that at least one of the first gap located on the sidewall of the source / drain plug and the first gap located on the sidewall of the gate plug and the sealing layer forms a first air gap. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (for example, low-k dielectric materials or ultra-low-k dielectric materials), thereby facilitating reduction of parasitic capacitance between the gate plug and the source / drain plug, reducing RC delay, and thereby improving the performance of the semiconductor structure.

[0013] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Figures 1 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0015] refer to Figures 1 to 5 , providing a substrate 100, a gate structure 110 located on the substrate 100, source and drain doped regions 130 in the substrate 100 located on both sides of the gate structure 110, and a bottom dielectric layer 135 located on the side of the gate structure 110 on the substrate 100 and covering the source and drain doped regions 130.

[0016] The substrate 100 is used to provide a process platform for subsequent processes. In this embodiment, the substrate 100 is a planar substrate. In other embodiments, the substrate can also be a three-dimensional substrate, for example, comprising a substrate and fins protruding from the substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other materials. The substrate 100 includes an active area (AA) 100a.

[0017] The gate structure 110 serves as the device gate, controlling the on / off switching of the conductive channel during device operation. In this embodiment, the gate structure 110 is a metal gate structure formed by forming a high-k gate dielectric layer followed by a gate electrode layer (high-k last metal gate last) process.

[0018] The source-drain doped region 130 is used to provide a carrier source when the device is operating.

[0019] The bottom dielectric layer 135 is used to isolate adjacent devices. The material of the bottom dielectric layer 135 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the bottom dielectric layer 135 is silicon oxide.

[0020] In this embodiment, a dummy sidewall 120 in contact with the sidewall of the gate structure 110 and a contact etch stop layer (CESL) 140 located on the sidewall of the dummy sidewall 120 are formed between the sidewall of the gate structure 110 and the bottom dielectric layer 135. The contact etch stop layer 140 is also located between the source and drain doped regions 130 and the bottom dielectric layer 135.

[0021] Subsequent steps also include: removing the dummy sidewall 120 to form a second gap exposing the sidewall of the gate structure 110, and the second gap is located between the contact etch stop layer 140 and the sidewall of the gate structure 110. Therefore, the dummy sidewall 120 is used to occupy space for forming the second gap, thereby subsequently forming a covering dielectric layer that seals the second gap, and the dielectric constant of the covering dielectric layer material is lower than the dielectric constant of the dummy sidewall 120 material. Correspondingly, the material on the sidewall of the gate structure 110 has a lower dielectric constant, which is beneficial to reducing the parasitic capacitance of the semiconductor structure, for example: reducing the effective capacitance between the gate structure 110 and the subsequently formed source-drain interconnection layer, thereby helping to improve the performance of the semiconductor structure.

[0022] Moreover, the subsequent covering dielectric layer is made of a material with a lower dielectric constant, such as a low-k dielectric material or an ultra-low-k dielectric material. In order to make the material of the covering dielectric layer have a lower dielectric constant, the material of the covering dielectric layer is usually a material with a looser structure and lower density. By first forming a dummy sidewall 120 to occupy the second gap, the material of the dummy sidewall 120 can be flexibly selected, so that the material of the dummy sidewall 120 is compatible with the subsequent process (for example, the dielectric constant requirement for the dummy sidewall 120 material is low). Accordingly, a material with higher density and etching resistance can be selected as the material of the dummy sidewall 120, which is beneficial to reducing the probability of the dummy sidewall 120 being damaged or removed by mistaken etching during the formation of the semiconductor structure, and is beneficial to ensuring the integrity of the dummy sidewall 120, and correspondingly ensuring that the size and position of the second gap meet the design requirements, and further beneficial to ensuring the insulation effect between the gate structure 110 and other conductive structures (for example, the source-drain interconnection layer), thereby improving the performance of the semiconductor structure.

[0023] Specifically, in this embodiment, the process of forming the source-drain doped region 130 includes a pre-cleaning step, and the formation of the gate structure 110 includes a step of removing the dummy gate structure to form a gate opening exposing the dummy side wall 120. The dummy side wall 120 has high density and etching resistance, which helps to reduce the probability of the dummy side wall 120 being mistakenly etched in these two steps.

[0024] In this embodiment, the material of the dummy spacer 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. As an example, the material of the dummy spacer 120 is an oxygen-containing material. Specifically, the material of the dummy spacer 120 is silicon oxide. Silicon oxide is a readily available insulating material commonly used in semiconductor processes, which helps improve the compatibility of the dummy spacer 120 with existing processes, reduces process risks, and saves costs.

[0025] The thickness of the dummy sidewall spacer 120 should not be too small, otherwise the width of the second gap formed later will be too small in the direction perpendicular to the sidewalls of the gate structure 110, making it difficult for the material of the subsequent top dielectric layer to fill the second gap, resulting in a poor effect on reducing the effective capacitance between the gate structure 110 and the source-drain interconnect layer. The thickness of the dummy sidewall spacer 120 should not be too large, otherwise the channel length in the direction perpendicular to the sidewalls of the gate structure 110 will be too long, making it difficult to meet the requirements of device miniaturization. To this end, the thickness of the dummy sidewall spacer 120 in the direction parallel to the surface of the substrate 100 and perpendicular to the sidewalls of the gate structure 110 is 2nm to 12nm.

[0026] Subsequently, a source-drain interconnection layer is formed in the bottom dielectric layer 135 on top of the source-drain doped region 130 to contact the source-drain doped region 130. The process of forming the source-drain interconnection layer includes the step of etching the bottom dielectric layer 135 to form an interconnection through-hole. The contact etch stop layer 140 is used to temporarily define the etching stop position during the formation of the interconnection through-hole, thereby improving the etching consistency and preventing the source-drain doped region 130 from being damaged.

[0027] In this embodiment, the contact etch stop layer 140 is made of a low-k dielectric material or an ultra-low-k dielectric material. This allows the contact etch stop layer 140 located between the dummy sidewall spacer 120 and the bottom dielectric layer 135 to further reduce the effective capacitance between the gate structure 110 and the source-drain interconnect layer. In other embodiments, the contact etch stop layer may also be made of silicon nitride.

[0028] In this embodiment, an anti-diffusion layer 125 is further formed between the dummy sidewall spacer 120 and the contact etch stop layer 140 to prevent easily diffusible ions in the dummy sidewall spacer 120 from diffusing into the contact etch stop layer 140, thereby preventing the ion diffusion from adversely affecting the material of the contact etch stop layer 140. For example, if the dummy sidewall spacer 120 is made of an oxygen-containing material (e.g., silicon oxide), when oxygen ions diffuse into the contact etch stop layer 140, the dielectric constant of the contact etch stop layer 140 increases. By forming the anti-diffusion layer 125, the probability of the dielectric constant of the contact etch stop layer 140 increasing can be reduced.

[0029] Therefore, the density of the diffusion prevention layer 125 is relatively high, and the diffusion prevention layer 125 is subsequently retained. The material of the diffusion prevention layer 125 is an insulating material. Specifically, the material of the diffusion prevention layer 125 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the diffusion prevention layer 125 is silicon nitride.

[0030] It should be noted that after the source-drain interconnection layer is subsequently formed, the anti-diffusion layer 125 is also located between the source-drain interconnection layer and the gate structure 110, and the anti-diffusion layer 125 will also affect the effective capacitance between the source-drain interconnection layer and the gate structure 110. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 125 on ions, in order to prevent the effective capacitance between the source-drain interconnection layer and the gate structure 110 from being too large, and to prevent the distance between the source-drain interconnection layer and the gate structure 110 from being too large and occupying too much chip area, the thickness of the anti-diffusion layer 125 is less than or equal to In this embodiment, the thickness of the anti-diffusion layer 125 is less than or equal to When the thickness of the anti-diffusion layer 125 is too small, the function of the anti-diffusion layer 125 in preventing ion diffusion may be deteriorated. Therefore, in this embodiment, the thickness of the anti-diffusion layer 125 is to

[0031] The steps of providing the substrate 100 of the present invention are described in detail below with reference to the accompanying drawings.

[0032] like Figure 1 As shown, a substrate 100 is formed; and a dummy gate structure 115 is formed on the substrate 100 .

[0033] The dummy gate structure 115 is used to occupy space for forming a gate structure. The dummy gate structure 115 is a single-layer or stacked-layer structure. In this embodiment, the dummy gate structure 115 is a single-layer structure, and the material of the dummy gate structure 115 is polysilicon.

[0034] like Figure 1 As shown, a dummy spacer 120 is formed on the sidewall of the dummy gate structure 115. In this embodiment, the dummy spacer 120 is also formed on the top of the dummy gate structure 115 and on the substrate 100.

[0035] In this embodiment, the process for forming the dummy sidewall spacer 120 includes an atomic layer deposition process, which has a high step coverage capability and is also beneficial for improving the thickness uniformity of the dummy sidewall spacer 120 .

[0036] In this embodiment, before forming the dummy spacer 120, the formation method further includes forming an offset spacer 105 on the sidewall of the dummy gate structure 115. The offset spacer 105 is used to increase the channel length of the formed transistor to improve the short channel effect and the hot carrier effect caused by the short channel effect.

[0037] In this embodiment, the offset spacer 105 is further formed on the top of the dummy gate structure 115 and on the substrate 100 . Accordingly, the dummy spacer 120 is formed on the offset spacer 105 .

[0038] The offset spacer 105 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxynitride, silicon boron nitride oxynitride, or silicon carbon boron nitride oxynitride. In this embodiment, the offset spacer 105 is made of silicon nitride.

[0039] like Figure 2 As shown, source and drain doped regions 130 are formed in the substrate 100 on both sides of the dummy gate structure 115 .

[0040] In this embodiment, before forming the source / drain doped regions 130 , the formation method further includes: removing the dummy sidewalls 120 and the offset sidewalls 105 on the substrate 100 on both sides of the dummy gate structure 115 , exposing the surface of the substrate 100 on both sides of the dummy gate structure 115 , thereby preparing for forming the source / drain doped regions 130 .

[0041] like Figure 3As shown, a contact etch stop layer 140 is formed to conformally cover the dummy sidewall spacers 120 and the source / drain doped regions 130. In this embodiment, before forming the contact etch stop layer 140, an anti-diffusion layer 125 is formed to conformally cover the dummy sidewall spacers 120 and the source / drain doped regions 130. Accordingly, the contact etch stop layer 140 is formed on the anti-diffusion layer 125.

[0042] The process for forming the anti-diffusion layer 125 includes an atomic layer deposition process, a chemical vapor deposition process, or a plasma-enhanced chemical vapor deposition process. In this embodiment, the anti-diffusion layer 125 is formed using the atomic layer deposition process, which facilitates forming a thin anti-diffusion layer 125 with good thickness uniformity and density. In addition, the anti-diffusion layer 125 also has good step coverage.

[0043] like Figure 4 As shown, a bottom dielectric layer 135 exposing the top of the dummy gate structure 115 is formed on the contact etch stop layer 140 on both sides of the dummy gate structure 115 .

[0044] In this embodiment, the step of forming the bottom dielectric layer 135 includes: forming an initial dielectric layer (not shown) on the substrate 100 to cover the top of the dummy gate structure 115; and removing the initial dielectric layer above the top of the dummy gate structure 115 to form the bottom dielectric layer 135. In this embodiment, during the step of removing the initial dielectric layer above the top of the dummy gate structure 115, the offset spacer 105, the dummy spacer 120, the anti-diffusion layer 125, and the etch stop layer 140 located on the top of the dummy gate structure 115 are also removed, thereby exposing the top of the dummy gate structure 115 to facilitate the subsequent removal of the dummy gate structure 115.

[0045] like Figure 5 As shown, the dummy gate structure 115 is removed to form a gate opening (not shown); and a gate structure 110 is formed in the gate opening.

[0046] Combined with reference Figure 6 In this embodiment, the formation method further includes: after providing the substrate 100, removing a portion of the gate structure 110, and forming a gate cap layer 145 on top of the remaining gate structure 110. In this embodiment, the top surface of the gate cap layer 145 is flush with the top surface of the bottom dielectric layer 135.

[0047] The gate cap layer 145 is used to protect the top of the gate structure 110 during the subsequent formation of the source-drain interconnection layer and the source-drain plug, thereby reducing the probability of damage to the gate structure 110 and short circuit problems between the gate structure 110 and the source-drain interconnection layer or the source-drain plug.

[0048] Subsequently, a source-drain capping layer is formed on the top surface of the source-drain interconnection layer to protect the top of the source-drain interconnection layer. Therefore, the gate capping layer 145 is selected from a material that has etching selectivity with the source-drain capping layer, the bottom dielectric layer 135, and the subsequently formed dielectric layer, thereby ensuring that the gate capping layer 145 protects the gate structure 110. In this embodiment, the material of the gate capping layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 145 is silicon nitride.

[0049] refer to Figure 7 , forming a bottom dielectric layer 135 that passes through the top of the source / drain doped region 130 and a source / drain interconnection layer 150 that contacts the source / drain doped region 130. The source / drain interconnection layer 150 contacts the source / drain doped region 130 and is used to electrically connect the source / drain doped region 130 to an external circuit or other interconnection structure.

[0050] In this embodiment, the source-drain interconnect layer 150 is made of copper. Copper has a low resistivity, which helps improve signal delay in the back-end RC circuit and increase chip processing speed. It also helps reduce the resistance of the source-drain interconnect layer 150, thereby reducing power consumption. In other embodiments, the source-drain interconnect layer can also be made of conductive materials such as tungsten or cobalt.

[0051] In this embodiment, the source-drain interconnection layer 150 also penetrates the contact etch stop layer 140 and the anti-diffusion layer 125 located on the source-drain doped region 130 .

[0052] In this embodiment, the formation method further includes: after forming the source-drain interconnection layer 150 , removing a portion of the source-drain interconnection layer 150 , and forming a source-drain capping layer 155 on top of the remaining source-drain interconnection layer 150 .

[0053] In this embodiment, the top surface of the source / drain capping layer 155 is flush with the top surface of the bottom dielectric layer 135 .

[0054] Subsequently, a gate plug is formed in contact with the gate structure 110, and the source-drain cap layer 155 is located on the top surface of the source-drain interconnection layer 150. During the process of forming the gate plug, the source-drain cap layer 155 can protect the source-drain interconnection layer 150, which is beneficial to reduce damage to the source-drain interconnection layer 150 and reduce the probability of short circuit between the gate plug and the source-drain interconnection layer 150.

[0055] The source-drain capping layer 155 is made of a material having a high etching selectivity with the gate capping layer 145, the dummy sidewall 120, the bottom dielectric layer 135, and the subsequent dielectric layer, so as to ensure that the source-drain capping layer 155 protects the source-drain interconnect layer 150. In this embodiment, the material of the source-drain capping layer 155 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. Specifically, the material of the source-drain capping layer 155 is different from that of the gate capping layer 145, and the material of the source-drain capping layer 155 is different from that of the dummy sidewall 120. As an example, the material of the source-drain capping layer 155 is silicon carbide.

[0056] refer to Figure 8 , a top dielectric layer 160 is formed on the bottom dielectric layer 135 , covering the gate structure 110 and the source-drain interconnection layer 150 .

[0057] Subsequently, source and drain plugs contacting the source / drain interconnect layer 150 and a gate plug contacting the gate structure 110 are formed in the top dielectric layer 160. The top dielectric layer 160 is used to achieve electrical isolation between the source / drain plugs and the gate plug. Furthermore, in this embodiment, the top dielectric layer 160 and the dummy spacer 120 are subsequently removed to form a second gap between the bottom dielectric layer 135 and the sidewalls of the gate structure 110. A capping dielectric layer is formed on the bottom dielectric layer 135 to seal the top of the second gap. The top dielectric layer 160 also serves to occupy space for the formation of the capping dielectric layer.

[0058] In this embodiment, the top dielectric layer 160 covers the gate cap layer 145 and the source / drain cap layer 155 .

[0059] The material of top dielectric layer 160 is an insulating material. Furthermore, in this embodiment, top dielectric layer 160 will be subsequently etched, so a material that is easily etched is selected for top dielectric layer 160. The material of top dielectric layer 160 includes one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. In this embodiment, the material of top dielectric layer 160 is silicon oxide.

[0060] refer to Figure 9 , forming a top dielectric layer 160 that penetrates the top of the gate structure 110 and exposes the gate contact hole 10 at the top of the gate structure 110, and a top dielectric layer 160 that penetrates the top of the source-drain interconnection layer 150 and exposes the source-drain contact hole 20 at the top of the source-drain interconnection layer 150.

[0061] The gate contact hole 10 is used to provide space for forming a gate plug. The source-drain contact hole 20 is used to provide space for forming a source-drain plug. In this embodiment, the gate contact hole 10 and the source-drain contact hole 20 also reserve space for the subsequent formation of a sacrificial sidewall layer. The sidewalls of the gate contact hole 10 and the source-drain contact hole 20 provide support for the formation of the sacrificial sidewall layer.

[0062] The subsequently formed sacrificial sidewall layer has a thickness. Therefore, in order to reserve sufficient space for the gate contact hole 10 to form the sacrificial sidewall layer and the gate plug, the present embodiment can appropriately increase the opening size of the gate contact hole 10 according to actual process requirements. Similarly, in order to reserve sufficient space for the source / drain contact holes 20 to form the sacrificial sidewall layer and the source / drain plug, the present embodiment can appropriately increase the opening size of the source / drain contact holes 20 according to actual process requirements.

[0063] In this embodiment, the gate contact hole 10 penetrates the gate cap layer 145 and the top dielectric layer 160 at the top of the gate structure 110 in the active area 100a. Specifically, in this embodiment, to increase the size of the gate contact hole 10, the gate contact hole 10 also penetrates a portion of the offset spacer 105 located on the sidewall of the gate cap layer 145. Therefore, the gate contact hole 10 also exposes a portion of the dummy spacer 120.

[0064] In this embodiment, the source-drain contact holes 20 penetrate the source-drain cap layer 155 and the top dielectric layer 160 on the top of the source-drain interconnection layer 150 .

[0065] In this embodiment, the source-drain contact holes 20 and the gate contact hole 10 are formed in different steps.

[0066] refer to Figures 10 and 11 , a sacrificial sidewall layer 170 is formed on the sidewalls of the gate contact hole 10 and the source / drain contact hole 20 .

[0067] After forming the sacrificial sidewall layer 170 , the remaining space in the gate contact hole 10 is used to form a gate plug, and the remaining space in the source / drain contact hole 20 is used to form a source / drain plug.

[0068] The sacrificial sidewall layer 170 is used to occupy space for forming a first gap. That is, the sacrificial sidewall layer 170 is subsequently removed to form a first gap exposing the sidewalls of the gate plug and the sidewalls of the source and drain plugs, and a sealing layer is formed on the gate plug and the source and drain plugs to seal the first gap, so that the first gap and the sealing layer form a first air gap. The air gap has a lower dielectric constant than that of commonly used dielectric materials in semiconductor processes (for example, low-k dielectric materials or ultra-low-k dielectric materials), which is beneficial for reducing parasitic capacitance between the gate plug and the source and drain plugs, reducing RC delay, and thereby improving the performance of the semiconductor structure.

[0069] The sacrificial sidewall layer 170 needs to be removed later. Therefore, the sacrificial sidewall layer 170 is made of a material that is easy to remove, thereby reducing the difficulty of removing the sacrificial sidewall layer 170. Moreover, the material of the sacrificial sidewall layer 170 is selected as: a material that has etching selectivity with the gate cap layer 145, the source and drain cap layer 155, the bottom dielectric layer 135, the top dielectric layer 160, and the source and drain plugs and the gate plugs. Therefore, in the subsequent step of removing the sacrificial sidewall layer 170, the sacrificial sidewall layer 170 has an etching selectivity with these film layer structures, which is beneficial to reduce the damage to other film layers caused by removing the sacrificial sidewall layer 170, thereby improving process compatibility.

[0070] In this embodiment, the material of the sacrificial sidewall layer 170 includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, boron nitride, aluminum oxide, aluminum nitride, and silicon oxynitride. As an example, the material of the sacrificial sidewall layer 170 is amorphous silicon.

[0071] It should be noted that the thickness of the sacrificial sidewall layer 170 should not be too small or too large along the direction perpendicular to the sidewall of the gate contact hole 10 or perpendicular to the sidewall of the source-drain contact hole 20. If the thickness of the sacrificial sidewall layer 170 is too small, the width of the first gap formed by the subsequent removal of the sacrificial sidewall layer 170 is also too small, and the width of the first air gap is correspondingly too small, which may easily lead to the first air gap being used to reduce the parasitic capacitance between the source-drain plug and the gate plug. The effect is not obvious; if the thickness of the sacrificial sidewall layer 170 is too large, the width of the subsequent first gap is also too large, and the material of the subsequent sealing layer is easily filled into the first gap, which makes it difficult to form the first air gap. Moreover, the excessive width of the sacrificial sidewall layer 170 may easily increase the difficulty of the subsequent removal of the sacrificial sidewall layer 170, which may increase the process risk accordingly. For this reason, in this embodiment, the thickness of the sacrificial sidewall layer 170 is to For example, the thickness of the sacrificial sidewall layer 170 is

[0072] The steps of forming the sacrificial sidewall layer 170 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0073] like Figure 10 As shown, a sidewall material layer 165 is formed on the sidewall and bottom of the gate contact hole 10 , the sidewall and bottom of the source / drain contact hole 20 , and the top surface of the top dielectric layer 160 .

[0074] The process for forming the sidewall material layer 165 includes one or both of atomic layer deposition and chemical vapor deposition. As an example, the sidewall material layer 165 is formed using an atomic layer deposition process. The atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process. The deposited thin film can reach a thickness of a single layer of atoms, which is conducive to forming a thinner sidewall material layer 165, and correspondingly helps to make the thickness of the sacrificial sidewall layer meet the process requirements; moreover, the atomic layer deposition process also has a high step coverage capability, thereby improving the coverage capability of the sidewall material layer 165 on the sidewalls of the gate contact hole 10 and the source and drain contact hole 20, and correspondingly improving the thickness uniformity and film formation quality of the sidewall material layer 165.

[0075] In other embodiments, a chemical vapor deposition process may also be used to form the sidewall material layer. The chemical vapor deposition process may be a traditional chemical vapor deposition process or a chemical vapor deposition process that introduces a plasma treatment function. The chemical vapor deposition process that introduces a plasma treatment function includes multiple deposition cycles, and in each deposition cycle, after the deposition film is formed, the deposited film is also subjected to plasma treatment (Plasma Treatment) to improve the density and coverage of the film. Specifically, the gas used for plasma treatment includes one or more gases selected from hydrogen, helium, argon, oxygen and nitrogen. Plasma treatment can utilize energetic plasma to reduce or remove dangling bonds on the surface of the deposited film, thereby improving the density of the deposited film and preparing for the next deposition cycle.

[0076] like Figure 11 As shown, the sidewall material layer 165 at the bottom of the gate contact hole 10 and the source-drain contact hole 20 and on the top surface of the top dielectric layer 160 is removed, and the remaining sidewall material layer 165 on the sidewalls of the gate contact hole 10 and the source-drain contact hole 20 is used as a sacrificial sidewall layer 170.

[0077] Because the sidewall material layer 165 conformally covers the bottom and sidewalls of the gate contact hole 10 and the source / drain contact hole 20, as well as the top surface of the top dielectric layer 160, this embodiment can remove the sidewall material layer 165 located at the bottom of the gate contact hole 10 and the source / drain contact hole 20, and the top surface of the top dielectric layer 160, through an anisotropic etching process in a maskless environment. The anisotropic etching process has the characteristic of anisotropic etching, where the etching rate in the direction perpendicular to the surface of the substrate 100 (i.e., the longitudinal direction) is greater than the etching rate in the direction parallel to the substrate 100 (i.e., the lateral direction). As a result, the sidewall material layer 165 located at the bottom of the gate contact hole 10 and the source / drain contact hole 20, and the top surface of the top dielectric layer 160, can be etched away, while the sidewall material layer 165 located on the sidewalls of the gate contact hole 10 and the source / drain contact hole 20 can be retained to serve as a sacrificial sidewall layer. Specifically, the anisotropic etching process includes an anisotropic dry etching process, which has high process controllability, etching precision and etching efficiency.

[0078] refer to Figure 12 On the sacrificial sidewall layer 170 , a gate plug 11 filling the gate contact hole 10 and a source / drain plug 21 filling the source / drain contact hole 20 are formed.

[0079] The gate plug 11 is used to realize electrical connection between the gate structure 110 and an external circuit or other interconnection structures.

[0080] In this embodiment, the gate plug 11 is formed above the gate structure 110 of the active area 100 a . The gate plug 11 is a contact active gate plug (COAG), which helps save chip area and further reduce chip size.

[0081] The source-drain plugs 21 are in contact with the source-drain interconnection layer 150 , thereby electrically connecting the source-drain doped regions 130 to external circuits or other interconnection structures through the source-drain interconnection layer 150 .

[0082] The detailed description of the materials of the gate plug 11 and the source / drain plug 21 can be combined with reference to the aforementioned description of the source / drain interconnection layer 150 , which will not be repeated here.

[0083] In this embodiment, after the source-drain contact holes 20 and the gate contact hole 10 are formed, the source-drain plugs 21 and the gate plug 11 are formed in the same step.

[0084] It should be noted that, in this embodiment, after forming the gate plug 11 and the source / drain plug 21 , the method for forming the semiconductor structure further includes the following steps.

[0085] refer to Figure 13, the top dielectric layer 160 located between the top of the dummy sidewall 120 and the sacrificial sidewall layer 170 is etched to expose the top surface of the dummy sidewall 120 and the sidewall of the sacrificial sidewall layer 170; the dummy sidewall 120 is removed to form a second gap 40 between the contact etch stop layer 140 and the sidewall of the gate structure 110.

[0086] The second gap 40 is used to provide space for forming a subsequent cover dielectric layer. Specifically, in this embodiment, the second gap 40 is formed between the anti-diffusion layer 125 and the offset spacer 105 , and between the anti-diffusion layer 125 and the sacrificial sidewall layer 170 .

[0087] In this embodiment, an isotropic etching process is adopted to remove the top dielectric layer 160 and the pseudo side wall 120. By adopting the isotropic etching process, the top dielectric layer 160 and the pseudo side wall 120 can be removed cleanly, and the etching rate is relatively fast. In this embodiment, the isotropic etching process is a remote plasma etching process. The remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process. Among them, the principle of the remote plasma etching process is to form plasma outside the etching chamber (for example, plasma is generated by a remote plasma generator), and then introduce it into the etching chamber and use the chemical reaction between the plasma and the etched layer to etch, thereby achieving an isotropic etching effect, and because there is no ion bombardment, other film layers will not be damaged.

[0088] In other embodiments, the isotropic etching process may also be a wet etching process.

[0089] In this embodiment, the top dielectric layer 160 and the dummy sidewall spacers 120 are made of the same material. Therefore, the top dielectric layer 160 and the dummy sidewall spacers 120 can be removed in the same etching step, thereby simplifying the process steps.

[0090] refer to Figure 14 A covering dielectric layer 180 is formed on the bottom dielectric layer 135 to cover the sidewalls of the sacrificial sidewall layer 170 . The covering dielectric layer 180 seals the second gap 40 . The dielectric constant of the covering dielectric layer 180 is lower than that of the dummy sidewall 120 .

[0091] By removing the dummy sidewall spacer 120 and forming a capping dielectric layer 180 with a lower dielectric constant, the capping dielectric layer 180 seals the second gap 40, thereby reducing the effective capacitance between the gate structure 110 and the source / drain interconnect layer 150, thereby improving the performance of the semiconductor structure. Furthermore, in this embodiment, the capping dielectric layer 180 also serves to electrically isolate the source / drain plug 21 from the gate plug 11. Furthermore, upon subsequent removal of the sacrificial sidewall layer 170, a first gap is defined between the capping dielectric layer 180 and the sidewalls of the gate plug 11 or the sidewalls of the source / drain plug 21. The capping dielectric layer 180 also provides support for the subsequent formation of a sealing layer that seals the first gap.

[0092] In this embodiment, the cover dielectric layer 180 is used as an example to fill the second gap 40, thereby sealing the second gap 40. In other embodiments, when the aspect ratio (AR) of the second gap is large, the cover dielectric layer can also seal the top of the second gap, so that the second gap and the cover dielectric layer form a second air gap. The dielectric constant of air is relatively low, which helps to further reduce the effective capacitance between the gate structure and the source-drain interconnect layer.

[0093] In this embodiment, the material covering the dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150, and the parasitic capacitance between the source-drain plug 21 and the gate plug 11, thereby reducing the RC delay of the interconnection structure in the integrated circuit.

[0094] The process for forming the cover dielectric layer 180 includes one or more of a flow-type chemical vapor deposition process, an atomic layer deposition process, a spin coating process, and a chemical vapor deposition process. In this embodiment, the process for forming the cover dielectric layer 180 includes a spin coating process. The spin coating process has a relatively low process temperature, thereby avoiding channel degradation caused by high temperatures, which is beneficial for improving the performance of the semiconductor structure. Furthermore, the spin coating process has a high gap-filling capability, which is beneficial for improving the filling quality of the cover dielectric layer 180 in the second gap 40 and between the source / drain plug 21 and the gate plug 11.

[0095] In this embodiment, the step of forming the covering dielectric layer 180 includes: forming a dielectric material layer (not shown) on the bottom dielectric layer 135 to cover the sidewalls of the sacrificial sidewall layer 170, the dielectric material layer also covering the top of the gate plug 11 and the source and drain plugs 21, and the dielectric material layer sealing the second gap 40; and removing the dielectric material layer above the top of the gate plug 11 and the source and drain plugs 21.

[0096] In this embodiment, a spin coating process is used to form the dielectric material layer.

[0097] refer to Figure 15The sacrificial sidewall layer 170 is removed to form a first gap 30 that exposes the sidewalls of the gate plug 11 and the sidewalls of the source / drain plug 21. The first gap 30 is used to form a first air gap with a sealing layer formed subsequently.

[0098] In this embodiment, first gaps 30 are formed between the cover dielectric layer 180 and the sidewalls of the gate plug 11 , and between the cover dielectric layer 180 and the sidewalls of the source / drain plug 21 .

[0099] In this embodiment, an isotropic etching process is used to remove the sacrificial sidewall layer 170. The isotropic etching process is used so that the sacrificial sidewall layer 170 can be completely removed and the etching rate is relatively fast.

[0100] In this embodiment, the isotropic etching process is a remote plasma etching process. The remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process. The principle of the remote plasma etching process is to form plasma outside the etching chamber (for example, by generating plasma through a remote plasma generator), and then introduce it into the etching chamber and use the chemical reaction between the plasma and the etched layer to etch, thereby achieving an isotropic etching effect, and because there is no ion bombardment, other film layers will not be damaged.

[0101] In other embodiments, the isotropic etching process may also be a wet etching process.

[0102] refer to Figure 16 A sealing layer 190 is formed to seal the first gap 30 , so that at least one of the first gap 30 located on the sidewall of the source / drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11 and the sealing layer 190 form a first air gap 50 .

[0103] In this embodiment, at least one of the first gap 30 located on the sidewall of the source / drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11 is formed with the sealing layer 190 to form a first air gap 50. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), thereby reducing parasitic capacitance between the gate plug 11 and the source / drain plug 21 and reducing RC delay, thereby improving the performance of the semiconductor structure.

[0104] In this embodiment, the gate plug 11 is an active gate contact plug (COAG). Compared with a conventional gate plug located in an isolation region, the distance between the gate plug 11 and the source / drain plug 12 is closer in this embodiment. By forming a first gap 30 on the sidewalls of the gate plug 11 and the sidewalls of the source / drain plug 21 and sealing the first gap 30, a first air gap 50 is formed on the sidewalls of at least one of the source / drain plug 21 and the gate plug 11. This helps significantly reduce the parasitic capacitance between the gate plug 11 and the source / drain plug 12, alleviates RC delay problems, and thus significantly improves the performance of the semiconductor structure.

[0105] In this embodiment, the sealing layer 190 covers the source / drain plugs 21, the gate plug 11, and the top of the dielectric layer 180. Subsequent processes also include forming metal interconnects on top of the source / drain plugs 21 and the gate plug 11 to electrically connect the source / drain plugs 21 and the external circuit, and the gate plug 11 and the external circuit. The metal interconnects are formed in an intermetallic dielectric (IMD) layer. By covering the top of the source / drain plugs 180 with the sealing layer 190, the sealing layer 190 above the top of the source / drain plugs 180 serves as an intermetallic dielectric layer, thereby simplifying the process steps of the back-end-of-line (BEOL) process and making the sealing layer 190 compatible with the BEOL process.

[0106] The sealing layer 190 is made of a dielectric material. Detailed descriptions of the material of the sealing layer 190 can be found in the aforementioned description of the covering dielectric layer 180 and will not be repeated here.

[0107] As an example, the sealing layer 190 contacts the top corner of the first gap 30 located on the side wall of the source / drain plug 21, thereby sealing the top of the first gap 30, and further forming the first gap 30 located on the side wall of the source / drain plug 21 and the sealing layer 190 to form a first air gap 50.

[0108] As an example, the sealing layer 190 fills the first gap 30 located on the sidewall of the gate plug 11 .

[0109] Specifically, in this embodiment, the cross-section of the source / drain plug 21 is an inverted trapezoid with a larger top and a smaller bottom. The sidewalls of the first gap 30 located on the sidewalls of the source / drain plug 21 also have a certain inclination angle. The verticality of the sidewalls of the gate plug 11 is greater than that of the sidewalls of the source / drain plug 21. Therefore, it is more difficult for the sealing layer 190 to fill the first gap 30 located on the sidewalls of the source / drain plug 21 than to fill the first gap 30 located on the sidewalls of the gate plug 11. Accordingly, the sealing layer 190 easily encloses the first air gap 50 with the first gap 30 on the sidewalls of the source / drain plug 21, and the sealing layer 190 fills the first gap 30 located on the sidewalls of the gate plug 11.

[0110] In other embodiments, depending on actual process conditions such as the aspect ratio of the first gap located at the gate plug, the cross-sectional morphology of the gate plug, and the slope of the sidewalls of the first gap, the sealing layer may also contact the top corner of the first gap located at the sidewalls of the gate plug, thereby sealing the top of the first gap and further forming a first air gap between the first gap located at the sidewalls of the gate plug and the sealing layer. In still other embodiments, only the first gap located at the sidewalls of the gate plug and the sealing layer may form the first air gap.

[0111] In this embodiment, a deposition process with a relatively weak filling capability is used to form the sealing layer 190. This makes it difficult for the sealing layer 190 to fill the first gap 30, and thus makes it easy for the sealing layer 190 to contact the first gap 30 at the top corner to form the first air gap 50. In this embodiment, the process for forming the sealing layer 190 includes one or both of a chemical vapor deposition process and a plasma-enhanced chemical vapor deposition process.

[0112] It should be noted that this embodiment uses the COAG process as an example for illustration. In other embodiments, when the gate plug is located on top of the gate structure in the isolation region, the method for forming the semiconductor structure provided in this embodiment can still achieve the effect of reducing the parasitic capacitance between the source / drain plug and the gate structure.

[0113] Accordingly, the present invention also provides a semiconductor structure. Figure 16 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0114] The semiconductor structure includes: a substrate 100; a gate structure 110 located on the substrate 100; source-drain doped regions 130 located in the substrate 100 on both sides of the gate structure 110; a source-drain interconnection layer 150 located on top of the source-drain doped regions 130 and in contact with the source-drain doped regions 130; a gate plug 11 located on top of the gate structure 110 and in contact with the gate structure 110; a source-drain plug 21 located on top of the source-drain interconnection layer 150 and in contact with the source-drain plug 21; a dielectric layer 180 covering the sidewalls of the gate plug 11 and the source-drain plug 21 and filling the space between the gate plug 11 and the source-drain plug 21; a first gap 30 (such as Figure 15 As shown in FIG, 4 , the first air gap 50 is formed between the sidewall of the gate plug 11 and the dielectric layer 180, and between the sidewall of the source / drain plug 21 and the dielectric layer 180. The sealing layer 190 is located on the dielectric layer 180 and seals the first gap 30. At least one of the first gap 30 located on the sidewall of the source / drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11 is surrounded by the sealing layer 190 to form a first air gap 50.

[0115] By providing a first gap 30 that exposes the sidewalls of the gate plug 11 and the sidewalls of the source / drain plug 12, and providing a sealing layer 190, at least one of the first gap 30 located on the sidewall of the source / drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11, together with the sealing layer 190, forms a first air gap 50. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), thereby reducing parasitic capacitance between the gate plug 11 and the source / drain plug 21 and reducing RC delay, thereby improving the performance of the semiconductor structure.

[0116] The substrate 100 is used to provide a platform for the process. In this embodiment, the substrate 100 is a planar substrate. In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 includes an active area 100a.

[0117] The gate structure 110 serves as a device gate and is used to control the opening or closing of the conductive channel when the device is in operation.

[0118] In this embodiment, the gate structure 110 is a metal gate structure, and the gate structure 110 is formed by forming a high-k gate dielectric layer and then forming a gate electrode layer.

[0119] The source-drain doped region 130 is used to provide a carrier source when the device is operating.

[0120] In this embodiment, the semiconductor structure further includes: a bottom dielectric layer 135 (such as Figure 6 , located on the substrate 100 where the gate structure 110 is exposed. The bottom dielectric layer 135 is used to isolate adjacent devices. In this embodiment, the material of the bottom dielectric layer 135 is silicon oxide.

[0121] The source-drain interconnect layer 150 contacts the source-drain doped region 130 and is used to electrically connect the source-drain doped region 130 to external circuits or other interconnect structures. In this embodiment, the source-drain interconnect layer 150 is made of copper. In other embodiments, the source-drain interconnect layer can also be made of a conductive material such as tungsten or cobalt.

[0122] In this embodiment, the source-drain interconnection layer 150 penetrates the bottom dielectric layer 135 located on the source-drain doped region 130 .

[0123] In this embodiment, the semiconductor structure further includes: a gate cap layer 145 (eg Figure 8 As shown), it is located between the top of the gate structure 110 and the dielectric layer 180; the source and drain cap layer 155 is located between the top of the source and drain interconnection layer 150 and the dielectric layer 180.

[0124] In this embodiment, the top surface of the source / drain capping layer 155 is flush with the top surface of the bottom dielectric layer 135 .

[0125] The source-drain capping layer 155 is located on the top surface of the source-drain interconnection layer 150 and is used to protect the source-drain interconnection layer 150 during the formation of the gate plug 11, thereby reducing damage to the source-drain interconnection layer 150 and reducing the probability of short circuit between the gate plug 11 and the source-drain interconnection layer 150.

[0126] The gate cap layer 145 is used to protect the top of the gate structure 110 during the process of forming the source-drain interconnection layer 150 and the source-drain plug 21, thereby reducing damage to the gate structure 110 and reducing the probability of short circuit problems between the gate structure 110 and the source-drain interconnection layer 150 or the source-drain plug 11.

[0127] For detailed description of the materials of the gate capping layer 145 and the source / drain capping layer 155 , reference may be made to the corresponding description in the aforementioned embodiments, which will not be repeated here.

[0128] In this embodiment, the semiconductor structure further includes: a contact etch stop layer 140, which is located on the substrate 100 between the sidewalls of the source-drain interconnect layer 150 and the gate structure 110, and is arranged opposite to the sidewalls of the gate structure 110, and a second gap 40 (such as Figure 13 shown).

[0129] A contact etch stop layer 140 is also located on the top surface of the source / drain doped region 130. The contact etch stop layer 140 is used to temporarily define the etching stop position during the formation of the source / drain interconnect layer 150, thereby improving etching consistency and preventing damage to the source / drain doped region 130. In this embodiment, the material of the contact etch stop layer 140 is a low-k dielectric material or an ultra-low-k dielectric material, so that the contact etch stop layer 140 can further reduce the effective capacitance between the gate structure 110 and the source / drain interconnect layer 150. In other embodiments, the material of the contact etch stop layer can also be silicon nitride.

[0130] In this embodiment, the dielectric layer 180 is a cover dielectric layer 180. The cover dielectric layer 180 seals the second gap 40. The second gap 40 is used to provide a space for the cover dielectric layer 180 to form.

[0131] The capping dielectric layer 180 seals the second gap 40 , thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150 , thereby improving the performance of the semiconductor structure.

[0132] In this embodiment, the material of the cover dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, the cover dielectric layer 180 fills the second gap 40. In other embodiments, when the aspect ratio (AR) of the second gap is large, the cover dielectric layer seals the top of the second gap, and the second gap and the cover dielectric layer form a second air gap. Air has a low dielectric constant, which helps further reduce the effective capacitance between the gate structure and the source-drain interconnect layer.

[0133] In this embodiment, in a direction parallel to the surface of the substrate 100 and perpendicular to the sidewall of the gate structure 110 , the width of the second gap 40 is 2 nm to 12 nm.

[0134] In this embodiment, the semiconductor structure further includes an anti-diffusion layer 125 located on the sidewalls of the contact etch stop layer 140 exposed by the second gap 40. The second gap 40 is formed by removing the dummy sidewall spacer. The anti-diffusion layer 125 is used to prevent easily diffusible ions in the dummy sidewall spacer from diffusing into the contact etch stop layer 140, thereby preventing the contact etch stop layer 140 from being adversely affected by ion diffusion.

[0135] Therefore, the density of the diffusion prevention layer 125 is relatively high, and the material of the diffusion prevention layer 125 is an insulating material. Specifically, the material of the diffusion prevention layer 125 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the diffusion prevention layer 125 is silicon nitride.

[0136] It should be noted that the anti-diffusion layer 125 is also located between the source-drain interconnection layer 150 and the gate structure 110, and the anti-diffusion layer 125 will also affect the effective capacitance between the source-drain interconnection layer 150 and the gate structure 110. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 125 on ions, in order to prevent the effective capacitance between the source-drain interconnection layer 150 and the gate structure 110 from being too large and to prevent it from occupying too much chip area, the thickness of the anti-diffusion layer 125 is less than or equal to In this embodiment, the thickness of the anti-diffusion layer 125 is less than or equal to When the thickness of the anti-diffusion layer 125 is too small, the anti-diffusion layer 125 may have a poor effect in preventing ion diffusion. to

[0137] In this embodiment, the semiconductor structure further includes an offset spacer 105 located on the sidewall of the gate structure 110 exposed by the second gap 40. The offset spacer 105 is used to improve the short channel effect and the hot carrier effect caused by the short channel effect.

[0138] In this embodiment, the offset spacer 105 is further located on the substrate 100 exposed by the second gap 40. The offset spacer 105 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride-carbon nitride, silicon oxynitride-boron nitride, or silicon oxynitride-carbon-boron nitride.

[0139] The gate plug 11 is used to realize electrical connection between the gate structure 110 and an external circuit or other interconnection structures.

[0140] In this embodiment, the gate plug 11 is located above the gate structure 110 of the active area 100a. The gate plug 11 is an active gate contact hole plug. Compared with the solution in which the gate plug contacts the gate structure located in the isolation area, this embodiment omits the portion of the gate structure 110 located in the isolation area, which is beneficial to saving chip area, thereby achieving further reduction in chip size.

[0141] The source-drain plugs 21 are in contact with the source-drain interconnection layer 150 , thereby electrically connecting the source-drain doped regions 130 to external circuits or other interconnection structures through the source-drain interconnection layer 150 .

[0142] The detailed description of the gate plug 11 and the source-drain plug 21 can be combined with reference to the aforementioned description of the source-drain interconnection layer 150 , which will not be repeated here.

[0143] In this embodiment, the cover dielectric layer 180 seals the second gap 40, thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnect layer 150, thereby improving the performance of the semiconductor structure. Furthermore, in this embodiment, the cover dielectric layer 180 is used to achieve electrical isolation between the source-drain plug 21 and the gate plug 11. Furthermore, the cover dielectric layer 180 provides support for the sealing layer 190 that seals the first gap 30.

[0144] In this embodiment, the material covering the dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material, thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150, and also helping to reduce the parasitic capacitance between the source-drain plug 21 and the gate plug 11, thereby reducing RC delay.

[0145] The first gap 30 is used to form a first air gap 50 , thereby facilitating reduction of parasitic capacitance between the source / drain plug 21 and the gate plug 11 .

[0146] The width of the first gap 30 should not be too small or too large along the direction perpendicular to the side wall of the gate plug 11 or perpendicular to the side wall of the source-drain plug 21. If the width of the first gap 30 is too small, the width of the first air gap 50 is also too small, which may lead to the first air gap 50 being less effective in reducing the parasitic capacitance between the source-drain plug 21 and the gate plug 11. If the width of the first gap 30 is too large, the material of the sealing layer 190 may easily fill into the first gap 30, making it difficult to form the first air gap 50. For this reason, in this embodiment, the width of the first gap 30 along the direction perpendicular to the side wall of the gate plug 11 or perpendicular to the side wall of the source-drain plug 21 is to For example: the width of the first gap 30 is

[0147] The sealing layer 190 is used to seal the first gap 30, thereby forming a first air gap 50. The air gap has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), thereby reducing the parasitic capacitance between the gate plug 11 and the source / drain plug 21, reducing RC delay, and thereby improving the performance of the semiconductor structure.

[0148] In this embodiment, the gate plug 11 is an active gate contact plug (COAG). Compared with a conventional gate plug located in an isolation region, the distance between the gate plug 11 and the source / drain plug 12 is closer. By providing the first air gap 50, the parasitic capacitance between the gate plug 11 and the source / drain plug 12 is significantly reduced, the RC delay problem is reduced, and the performance of the semiconductor structure is significantly improved.

[0149] In this embodiment, the sealing layer 190 covers the source / drain plugs 21, the gate plug 11, and the top of the dielectric layer 180. Subsequent processes also include forming metal interconnects on top of the source / drain plugs 21 and the gate plug 11 to electrically connect the source / drain plugs 21 or the gate plug 11 to external circuits. The metal interconnects are formed in an intermetallic dielectric (IMD) layer. By covering the top of the source / drain plugs 180 with the sealing layer 190, the portion of the sealing layer 190 that is higher than the top of the source / drain plugs 180 serves as an intermetallic dielectric layer, thereby simplifying the process steps of the back-end-of-line (BEOL) process and making the sealing layer 190 compatible with the BEOL process.

[0150] The sealing layer 190 is made of a dielectric material. Detailed descriptions of the material of the sealing layer 190 can be found in the aforementioned description of the covering dielectric layer 180 and will not be repeated here.

[0151] As an example, the sealing layer 190 contacts the top corner of the first gap 30 located on the side wall of the source / drain plug 21, thereby sealing the top of the first gap 30, and further forming the first gap 30 located on the side wall of the source / drain plug 21 and the sealing layer 190 to form a first air gap 50.

[0152] As an example, the sealing layer 190 fills the first gap 30 located on the sidewall of the gate plug 11 .

[0153] Specifically, in this embodiment, the cross-section of the source / drain plug 21 is an inverted trapezoid with a larger top and a smaller bottom. The sidewalls of the first gap 30 located on the sidewalls of the source / drain plug 21 also have a certain inclination angle. The verticality of the sidewalls of the gate plug 11 is greater than that of the sidewalls of the source / drain plug 21. Therefore, it is more difficult for the sealing layer 190 to fill the first gap 30 located on the sidewalls of the source / drain plug 21 than the first gap 30 located on the sidewalls of the gate plug 11. Accordingly, the sealing layer 190 can easily enclose the first air gap 50 with the first gap 30 on the sidewalls of the source / drain plug 21, and the sealing layer 190 fills the first gap 30 located on the sidewalls of the gate plug 11.

[0154] In other embodiments, depending on actual process conditions such as the aspect ratio of the first gap located on the sidewall of the gate plug, the cross-sectional morphology of the gate plug, and the slope of the sidewall of the first gap, the sealing layer can also contact the top corner of the first gap located on the sidewall of the gate plug, thereby sealing the top of the first gap and further forming a first air gap between the first gap located on the sidewall of the gate plug and the sealing layer. In still other embodiments, only the first gap located on the sidewall of the gate plug and the sealing layer can form the first air gap.

[0155] It should be noted that in this embodiment, the gate plug 11 is described as a COAG. In other embodiments, when the gate plug is located on top of the gate structure in the isolation region, the semiconductor structure provided by this embodiment can still achieve the effect of reducing the parasitic capacitance between the source / drain plug and the gate structure.

[0156] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0157] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a gate structure, located on the substrate; Source and drain doped regions are located in the substrate on both sides of the gate structure; a source-drain interconnection layer, located on top of the source-drain doped region and in contact with the source-drain doped region; a gate plug located on top of the gate structure and in contact with the gate structure; a source-drain plug, located on top of the source-drain interconnection layer and in contact with the source-drain interconnection layer; a dielectric layer covering the sidewalls of the gate plug and the source / drain plug and filling between the gate plug and the source / drain plug; a first gap located between the sidewall of the source / drain plug and the dielectric layer, wherein the first gap exposes the sidewall of the source / drain plug; A sealing layer is located on the dielectric layer and seals the first gap from the top of the first gap. The first gap located on the sidewall of the source / drain plug and the sealing layer form a first air gap, and the first air gap is located above the source / drain interconnection layer.

2. The semiconductor structure according to claim 1, wherein The substrate includes an active area; the semiconductor structure also includes: a gate cap layer located between the top of the gate structure and the dielectric layer; a source / drain cap layer located between the top of the source / drain interconnection layer and the dielectric layer; and the gate plug is located above the gate structure in the active area.

3. The semiconductor structure according to claim 1, wherein: Along the direction perpendicular to the sidewall of the gate plug or the source / drain plug, the width of the first gap is to 4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a contact etch stop layer located on the substrate between the sidewall of the source-drain interconnect layer and the gate structure and arranged opposite to the sidewall of the gate structure, with a second gap between the contact etch stop layer and the sidewall of the gate structure; The dielectric layer fills the second gap, or the dielectric layer seals the top of the second gap, and the second gap and the dielectric layer form a second air gap.

5. The semiconductor structure according to claim 1 or 4, wherein: The material of the dielectric layer includes low-k dielectric material or ultra-low-k dielectric material.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, a gate structure located on the substrate, source and drain doped regions in the substrate located on both sides of the gate structure, and a bottom dielectric layer located on the substrate at the side of the gate structure and covering the source and drain doped regions; forming a bottom dielectric layer penetrating the top of the source / drain doped region and forming a source / drain interconnection layer in contact with the source / drain doped region; forming a top dielectric layer on the bottom dielectric layer, covering the gate structure and the source-drain interconnection layer; forming a gate contact hole penetrating the top dielectric layer on the top of the gate structure and exposing the top of the gate structure, and a source-drain contact hole penetrating the top dielectric layer on the top of the source-drain interconnection layer and exposing the top of the source-drain interconnection layer; forming a sacrificial sidewall layer on the sidewalls of the gate contact hole and the source / drain contact hole; forming a gate plug filling the gate contact hole and a source / drain plug filling the source / drain contact hole on the sacrificial sidewall layer; removing the sacrificial sidewall layer to form a first gap exposing the sidewall of the source / drain plug; A sealing layer is formed to seal the first gap from the top of the first gap, so that the first gap located on the sidewall of the source / drain plug and the sealing layer form a first air gap, and the first air gap is formed above the source / drain interconnection layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: In the step of providing a substrate, the substrate includes an active area; The method for forming the semiconductor structure further includes: after providing the substrate and before forming the top dielectric layer, removing a portion of the gate structure, and forming a gate cap layer on top of the remaining gate structure; After forming the source-drain interconnection layer and before forming the top dielectric layer, removing a portion of the source-drain interconnection layer, and forming a source-drain cap layer on top of the remaining source-drain interconnection layer; The top dielectric layer covers the gate cap layer and the source / drain cap layer; the gate contact hole penetrates the gate cap layer and the top dielectric layer at the top of the gate structure in the active area; the source / drain contact hole penetrates the source / drain cap layer and the top dielectric layer at the top of the source / drain interconnection layer.

8. The method for forming a semiconductor structure according to claim 6, wherein: In the step of providing a substrate, a dummy sidewall contacting the sidewall of the gate structure and a contact etch stop layer located on the sidewall of the dummy sidewall are formed between the sidewall of the gate structure and the bottom dielectric layer, and the contact etch stop layer is also located between the source and drain doped regions and the bottom dielectric layer; The method for forming a semiconductor structure further includes: after forming the gate plug and the source / drain plug and before removing the sacrificial sidewall layer, etching the top dielectric layer located between the top of the dummy sidewall and the sacrificial sidewall layer to expose the top surface of the dummy sidewall and the sidewall of the sacrificial sidewall layer; removing the dummy sidewall to form a second gap between the contact etch stop layer and the sidewall of the gate structure; forming a capping dielectric layer on the bottom dielectric layer to cover the sidewalls of the sacrificial sidewall layer, the capping dielectric layer filling the second gap, the dielectric constant of the capping dielectric layer material being lower than the dielectric constant of the dummy sidewall material, or the capping dielectric layer sealing the top of the second gap so that the second gap and the capping dielectric layer enclose a second air gap; In the step of removing the sacrificial sidewall layer, the first gap is formed between the cover dielectric layer and the sidewall of the gate plug, and between the cover dielectric layer and the sidewall of the source / drain plug.

9. The method for forming a semiconductor structure according to claim 6, wherein: The step of forming the sacrificial sidewall layer includes: forming a sidewall material layer on the sidewall and bottom of the gate contact hole, the sidewall and bottom of the source and drain contact holes, and the top surface of the top dielectric layer; The sidewall material layer at the bottom of the gate contact hole and the source / drain contact hole and on the top surface of the top dielectric layer is removed, and the remaining sidewall material layer on the sidewalls of the gate contact hole and the source / drain contact hole is used as the sacrificial sidewall layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the sidewall material layer includes one or both of atomic layer deposition and chemical vapor deposition.

11. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the sidewall material layer located at the bottom of the gate contact hole and the source / drain contact hole and the top surface of the top dielectric layer includes an anisotropic dry etching process.

12. The method for forming a semiconductor structure according to claim 6, wherein: The material of the sacrificial sidewall layer includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, boron nitride, aluminum oxide, aluminum nitride and silicon oxynitride.

13. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming the sacrificial sidewall layer, the thickness of the sacrificial sidewall layer is perpendicular to the sidewall of the gate contact hole or perpendicular to the sidewall of the source and drain contact hole. to 14. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the sacrificial sidewall layer includes a remote plasma etching process or a wet etching process.

15. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the sealing layer includes one or both of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

16. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the top dielectric layer and the dummy sidewall spacer includes a remote plasma etching process or a wet etching process.

17. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the cover dielectric layer includes one or more of a flow chemical vapor deposition process, an atomic layer deposition process, a spin coating process and a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 8, wherein: The material of the dummy sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride.

19. The method for forming a semiconductor structure according to claim 8, wherein: The material of the cover dielectric layer includes a low-k dielectric material or an ultra-low-k dielectric material.

20. The method for forming a semiconductor structure according to claim 6 or 8, wherein: The material of the top dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride.

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