Fingerprint sensor circuit

Abstract

This invention discloses a fingerprint sensor circuit, including a substrate and at least one isolation well unit and an integrating circuit disposed on the substrate. The isolation well unit contains a sensing unit and a coupling capacitor. The sensing unit includes a sensing capacitor, a first switch, and a second switch. The first plate of the sensing capacitor represents the finger being sensed. The second plate of the sensing capacitor is connected to the first terminal of the first switch, the third terminal of the second switch, and the third plate of the coupling capacitor. The fourth terminal of the second switch is connected to the integrating circuit. The isolation well unit is configured to be driven according to a preset isolation level, which is configured to have a pulse waveform. The second terminal of the first switch, the fourth plate of the coupling capacitor, and the integrating circuit are connected to the isolation well unit and configured to drive synchronously with the isolation level. The fingerprint sensor circuit provided by this invention has high sensitivity, high linearity, and strong anti-interference capability.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, and in particular to a fingerprint sensor circuit. Background Technology

[0002] The principle of a fingerprint sensor is to obtain a fingerprint image by measuring the capacitance between the finger and the sensor detection array. In order to improve the structural strength of the sensor, an insulating layer is usually placed between the finger and the sensor detection array. This setting will affect the detection accuracy of the sensor to a certain extent. Combined with the charge accumulation and release of other components inside the circuit, it will cause the linearity between the circuit output and the measured capacitance to decrease, slow down the fingerprint recognition process, and cause problems such as blurred fingerprint images or even recognition failure. Summary of the Invention

[0003] The purpose of this invention is to provide a fingerprint sensor circuit that solves the technical problems in the prior art, such as poor linearity between the circuit output and the measured capacitor, poor fingerprint recognition sensitivity, and the inability to eliminate interference from other components inside the circuit.

[0004] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a fingerprint sensor circuit, including a substrate and at least one isolation well unit and an integrating circuit disposed on the substrate; the isolation well unit is provided with a sensing unit and a coupling capacitor, the sensing unit includes a sensing capacitor, a first switch and a second switch, the first plate of the sensing capacitor represents the sensed finger, the second plate of the sensing capacitor is respectively connected to the first terminal of the first switch, the third terminal of the second switch and the third plate of the coupling capacitor, and the fourth terminal of the second switch is connected to the integrating circuit; the isolation well unit is configured to be driven according to a preset isolation level, the isolation level is configured to have a pulse waveform, the second terminal of the first switch, the fourth plate of the coupling capacitor and the integrating circuit are connected to the isolation well unit and configured to drive synchronously with the isolation level.

[0005] As a further improvement of one embodiment of the present invention, the integrating circuit includes an operational amplifier, an integrating capacitor, and a reference voltage source. The non-inverting input terminal of the operational amplifier is connected to the fourth terminal of the second switch. The two ends of the integrating capacitor are respectively connected to the non-inverting input terminal and the output terminal of the operational amplifier. The inverting input terminal of the operational amplifier is connected to the reference voltage source. The operational amplifier is connected to the isolation well unit and configured to drive synchronously with the isolation level.

[0006] As a further improvement of one embodiment of the present invention, the isolation well unit includes a signal terminal for controlling the isolation level. The signal terminal is connected to the second terminal, the fourth plate, and the operational amplifier, and provides the lowest potential of the sensing capacitor, the coupling capacitor, and the integrating circuit to switch between a preset first potential and a second potential; wherein the first potential is ground level, and the second potential is high level.

[0007] As a further improvement of one embodiment of the present invention, the working timing of the isolation well unit is as follows: First state: the second switch is open, driving the signal terminal to the second potential, and the first switch is closed; Second state: the first switch is open, the signal terminal is switched to the first potential, and the second switch is closed.

[0008] As a further improvement of one embodiment of the present invention, in the first state, the sensing capacitor accumulates charge to generate a first charge, and the coupling capacitor has no charge accumulation; in the second state, the sensing capacitor accumulates charge to generate a second charge, and the coupling capacitor accumulates charge to generate a third charge, and the change in the output voltage of the integrating circuit is:

[0009]

[0010] As a further improvement of one embodiment of the present invention, the first charge is the product of the second potential and the sensing capacitor, the second charge is the product of the reference voltage and the sensing capacitor, and the third charge is the product of the reference voltage and the coupling capacitor.

[0011] As a further improvement of one embodiment of the present invention, the isolation well units are arranged in multiple rows, and the circuit further includes a first row bus, a second row bus, a first pulse power supply and a second pulse power supply corresponding to each row of isolation well units. One end of the first row bus is connected to the first pulse power supply and the other end is connected to the first switch of each isolation well unit. One end of the second row bus is connected to the second pulse power supply and the other end is connected to the second switch of each isolation well unit.

[0012] As a further improvement of one embodiment of the present invention, multiple isolation well units are arranged in columns, and the circuit further includes a column bus. The column bus and the integrating circuit are respectively arranged for each column of isolation well units. One end of the column bus is connected to the integrating circuit, and the other end is connected to the second switch of each isolation well unit.

[0013] As a further improvement of one embodiment of the present invention, the integrating circuit includes an operational amplifier, a first reference voltage source, a second reference voltage source, a first switching contact, and a second switching contact. The first reference voltage source and the second reference voltage source are respectively connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier. The fifth terminal of the first switching contact and the seventh terminal of the second switching contact are respectively connected to the column bus. The sixth terminal of the first switching contact is connected to the non-inverting input terminal of the operational amplifier, and the eighth terminal of the second switching contact is connected to the inverting input terminal of the operational amplifier. A first linkage switch that opens and closes synchronously with the first switching contact is also provided between the first reference voltage source and the operational amplifier. A second linkage switch that opens and closes synchronously with the second switching contact is also provided between the second reference voltage source and the operational amplifier. The first switching contact, the first linkage switch, the second switching contact, and the second linkage switch are configured to open and close an equal number of times in one cycle.

[0014] As a further improvement of one embodiment of the present invention, the integrating circuit further includes a first control line and a second control line connected to the operational amplifier, wherein the first control line is connected to the first switching contact and the first linkage switch, and the second control line is connected to the second switching contact and the second linkage switch.

[0015] Compared with the prior art, the fingerprint sensor circuit provided by the present invention, by setting up an isolation well unit, configuring the isolation well unit with an isolation level with a pulse waveform, and connecting components such as coupling capacitors to the isolation level, can maintain synchronous driving of components within the isolation well unit, reduce the influence of coupling capacitors on the output of the sensor circuit, improve the linearity between the circuit output and the measured capacitor, and enhance the sensitivity of the fingerprint sensor. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the external structure of a fingerprint sensor circuit according to one embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a column of isolation well units and an integrating circuit in a fingerprint sensor circuit according to an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the structure of a single isolation well unit and an integrating circuit in a fingerprint sensor circuit according to an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the working timing of the isolation well unit in the fingerprint sensor circuit according to one embodiment of the present invention;

[0020] Figure 5This is a schematic diagram of the integrating circuit in the fingerprint sensor circuit according to another embodiment of the present invention. Detailed Implementation

[0021] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0022] It should be noted that the term "comprising" or any other variations thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the description of specific embodiments of the invention, the terms "above," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, generally with reference to the device or apparatus in its normal operating state, and do not indicate that the indicated location or element must have a specific orientation. Furthermore, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] The fingerprint sensor circuit provided by this invention operates on the principle of utilizing the differences in the depth of the peaks and valleys in the ridges of a fingerprint to bring grooves of different depths into contact with the sensing element on the fingerprint sensor circuit. The sensing element generates different electrical signals accordingly, which are then transmitted to an analog-to-digital converter and a data analysis device for analysis to obtain fingerprint information.

[0024] like Figure 1 The external structure of a fingerprint sensor circuit according to an embodiment of the present invention is shown. Specifically, it includes a substrate 100 and components disposed on the substrate 100 for sensing fingerprints. In this embodiment, the components are arranged in an array to ultimately form a sensing array 200. During use, the side of the finger with the fingerprint covers the surface of the sensing array 200, ultimately generating and outputting different electrical signals.

[0025] Specifically, the units in the sensing array 200 used to sense fingerprints and emit electrical signals are configured in m rows and n columns, thus ultimately generating and outputting m×n sets of electrical signals. The specific values ​​of m and n can be configured according to the needs of those skilled in the art, mainly based on the surface area of ​​the fingerprint sensor module, sufficient to collect most of the information in most fingerprints. In addition to the sensing array 200, the fingerprint sensor circuit provided by the present invention further includes a readout circuit 300 and a logic control circuit 500 electrically connected to the sensing array 200, respectively. The logic control circuit 500 is used to control the scanning of fingerprints by the sensing array 200 according to a preset working sequence, while the readout circuit 300 is located at the rear end of the sensing array 200, receives and processes multiple sets of electrical signals from the sensing array 200, and finally outputs them to other peripherals.

[0026] It should be emphasized that although in this embodiment, both the readout circuit 300 and the logic control circuit 500 are disposed on the substrate 100, their functions are not limited to being implemented on the substrate 100. The sensing array 200 can also receive logic control from the peripheral device and directly output the different electrical signals obtained from scanning the fingerprint to the peripheral device for fingerprint pattern analysis. In this case, it is not necessary to separately set the logic control circuit 500 on the substrate 100. At the same time, the function of the readout circuit 300 is not limited in this invention. In addition to functions such as organizing and converting multiple electrical signals, some embodiments may also include functions such as storage, comparison, and verification. This invention does not make specific limitations.

[0027] The following will specifically describe the arrangement of the sensing units within the sensing array 200 and the structural configuration of the logic control circuit 500 corresponding to the arrangement of the sensing units in this embodiment. Figure 2 As shown.

[0028] In this embodiment, the sensing array 200 is configured to be arranged in an m×n matrix of isolation well units 2, and the readout circuit 300 is provided with a plurality of integration circuits 3 corresponding to the n columns of isolation well units 2. As can be seen from the above description, at least one isolation well unit 2 and integration circuit 3 are disposed on the substrate 100.

[0029] On the one hand, the sensing array 200 has multiple isolation well units 2 arranged in rows. The logic control circuit 500 also includes a first row bus 511, a second row bus 512, a first pulse power supply 521, and a second pulse power supply 522, which are set corresponding to each row of isolation well units 2. The first row bus 511 is configured to be connected to the first pulse power supply 521 at one end, and the second row bus 512 is configured to be connected to the second pulse power supply 522 at one end. The other ends of the first row bus 511 and the second row bus 512 that are not connected to the pulse power supply are respectively connected to different switches inside the isolation well unit 2. In this way, the first pulse power supply 521 and the second pulse power supply 522 will output pulse voltage according to a certain working sequence, and input to different switches inside a single isolation well unit 2 through the first row bus 511 and the second row bus 512 respectively, thereby controlling the switches to close or close. Finally, the scanning process in the fingerprint sensing process can be realized, and the circuit anti-interference capability can be improved.

[0030] by Figure 2 Taking the first isolation well unit 2A shown as an example, the first isolation well unit 2A includes a first unit first switch 41A and a first unit second switch 42A. The first unit first switch 41A is connected to the end of the first row bus 511 that is not connected to the first pulse power supply 521, and the first unit second switch 42A is connected to the end of the second row bus 512 that is not connected to the second pulse power supply 522. Thus, they are opened and closed under the control of a preset working sequence. Of course, since the isolation well units 2 are arranged in rows in the sensing array 200, the first row bus 511 is actually configured to connect one end to the first pulse power supply 521 and the other end to the first switch 41 of each row of isolation well units 2. The second row bus 512 is correspondingly configured to connect one end to the second pulse power supply 522 and the other end to the second switch 42 of each row of isolation well units 2.

[0031] On the other hand, the sensor array 200 has multiple isolation well units 2 arranged in columns. Similar to the integration circuit 3 in the readout circuit 300, the fingerprint sensor circuit also includes a column bus 53 corresponding to each column of isolation well units. One end of the column bus 53 is connected to the integration circuit 3, and the other end is connected to the second switch 42 of each column of isolation well units 2. Specifically, Figure 2The diagram shows three isolation well units 2 arranged in columns: a first isolation well unit 2A, a second isolation well unit 2B, and a third isolation well unit 2C. The first isolation well unit 2A includes a first unit first switch 41A and a first unit second switch 42A. The second isolation well unit 2B includes a second unit first switch 41B and a second unit second switch 42B. The third isolation well unit 2C includes a third unit first switch 41C and a third unit second switch 42C. One end of the column bus 53 is connected to the integrator circuit 3 corresponding to the column, and the other end is connected to the first unit second switch 42A, the second unit second switch 42B, and the third unit second switch 42C, respectively. In this way, the column bus 53, relying on the opening and closing of the second switch 42 of each isolation well unit 2, intermittently transmits the electrical signal sensed by the isolation well unit 2 to the readout circuit 300 where the integrator circuit 3 is located.

[0032] Of course, in order to control each first switch 41 and second switch 42 in each column of isolation well unit 2, the first row bus 511 and second row bus 512 mentioned above are arranged at the front end of different rows of isolation well units 2 in each column, and should be arranged separately. Specifically, the front end of the first isolation well unit 2A includes the first unit first row bus 511A and the first unit second row bus 512A, the second isolation well unit 2B includes the second unit first row bus 511B and the second unit second row bus 512B, and the third isolation well unit 2C includes the third unit first row bus 511C and the third unit second row bus 512C. Specifically, the first row bus 511A of the first unit is connected to the first switch 41A of the first unit, the second row bus 512A of the first unit is connected to the second switch 42A of the first unit, the first row bus 511B of the second unit is connected to the first switch 41B of the second unit, the second row bus 512B of the second unit is connected to the second switch 42B of the second unit, the first row bus 511C of the third unit is connected to the first switch 41C of the third unit, and the second row bus 512C of the third unit is connected to the second switch 42C of the third unit. The opening and closing of the above switches are controlled in this way to achieve scanning and anti-interference.

[0033] Understandably, according to Figure 2It is known that each of the first switches 41 and the second switches 42 is triggered and performs opening and closing actions in a preset working sequence. The first row bus 511A of the first unit, the first row bus 511B of the second unit, and the first row bus 511C of the third unit can be configured to be connected to the first pulse power supply 521 respectively. At the same time, the second row bus 512A of the first unit, the second row bus 512B of the second unit, and the second row bus 512C of the third unit can be configured to be connected to the second pulse power supply 522 respectively. By controlling the working sequence of the first pulse power supply 521 and the second pulse power supply 522, so that they sequentially supply power to the first isolation well unit 2A, the second isolation well unit 2B, and the third isolation well unit 2C, the expected technical effect can be achieved.

[0034] In other embodiments, the different first row buses 511 and second row buses 512 connected to each isolation well unit 2 can, of course, be configured to be connected to different pulse power supplies, thereby achieving the technical effect of controlling the first isolation well unit 2A, the second isolation well unit 2B, and the third isolation well unit 2C to operate sequentially. Meanwhile, this embodiment, based on a matrix arrangement, sets up a cooperative structure of column buses 53 and integrator circuits 3 at each column of isolation well units 2. However, this does not mean that this implementation method must be used in other embodiments. Electrical signals can be exported through specially configured data lines, or the integrator circuits 3 set in each column can be replaced with different pins of a single control chip, all of which can achieve the expected technical effect of this invention.

[0035] The following will combine Figure 3 The specific structure of a single isolation well unit 2 and its cooperating integrating circuit 3 is described below. Specifically, the isolation well unit 2 is equipped with a sensing unit 4 and a coupling capacitor 21. The sensing unit 4 includes a sensing capacitor 40, a first switch 41, and a second switch 42. The first plate 401 of the sensing capacitor 40 represents the finger being sensed, and the second plate 402 of the sensing capacitor 40 is used to sense the finger touch and forms a capacitance of different values ​​according to the depth of the fingerprint pattern. The second plate 402 of the sensing capacitor 40 is connected to the first terminal 411 of the first switch 41, the third terminal 421 of the second switch 42, and the third plate 211 of the coupling capacitor. The fourth terminal 422 of the second switch 42 is connected to the integrating circuit 3. Thus, when the opening and closing states of the first switch 41 and the second switch 42 meet the preset closing conditions, at least one of the sensing capacitor 40 and the coupling capacitor 21 will receive a drive from one side and accumulate charge. The second switch 42 will be turned on, and the accumulated charge will be transferred to the integrating circuit 3 through the column bus 53, that is, an electrical signal will be output.

[0036] During this process, the condition for the sensing capacitor 40 to accumulate charge is that the second plate 402 of the sensing capacitor 40 cooperates with the first plate 401, which has a ground level generated by the finger, so that the sensing capacitor 40 is formed and there is a potential difference on both sides, so as to accumulate charge. When the accumulated charge enters the column bus 53 for output through the second switch 42 in the closed state, the charge accumulated by the coupling capacitor 21 in this process will be output at the same time. Therefore, this embodiment is configured with a first switch 41 and a second switch 42 that operate according to different working sequences, and is configured with the circuit structure as described above, so that when the sensing capacitor 40 is formed and has charge accumulation, the coupling capacitor 21 does not accumulate charge, so as to reduce the influence of the charge accumulated by the coupling capacitor 21 on the final output electrical signal.

[0037] To further enhance the quality of the output electrical signal, the isolation well unit 2 in this embodiment also has a special configuration. Specifically, it is configured to be driven according to a preset isolation level. The isolation level is configured as a pulse waveform, and the duty cycle and working sequence can be configured according to the needs of those skilled in the art. It is only necessary to ensure that the second terminal 412 of the first switch 41, the fourth plate 212 of the coupling capacitor 21 and the integrating circuit 3 are configured to be connected to the isolation well unit 2 and driven synchronously with the isolation level. Thus, the voltage levels of at least the first switch 41 and the coupling capacitor 21 located in the isolation well unit 2 will fluctuate with the pulses of the isolation level. When the first switch 41 is closed, the isolation level will reach the coupling capacitor 21 and the sensing capacitor 40 through the second terminal 412 of the first switch 41, and will also be applied to the fourth plate 212 of the coupling capacitor 21. In this state, the coupling capacitor 21 will not accumulate charge, thus reducing the influence of the coupling capacitor 21 on the electrical signal output. Since the first plate 401 of the sensing capacitor 40 is connected to the equivalent ground level, it can still accumulate charge and output under the pulses of the isolation level, thereby improving the overall anti-interference capability and accuracy of the circuit.

[0038] Furthermore, regarding the integrator circuit 3 in the readout circuit 300, this invention provides a specific implementation to integrate the output electrical signal and achieve the technical effect of further reducing the charge accumulation in the coupling capacitor 21. For example... Figure 3As shown, the integrating circuit 3 specifically includes an operational amplifier 31, an integrating capacitor 32, and a reference voltage source 33. The non-inverting input terminal 312 of the operational amplifier 31 is connected to the fourth terminal 422 of the second switch 42. In this embodiment, the connection is established through the column bus 53. The two ends of the integrating capacitor 32 are connected to the non-inverting input terminal 312 and the output terminal 310 of the operational amplifier 31, respectively. The inverting input terminal 311 of the operational amplifier 31 is connected to the reference voltage source 33, thus performing integration on the electrical signal output from the second switch 42. As described above, the integrating circuit 3 is configured to connect to the isolation well unit 2. Therefore, in this embodiment, the operational amplifier 31 in the integrating circuit 3 is specifically configured to connect to the isolation well unit 2 and drive synchronously with the isolation level.

[0039] Regarding the configuration of the fourth plate 212 of the coupling capacitor 21 and the operational amplifier 31 of the integrator circuit 3 to be synchronously driven with the isolation level of the isolation well unit 2, in addition to setting all the components inside the isolation well unit 2 at the hardware level and configuring the levels of multiple isolation well units 2 to be mutually isolated, this embodiment also has a special structural configuration for the isolation well unit 2. Specifically, the isolation well unit 2 includes a signal terminal 20 for controlling the isolation level. The control referred to here may include the control of parameters such as the duty cycle, frequency and amplitude of the isolation level pulse waveform, and may also include the control of the input signal type and whether the isolation level is input. Furthermore, the signal terminal 20 is connected to the second terminal of the first switch 41, the fourth plate 212 of the coupling capacitor 21, and the operational amplifier 31 of the integrating circuit 3, thereby providing the lowest potential of the sensing capacitor 40, the coupling capacitor 21, and the integrating circuit 3 to switch between a preset first potential and a preset second potential. One of the first and second potentials is configured as a low level, and the other as a high level. Thus, when the input is high, the coupling capacitor 21 is shielded, the sensing capacitor 40 triggers scanning and accumulates charge, while when the input is low and there is no external power supply, the electrical signal of the sensing capacitor 40 can be extracted. To enhance the purity of the level signal, in this embodiment, the first potential is configured as ground level, and the second potential is configured as high level.

[0040] Based on the fact that the integrator circuit 3 in this embodiment is equipped with a reference voltage source 33, when the second switch 42 is closed, based on the "virtual short" principle of the operational amplifier 31, the level of the reference voltage source 33 is conducted between the sensing capacitor 40 and the coupling capacitor 21, and charge accumulation occurs again. In order to reduce the influence of this phenomenon on the output electrical signal, the first switch 41 and the second switch 42 are configured to have a special working sequence. The coordination of this working sequence with the isolation level can eliminate the influence of charge accumulation in the coupling capacitor 21 by repeatedly switching on and off within a single cycle.

[0041] Specifically, such as Figure 3 and Figure 4 As shown, the working timing configuration of the isolation well unit 2 is as follows: In the first state, the second switch 42 is de-energized and disconnected, the signal terminal 20 receives the level control signal and is driven to the second potential, and the first switch 41 is energized and driven to close; in the second state, the first switch 41 is de-energized and disconnected, the signal terminal 20 receives the level control signal and is switched to the first potential, and the second switch 42 is energized and driven to close. Figure 4 The diagram shows the operating timing and level switching of signal terminal 20, first switch 41 and second switch 42. Signal terminal 20 is controlled to switch between ground level 0 as the first potential and high level Vd as the second potential. First switch 41 is closed under the control of the drive level Vp of the first row bus 511 in this embodiment, and is opened when power is off or when only high level Vd is applied. Second switch 42 is closed under the control of the drive level Vp of the second row bus 512 in this embodiment, and is opened when power is off or when only high level Vd is applied. The first row bus 511 and the second row bus 512 are configured to alternately output drive level Vp.

[0042] In the first state, the second row bus 512 does not output the drive level Vp, the level of the second switch 42 is consistent with the level of the signal terminal 20, the second switch 42 is open, the sensing capacitor 40 and the coupling capacitor 21 in the isolation well unit 2 are isolated, the potential of the signal terminal 20 is driven to a high level Vd, the first row bus 511 outputs the drive level Vp, the first switch 41 is closed by the drive level Vp, and the high level Vd at the second terminal 412 is conducted to the second plate 402 of the sensing capacitor 40 and the third plate 211 of the coupling capacitor 21. Thus, the sensing capacitor 40 accumulates charge based on the potential difference, and the coupling capacitor 21 does not accumulate charge because there is no potential difference.

[0043] In the second state, the first bus 511 switches to ground level or another level lower than the difference between the drive level Vp and the high level Vd. The first switch 41 is open, and the sensing capacitor 40 and coupling capacitor 21 in the isolation well unit 2 are isolated from the front end on the side of the first switch 41. The potential of the signal terminal 20 is switched to ground level 0. The second bus 512 outputs the drive level Vp, and the second switch 42 is closed by the drive level Vp. The level of the reference voltage source 33, which is connected to the fourth terminal 422 of the second switch 42 through a "virtual short", is connected between the sensing capacitor 40 and the coupling capacitor 21. The sensing capacitor 40 and the coupling capacitor 21 generate the same potential difference and accumulate charge at the same time.

[0044] As can be seen from the above process, within a cycle formed by the combination of the first and second states, the sensing capacitor 40 will accumulate charge twice, and the coupling capacitor 21 will accumulate charge once. The amount of output charge during the re-discharge process is different. At the same time, since the sensing capacitor 40, the coupling capacitor 21, and the operational amplifier 31 are all connected to the isolation level in this embodiment, the output voltage of the reference voltage source 33 can be equivalent to 0. This means that in the second state, neither the sensing capacitor 40 nor the coupling capacitor 21 will accumulate charge, thus further enhancing the anti-interference capability and the accuracy of the output signal.

[0045] Furthermore, in this embodiment, the switching between the first state and the second state is repeated, and the output is sent to the integrating circuit 3 for integration, so that the operational amplifier 31 finally outputs an electrical signal. During this process, the change in output voltage can be quantitatively calculated.

[0046] In the first state, sensing capacitor 40 accumulates charge, generating a first charge, while coupling capacitor 21 accumulates no charge. In the second state, sensing capacitor 40 accumulates charge, generating a second charge, and coupling capacitor 21 accumulates charge, generating a third charge. Therefore, the change in the output voltage of the integrator circuit is:

[0047]

[0048] Furthermore, quantifying the above values, the first charge is the product of the second potential and the capacitance of sensing capacitor 40; the second charge is the product of the reference voltage and the capacitance of sensing capacitor 40; and the third charge is the product of the reference voltage and the capacitance of coupling capacitor 21. That is, we have:

[0049]

[0050] Wherein, ΔVout is the output voltage change, n is the number of integrations, Qf(2) is the second charge, Qd(2) is the third charge, Qf(1) is the first charge, Qd(1) is the charge accumulated by coupling capacitor 21 in the first state (i.e., zero charge), Cint is the capacitance of integration capacitor 32, Vref is the voltage value of reference voltage source 33, Cd is the capacitance of coupling capacitor 21, Cf is the capacitance of sensing capacitor 40, and Vd is the second level (i.e., high level) output by signal terminal 20.

[0051] Furthermore, since the integrating circuit 3 is configured to be electrically connected to the isolation well unit 2, especially to the signal terminal 20, the reference voltage source 33 can also be configured to operate with the isolation level and be equivalent to 0. Thus, the factor containing the reference voltage Vref in the above equation is omitted, and the output voltage change ΔVout and the capacitance Cf of the sensing capacitor 40 satisfy the following linear relationship:

[0052] ΔVout=-n·Vd·Cf;

[0053] Therefore, the output voltage value (i.e., the output electrical signal) satisfies:

[0054] Vout=Vout(s)+ΔVout=Vout(s)-n·Vd·Cf;

[0055] Where Vout is the output voltage, Vout(s) is the typical value of the output voltage, and the number of integrations n can be adjusted according to the thickness of the insulating layer between the finger and the fingerprint sensor circuit. In this embodiment, the number of integrations is configured to be 100≤n≤200.

[0056] This allows for easier calculation of the capacitance Cf of the sensing capacitor 40 under different fingerprint contact states, enabling the generation of an electrical signal output for analysis. As can be seen, this invention, based on configuring the sensing unit in the prior art as an isolation well unit 2 to form a sensing area with different high and low level changes, and configuring the sensing unit with an isolation level having a pulse waveform, ultimately achieves the equivalent of the reference voltage Vref to 0, eliminating the influence of charge accumulation in the internal coupling capacitor 21 on the output electrical signal, thereby improving the overall sensitivity and linearity of the fingerprint sensor circuit.

[0057] In existing technology, to ensure that the output is also 0 when both inputs are 0, an offset voltage Vos is set between the two inputs of operational amplifier 31. However, when this type of operational amplifier is applied to the circuit provided by this invention, especially when both the input and output electrical signals of the operational amplifier are configured as voltage signals, the offset voltage Vos affects the purity of the signal, thus affecting the final analysis and detection results. To further improve the sensitivity, linearity, and accuracy of the fingerprint sensor circuit provided by this invention, the integrating circuit 3 in this embodiment has the following special configuration, such as... Figure 5 As shown.

[0058] The integrating circuit 3 includes an operational amplifier 31, a first reference voltage source 331, a second reference voltage source 332, a first switching contact 341, and a second switching contact 342. The first reference voltage source 331 and the second reference voltage source 332 are respectively connected to the inverting input terminal 311 and the non-inverting input terminal 312 of the operational amplifier 31. The fifth terminal 3411 of the first switching contact 341 and the seventh terminal 3421 of the second switching contact 342 are respectively connected to the column bus 53. The sixth terminal 3412 of the first switching contact 341 is connected to the non-inverting input terminal 312 of the operational amplifier 31. The eighth terminal 3422 of the second switching contact 342 is connected to... The non-inverting input terminal 312 of the operational amplifier 31 is connected to the non-inverting input terminal 311 of the operational amplifier 31. Furthermore, a first linkage switch 351 that opens and closes synchronously with the first switching contact 341 is provided between the first reference voltage source 331 and the operational amplifier 31, and a second linkage switch 352 that opens and closes synchronously with the second switching contact 342 is provided between the second reference voltage source 332 and the operational amplifier 31. The first switching contact 341, the first linkage switch 351, the second switching contact 342, and the second linkage switch 352 are configured to open and close an equal number of times in one cycle.

[0059] While keeping the fingerprint sensor circuit provided by this invention unchanged except for the integrating circuit 3, and considering the offset voltage Vos and without applying the above-described switching structure configuration, the relationships between the second charge Qf(2) and the third charge Qd(2) and the capacitance Cf of the sensing capacitor 40 and the capacitance Cd of the coupling capacitor 21 are changed to satisfy:

[0060] Qf(2) = (Vref + Vos)·Cf;

[0061] Qd(2) = (Vref + Vos)·Cd;

[0062] Therefore, the change in output voltage derived from the charge balance principle is further modified to satisfy:

[0063]

[0064] Assuming the reference voltage Vref is equivalent to 0, and given that the capacitance Cd of coupling capacitor 21 is much larger than the capacitance Cf of sensing capacitor 40, we can further derive the above equation as follows:

[0065] ΔVout=n·(Vos·Cd-Vd·Cf);

[0066] Therefore, it is evident that when high accuracy is required for the equipment, the offset voltage Vos will affect the output of the sensor circuit, leading to a decrease in linearity. Continuing, with the aforementioned switching structure configured between the two outputs of the operational amplifier 31, and the first switching contact 341, the first linkage switch 351, the second switching contact 342, and the second linkage switch 352 configured to open and close an equal number of times within one cycle:

[0067] (1) The first switching contact 341 and the first linkage switch 351 are closed, the second switching contact 342 and the second linkage switch 352 are open, the non-inverting input terminal 312 of the operational amplifier 31 is connected to the fourth terminal 422 of the second switch 42 in the isolation well unit 2 through the column bus 53 to receive electrical signals, and the inverting input terminal 311 of the operational amplifier 31 is connected to the first reference voltage source 331. At the same time, since there is an offset voltage Vos between the non-inverting input terminal 312 and the inverting input terminal 311, in this state, the relationship between the second charge Qf (2) and the third charge Qd (2) and the capacitance Cf of the sensing capacitor 40 and the capacitance Cd of the coupling capacitor 21 respectively changes to satisfy:

[0068] Qf(2) = (Vref1 + Vos)·Cf;

[0069] Qd(2) = (Vref1 + Vos)·Cd;

[0070] (2) The second switching contact 342 and the second linkage switch 352 are closed, the first switching contact 341 and the second linkage switch 352 are open, the non-inverting input terminal 312 of the operational amplifier 31 is connected to the second reference voltage source 332, and the inverting input terminal 311 of the operational amplifier 31 is connected to the fourth terminal 422 of the second switch 42 in the isolation well unit 2 through the column bus 53 to receive electrical signals. At this time, since the reference voltage is switched to be input through the non-inverting input terminal 312, the relationship between the second charge Qf (2) and the third charge Qd (2) and the capacitance Cf of the sensing capacitor 40 and the capacitance Cd of the coupling capacitor 21 respectively changes to satisfy:

[0071] Qf(2) = (Vref2 - Vos)·Cf;

[0072] Qd(2) = (Vref2 - Vos)·Cd;

[0073] Thus, when the reference voltage values ​​Vref1 and Vref2 input to the first reference voltage source 331 and the second reference voltage source 332 are configured to be equal, and based on the configuration of the first switching contact 341, the first linkage switch 351, the second switching contact 342, and the second linkage switch 352 being configured to open and close an equal number of times within one cycle, the offset voltage Vos will be canceled out during the switching process, thereby ensuring that the final output voltage change still satisfies:

[0074] ΔVout=n·Vd·Cf;

[0075] The output voltage can also meet the requirements:

[0076] Vout=Vout(s)+ΔVout=Vout(s)-n·Vd·Cf;

[0077] It is worth noting that the equal number of opening and closing times mentioned here can be understood as configuring the circuit so that after the first switching contact 341 and the first linkage switch 351 are turned on for a preset time, the circuit is triggered to switch to the second switching contact 342 and the second linkage switch 352 for the same preset time. Alternatively, the number of times the first switching contact 341, the first linkage switch 351, the second switching contact 342, and the second linkage switch 352 are switched can be configured to be half of the integral number, both of which can achieve the expected technical effect. The resulting different circuit configurations can be adjusted according to the needs of those skilled in the art.

[0078] To further achieve the above effects, the integrating circuit 3 in this embodiment further includes a first control line 541 and a second control line 542 connected to the operational amplifier 31. The first control line 541 connects the first switching contact 341 and the first linkage switch 351, and the second control line 542 connects the second switching contact 342 and the second linkage switch 352. In this way, by configuring the operational amplifier 31 as a chopper-type operational amplifier, control signals can be provided to the switching contact and the linkage switch, and flicker noise and other noise can be further reduced, and harmonics of the triangular wave can be filtered out. Of course, the first control line 541 and the second control line 542 can also be connected to other components that can output control signals, or even without the first control line 541 and the second control line 542, similar technical effects can be achieved.

[0079] In summary, compared with the prior art, the fingerprint sensor circuit provided by the present invention, by setting up an isolation well unit 2, configuring the isolation well unit 2 with an isolation level having a pulse waveform, and connecting components such as the coupling capacitor 21 to the isolation level, can maintain synchronous driving of components within the isolation well unit 2, reduce the influence of the coupling capacitor 21 on the output of the sensor circuit, improve the linearity between the circuit output and the measured capacitor, and enhance the sensitivity of the fingerprint sensor.

[0080] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0081] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fingerprint sensor circuit, characterized in that, It includes a substrate (100) and at least one isolation well unit (2) and an integration circuit (3) disposed on the substrate (100); The isolation well unit (2) is provided with a sensing unit (4) and a coupling capacitor (21). The sensing unit (4) includes a sensing capacitor (40), a first switch (41) and a second switch (42). The first plate (401) of the sensing capacitor (40) represents the finger being sensed. The second plate (402) of the sensing capacitor (40) is connected to the first terminal (411) of the first switch (41), the third terminal (421) of the second switch (42) and the third plate (211) of the coupling capacitor (21). The fourth terminal (422) of the second switch (42) is connected to the integrating circuit (3). The isolation well unit (2) is configured to be driven according to a preset isolation level, the isolation level being configured to have a pulse waveform. The second terminal (412) of the first switch (41), the fourth plate (212) of the coupling capacitor (21) and the integrator (3) are connected to the isolation well unit (2) and configured to be driven synchronously following the isolation level. The operating sequence of the isolation well unit is as follows: First state: The second switch (42) is open, and the first switch (41) is closed; Second state: The first switch (41) is open and the second switch (42) is closed.

2. The fingerprint sensor circuit according to claim 1, characterized in that, The integrating circuit (3) includes an operational amplifier (31), an integrating capacitor (32), and a reference voltage source (33). The non-inverting input terminal (312) of the operational amplifier (31) is connected to the fourth terminal (422) of the second switch (42). The two ends of the integrating capacitor (32) are respectively connected to the non-inverting input terminal (312) and the output terminal (310) of the operational amplifier (31). The inverting input terminal (311) of the operational amplifier (31) is connected to the reference voltage source (33). The operational amplifier (31) is connected to the isolation well unit (2) and is configured to drive synchronously with the isolation level.

3. The fingerprint sensor circuit according to claim 2, characterized in that, The isolation well unit (2) includes a signal terminal (20) for controlling the isolation level. The signal terminal (20) is connected to the second terminal (412), the fourth plate (212) and the operational amplifier (31), and provides the lowest potential of the sensing capacitor (40), the coupling capacitor (21) and the integrating circuit (3) to switch between a preset first potential and a second potential; wherein the first potential is ground level and the second potential is high level.

4. The fingerprint sensor circuit according to claim 3, characterized in that, The operating sequence of the isolation well unit is as follows: First state: The second switch (42) is open, driving the signal terminal (20) to the second potential, and the first switch (41) is closed; Second state: The first switch (41) is open, the signal terminal (20) is switched to the first potential, and the second switch (42) is closed.

5. The fingerprint sensor circuit according to claim 4, characterized in that, In the first state, the sensing capacitor (40) accumulates charge to generate a first charge, while the coupling capacitor (21) does not accumulate charge. In the second state, the sensing capacitor (40) accumulates charge to generate a second charge, and the coupling capacitor (21) accumulates charge to generate a third charge. The change in the output voltage of the integrating circuit (3) is as follows: 。 6. The fingerprint sensor circuit according to claim 5, characterized in that, The first charge is the product of the second potential and the sensing capacitor (40), the second charge is the product of the reference voltage and the sensing capacitor (40), and the third charge is the product of the reference voltage and the coupling capacitor (21).

7. The fingerprint sensor circuit according to claim 1, characterized in that, The isolation well units (2) are arranged in multiple rows. The circuit also includes a first row bus (511), a second row bus (512), a first pulse power supply (521), and a second pulse power supply (522) for each row of isolation well units (2). One end of the first row bus (511) is connected to the first pulse power supply (521), and the other end is connected to the first switch (41) of each isolation well unit (2). One end of the second row bus (512) is connected to the second pulse power supply (522), and the other end is connected to the second switch (42) of each isolation well unit (2).

8. The fingerprint sensor circuit according to claim 1, characterized in that, The isolation well units (2) are arranged in multiple columns. The circuit also includes a column bus (53). The column bus (53) and the integrator circuit (3) are set in correspondence with each column of the isolation well units (2). One end of the column bus (53) is connected to the integrator circuit (3), and the other end is connected to the second switch (42) of each isolation well unit (2).

9. The fingerprint sensor circuit according to claim 8, characterized in that, The integrating circuit (3) includes an operational amplifier (31), a first reference voltage source (331), a second reference voltage source (332), a first switching contact (341), and a second switching contact (342). The first reference voltage source (331) and the second reference voltage source (332) are respectively connected to the inverting input terminal (311) and the non-inverting input terminal (312) of the operational amplifier (31). The fifth terminal (3411) of the first switching contact (341) and the seventh terminal (3421) of the second switching contact (342) are respectively connected to the column bus (53). The sixth terminal (3412) of the first switching contact (341) is connected to the non-inverting input terminal (312) of the operational amplifier (31). The eighth terminal (3422) of the second switching contact (342) is connected to the inverting input terminal (311) of the operational amplifier (31). A first linkage switch (351) that opens and closes synchronously with the first switching contact (341) is provided between the first reference voltage source (331) and the operational amplifier (31), and a second linkage switch (352) that opens and closes synchronously with the second switching contact (342) is provided between the second reference voltage source (332) and the operational amplifier (31); the first switching contact (341), the first linkage switch (351), the second switching contact (342), and the second linkage switch (352) are configured to open and close an equal number of times in one cycle.

10. The fingerprint sensor circuit according to claim 9, characterized in that, The integrating circuit (3) further includes a first control line (541) and a second control line (542) connected to the operational amplifier (31). The first control line (541) is connected to the first switching contact (341) and the first linkage switch (351), and the second control line (542) is connected to the second switching contact (342) and the second linkage switch (352).

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