Encapsulated chip, encapsulation structure, circuit board and manufacturing method thereof

Abstract

The present application provides a method for manufacturing a circuit board, which includes the steps of: providing a carrier board, the carrier board including a substrate layer and a peelable layer disposed on the substrate layer, the carrier board being provided with a first opening that penetrates the peelable layer and at least part of the substrate layer. A dielectric layer is disposed on the peelable layer, and part of the dielectric layer is filled into the first opening to form a positioning post. A connection pad is disposed on the dielectric layer, and the peelable layer and the substrate layer are removed to obtain the circuit board. The method for manufacturing a circuit board provided by the present application improves the connection strength between the circuit board and the main board by providing a positioning post on one side of the dielectric layer, and the positioning post can be used to insert into the positioning hole of the main board, thereby reducing the risk of the circuit board falling off or being misaligned. In addition, the present application also provides a circuit board, a packaged chip, and a packaging structure.

Description

Technical Field

[0001] The present application relates to a method for manufacturing a packaged chip, a packaging structure, a circuit board, and a circuit. Background Art

[0002] Generally, a circuit board and a packaging substrate are connected by solder balls. The solder ball connection method may have the problem of insufficient connection strength, such that in a severely vibrating or high-temperature and high-humidity environment, the packaging substrate may be misaligned or detached. Summary of the Invention

[0003] To solve the problems in the background art, the present application provides a method for manufacturing a circuit board.

[0004] In addition, it is also necessary to provide a circuit board.

[0005] In addition, it is also necessary to provide a packaged chip.

[0006] In addition, it is also necessary to provide a packaging structure.

[0007] A method for manufacturing a circuit board includes the steps of: providing a carrier plate, the carrier plate including a substrate layer and a peelable layer disposed on the substrate layer, the carrier plate having a first opening that penetrates the peelable layer and at least part of the substrate layer. Disposing a dielectric layer on the peelable layer, and filling part of the dielectric layer into the first opening to form a positioning post. The dielectric layer is provided with a connection pad, and the connection pad is exposed on the dielectric layer. Removing the peelable layer and the substrate layer to obtain the circuit board.

[0008] Further, the connection pad includes an inner connection pad and an outer connection pad electrically connected to the inner connection pad. The step of "disposing a connection pad on the dielectric layer" includes: disposing the inner connection pad on part of the peelable layer, disposing the dielectric layer on the inner connection pad, and forming a second opening in the dielectric layer. The inner connection pad is exposed at the bottom of the second opening, and electroplating a plurality of the outer connection pads on a side of the dielectric layer facing away from the inner connection pad. Part of the outer connection pads are filled into the second opening to form a conduction body, and the conduction body electrically connects the inner connection pad and the outer connection pad.

[0009] Further, the dielectric layer has the same material as the substrate layer. The step of "removing the peelable layer and the substrate layer" includes: removing part of the substrate layer around the positioning post, and removing the peelable layer to separate another part of the substrate layer from the dielectric layer.

[0010] Furthermore, the carrier board also includes a first copper layer, which is arranged on the side of the substrate layer away from the dielectric layer, and the positioning column is connected to the first copper layer. The manufacturing method also includes the step of etching the first copper layer to form a plurality of connecting blocks, and the connecting blocks are arranged on the positioning column.

[0011] Furthermore, the carrier board also includes a second copper layer, which is arranged between the dielectric layer and the substrate layer. Before the step of "removing the peelable layer to separate another part of the substrate layer from the dielectric layer", it also includes: removing part of the second copper layer around the positioning column.

[0012] Furthermore, the method further comprises the steps of: disposing a solder mask layer on opposite sides of the dielectric layer, the solder mask layer being provided with a plurality of openings, and the connection pad being exposed at the bottom of the openings.

[0013] Furthermore, the method further comprises the step of: providing a protective layer on the outer surface of the connection pad.

[0014] A circuit board comprises a dielectric layer, a connection pad and a positioning column, wherein the positioning column is protrudingly arranged on one side of the dielectric layer, and the connection pad is arranged on the dielectric layer.

[0015] A packaged chip comprises a chip, a package body, solder balls and the circuit board as described above, wherein the chip is arranged on the other side of the dielectric layer, the package body covers the chip, the chip is electrically connected to part of the connection pads, and the solder balls are electrically connected to another part of the connection pads.

[0016] A packaging structure includes a mainboard and the packaging chip as described above, wherein the mainboard includes a main body and a plurality of connecting parts, the main body is penetrated by a positioning hole, the positioning column is accommodated in the positioning hole, and the connecting part is electrically connected to the solder ball.

[0017] The circuit board provided in the present application has a positioning column arranged on one side of the dielectric layer, and the positioning column can be used to be inserted into the positioning hole of the main board, thereby improving the connection strength between the circuit board and the main board and reducing the risk of the circuit board falling off or being misplaced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a carrier substrate provided in accordance with an embodiment of the present application.

[0019] Figure 2 for Figure 1 The schematic diagram shown is a carrier substrate after the first dry film is provided.

[0020] Figure 3 for Figure 1 The schematic diagram shown is after the first photosensitive pattern is set on the carrier substrate.

[0021] Figure 4 For Figure 1 Schematic diagram of setting the first half-hole on the carrier substrate shown

[0022] Figure 5 For Figure 1 Schematic diagram of setting the first opening on the carrier substrate shown

[0023] Figure 6 For Figure 5 Schematic diagram of setting the second dry film on the carrier substrate shown

[0024] Figure 7 For Figure 5 Schematic diagram of setting the second photosensitive pattern on the carrier substrate shown

[0025] Figure 8 Schematic diagram of the carrier provided by an embodiment of the present application

[0026] Figure 9 For Figure 8 Schematic diagram of setting the dielectric layer on the carrier shown

[0027] Figure 10 For Figure 9 Schematic diagram of setting the plating layer on the node layer shown

[0028] Figure 11 For Figure 10 Schematic diagram of setting the third dry film on the plating layer shown

[0029] Figure 12 For Figure 10 Schematic diagram of setting the third photosensitive pattern on the plating layer shown

[0030] Figure 13 For Figure 10 Schematic diagram of setting the outer connection pad on the plating layer shown

[0031] Figure 14 For removing Figure 13 Schematic diagram after removing the third photosensitive pattern shown

[0032] Figure 15 For Figure 14 Schematic diagram of setting the fourth dry film on the second copper plating layer shown

[0033] Figure 16 For Figure 14 Schematic diagram of setting the fourth photosensitive pattern on the second copper plating layer shown

[0034] Figure 17 For Figure 16 Schematic diagram of setting the connection block on the positioning post shown

[0035] Figure 18 Schematic diagram after removing part of the dielectric layer around the positioning post shown Figure 16

[0036] Figure 19 Schematic diagram after removing part of the first copper-carrying layer and part of the peelable layer around the positioning post shown Figure 18

[0037] Figure 20 Schematic diagram after removing the remaining part of the peelable layer shown Figure 19

[0038] Figure 21 Schematic diagram after removing the plating layer shown Figure 20

[0039] Figure 22 Schematic diagram after applying solder mask layers on opposite sides of the dielectric layer shown Figure 21

[0040] Figure 23 Schematic diagram of a circuit board provided by an embodiment of the present application

[0041] Figure 24 Schematic diagram of a packaged chip provided by an embodiment of the present application

[0042] Figure 25 Schematic diagram of a packaging structure provided by an embodiment of the present application

[0043] Description of main component symbols

[0044] Circuit board 100

[0045] Carrier board 10

[0046] Base material layer 11

[0047] First copper-carrying layer 12

[0048] Second copper-carrying layer 13

[0049] Peelable layer 14

[0050] First opening 15

[0051] First half hole 151

[0052] Second half hole 152

[0053] Inner connecting pad 16

[0054] First protective layer 161

[0055] Outer connecting pad 17 ​​​​​

[0056] Second protective layer 171

[0057] Carrier substrate 20

[0058] First dry film 21

[0059] First photosensitive pattern 22

[0060] First etching groove 221

[0061] Second dry film 23

[0062] Second photosensitive pattern 24

[0063] First electroplating groove 241

[0064] Dielectric layer 30

[0065] Alignment post 31

[0066] Plated via hole 32

[0067] Electroplated layer 33

[0068] Seed layer 34

[0069] Third dry film 35

[0070] Third photosensitive pattern 36

[0071] Second electroplating groove 361

[0072] Fourth dry film 41

[0073] Fourth photosensitive pattern 42

[0074] Second etching groove 421

[0075] Connection block 43

[0076] Third protective layer 431

[0077] Annular hole 44

[0078] Solder mask 50

[0079] Window opening 51

[0080] Encapsulated chip 200

[0081] Chip 201

[0082] Package body 202

[0083] Solder ball 203

[0084] Package structure 300

[0085] Main board 301

[0086] Positioning hole 3011

[0087] Body part 302

[0088] Connection part 303

[0089] Conductive pad 304

[0090] Thickness direction H

[0091] The following specific embodiments will further illustrate the present application in conjunction with the above drawings. Specific embodiments

[0092] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0093] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. When an element is considered to be "disposed on" another element, it can be directly disposed on the other element or there may be an intermediate element at the same time.

[0094] Please refer to Figures 1 to 23 , the embodiments of the present application provide a method for manufacturing a circuit board 100, including the steps:

[0095] S1: Please refer to Figure 8 , provide a carrier board 10, the carrier board 10 includes a substrate layer 11, a first copper-clad layer 12, a second copper-clad layer 13, and a peelable layer 14. The first copper-clad layer 12 and the second copper-clad layer 13 are respectively disposed on opposite sides of the substrate layer 11, and the peelable layer 14 is disposed on the second copper-clad layer 13. The carrier board 10 has a thickness direction H, and a plurality of first openings 15 are provided in the carrier board 10 along the thickness direction H. The first openings 15 penetrate through the peelable layer 14, the second copper-clad layer 13, and the substrate layer 11, and part of the first copper-clad layer 12 is exposed at the bottom of the first openings 15.

[0096] In other embodiments of the present application, the first copper-clad layer 12 and the second copper-clad layer 13 can be omitted, and the first openings 15 can penetrate through the peelable layer 14 and part of the substrate layer 11.

[0097] In this embodiment, please refer to Figure 8 , the carrier board 10 further includes a plurality of inner connection pads 16, and the inner connection pads 16 are spaced apart and disposed on the peelable layer 14. In some embodiments, the manufacturing method of the carrier board 10 includes:

[0098] S10: Refer to Figure 1 , provide a carrier substrate 20, and the carrier substrate 20 includes the base material layer 11, the first copper-carrying layer 12, the second copper-carrying layer 13, and the peelable layer 14.

[0099] S11: Refer to Figure 2 , press the first dry film 21 on the opposite sides of the carrier substrate 20 respectively.

[0100] S12: Refer to Figure 3 , expose and develop the first dry film 21 disposed on the peelable layer 14 to obtain a first photosensitive pattern 22, and the first photosensitive pattern 22 has a plurality of first etching grooves 221.

[0101] S13: Refer to Figure 4 , etch a part of the peelable layer 14 and a part of the second copper-carrying layer 13 corresponding to the first etching grooves 221 with a chemical solution to obtain a plurality of first half holes 151, and remove the first photosensitive pattern 22 and the unexposed first dry film 21.

[0102] S14: Refer to Figure 5 , remove a part of the base material layer 11 corresponding to the first half holes 151 by mechanical drilling or laser etching to obtain a plurality of second half holes 152, and the first half holes 151 communicate with the second half holes 152 to form the first opening 15.

[0103] S15: Refer to Figure 6 , press the second dry film 23 on the opposite sides of the carrier substrate 20 having the first opening 15 respectively, wherein the second dry film 23 covers the first opening 15.

[0104] S16: Refer to Figure 7 , expose and develop the second dry film 23 disposed on the peelable layer 14 to obtain a second photosensitive pattern 24, and the second photosensitive pattern 24 has a plurality of first electroplating grooves 241, and a part of the peelable layer 14 is exposed at the bottom of the first electroplating grooves 241.

[0105] S17: Refer to Figure 8 , electroplate to form the inner connection pads 16 in the first electroplating grooves 241, and remove the second photosensitive pattern 24 and the unexposed second dry film 23 to obtain the carrier 10.

[0106] S2: Refer to Figure 9 , dispose a dielectric layer 30 on the peelable layer 14, and the dielectric layer 30 covers the inner connection pads 16. A part of the dielectric layer 30 also fills into the first opening 15 to form the positioning posts 31.

[0107] S3: Please refer to Figures 10 to 15 , on the side of the dielectric layer 30 facing away from the positioning post 31, an outer connection pad 17 is provided, and the outer connection pad 17 is electrically connected to the inner connection pad 16.

[0108] In this embodiment, step S3 includes:

[0109] S30: Please refer to Figure 10 , on the dielectric layer 30, a plating through hole 32 is provided, and the plating through hole 32 penetrates the dielectric layer 30 along the thickness direction H, and the inner connection pad 16 is exposed at the bottom of the plating through hole 32.

[0110] S31: Please refer to Figure 10 , on the dielectric layer 30, a plating layer 33 is provided, and part of the plating layer 33 is filled into the plating through hole 32 to form a seed layer 34.

[0111] S32: Please refer to Figure 11 , on the plating layer 33, a third dry film 35 is provided, and the third dry film 35 covers the plating through hole 32.

[0112] S33: Please refer to Figure 12 , the third dry film 35 is exposed and developed to form a third photosensitive pattern 36, the third photosensitive pattern 36 has a plurality of second plating grooves 361, and part of the plating layer 33 is exposed at the bottom of the second plating grooves 361.

[0113] S34: Please refer to Figure 13 , the outer connection pad 17 is electroplated in the second plating groove 361, and part of the outer connection pad 17 is filled into the plating through hole 32 to form a conductor 37, and the conductor 37 is electrically connected to the inner connection pad 16 and the outer connection pad 17.

[0114] S35: Please refer to Figure 14 , the third photosensitive pattern 36 is removed.

[0115] S4: Please refer to Figures 15 to 21 , the peelable layer 14 and the substrate layer 11 are removed.

[0116] In this embodiment, step S4 includes:

[0117] S40: Please refer to Figure 15 , a fourth dry film 41 is provided on the outer connection pad 17 and the first copper-carrying layer 12.

[0118] S41: Please refer to Figure 16, the fourth dry film 41 disposed on the first copper-bearing layer 12 is exposed and developed to form a fourth photosensitive pattern 42, and the fourth photosensitive pattern 42 has a plurality of second etching grooves 421. Part of the first copper-bearing layer 12 is exposed at the bottom of the second etching groove 421. Along the thickness direction H, the second etching groove 421 is offset from the positioning post 31.

[0119] S42: Please refer to Figure 17 , a part of the first copper-bearing layer 12 corresponding to the second etching groove 421 is removed to form a plurality of connection blocks 43. The connection blocks 43 are disposed on a side of the positioning post 31 away from the dielectric layer 30, and the fourth photosensitive pattern 42 and the unexposed fourth dry film 41 are removed.

[0120] S43: Please refer to Figure 18 , a part of the base material layer 11 around the positioning post 31 is removed by mechanical drilling or laser irradiation to form an annular hole 44, the positioning post 31 is located at the center of the annular hole 44, and the second copper-bearing layer 13 is exposed at the bottom of the annular hole 44. Among them, a part of the base material layer 11 having the same material as the positioning post 31 can be effectively removed by mechanical drilling or laser irradiation. That is, in this embodiment, the dielectric layer 30 and the base material layer 11 have the same material, which is convenient for subsequent separation of the peelable layer 14. It can be understood that if a part of the base material layer 11 around the positioning post 31 is not removed, the bonding strength between the dielectric layer 30 and the base material layer 11 is too large, which is not conducive to the tearing of the peelable layer 14.

[0121] S44: Please refer to Figure 19 , a part of the second copper-bearing layer 13 corresponding to the annular hole 44, a part of the connection blocks 43 not corresponding to the positioning post 31, and a part of the peelable layer 14 are removed. Among them, a part of the second copper-bearing layer 13 corresponding to the annular hole 44 and a part of the peelable layer 14 can be effectively removed by chemical etching.

[0122] S45: Please refer to Figure 20 , the remaining peelable layer 14 is torn off so that the remaining base material layer 11 and the remaining second copper-bearing layer 13 are separated from the dielectric layer 30, and the plating layer 33 (see Figure 21 ) is removed, so that the outer connection pads 17 are electrically insulated from each other.

[0123] In this embodiment, the manufacturing method of the circuit board 100 further includes:

[0124] S5: Please refer to Figure 22, solder mask layers 50 are provided on opposite sides of the dielectric layer 30. The solder mask layers 50 are provided with a plurality of openings 51, and the inner connection pads 16 and the outer connection pads 17 are respectively exposed at the bottoms of the openings 51.

[0125] S6: Please refer to Figure 23 , a first protective layer 161 is provided on the outer surface of the inner connection pad 16, a second protective layer 171 is provided on the outer surface of the outer connection pad 17, and a third protective layer 431 is provided on the outer surface of the connection block 43 to obtain the circuit board 100. The materials of the first protective layer 161, the second protective layer 171, and the third protective layer 431 can be nickel-gold alloy. The first protective layer 161, the second protective layer 171, and the third protective layer 431 all have the function of corrosion prevention.

[0126] Please refer to Figure 23 , the present application further provides a circuit board 100. The circuit board 100 includes a dielectric layer 30, connection pads (including inner connection pads 16 and outer connection pads 17), and positioning posts 31. The positioning posts 31 protrude from one side of the dielectric layer 30. The connection pads are disposed on the dielectric layer 30 and are used for electrically connecting the chip 201 and the main board 301 (refer to Figure 24 ).

[0127] Please refer to Figure 24 , the present application further provides a packaged chip 200. The packaged chip 200 includes a chip 201, a package body 202, solder balls 203, and the circuit board 100. The chip 201 is disposed on the side of the dielectric layer 30 where no positioning posts 31 are provided. The package body 202 covers the chip 201. The chip 201 is electrically connected to the outer connection pads 17, and the solder balls 203 are electrically connected to the inner connection pads 16.

[0128] Please refer to Figure 25 , the present application further provides a packaging structure 300. The packaging structure 300 includes a main board 301 and the packaged chip 200. The main board 301 includes a body portion 302 and a plurality of connection portions 303. The body portion 302 is provided with positioning holes 3011 therethrough. The positioning posts 31 are received in the positioning holes 3011, and the connection portions 303 are electrically connected to the solder balls 203.

[0129] In this embodiment, the main board 301 further includes a plurality of conductive pads 304. The conductive pads 304 are disposed on the side of the body portion 302 facing away from the chip 201. The conductive pads 304 are disposed around the positioning holes 3011. The connection block 43 is exposed from the positioning holes 3011, and the connection block 43 is soldered to the conductive pads 304.

[0130] Compared with the prior art, the circuit board 100 provided by the present application is provided with positioning posts 31 on one side of the dielectric layer 30, and the positioning posts 31 can be used to insert into the positioning holes 3011 of the main board 301 (see Figure 25 ), thereby improving the connection strength between the circuit board 100 and the main board 301 and reducing the risk of the circuit board 100 falling off or being misaligned.

[0131] In addition, those skilled in the art can also make other changes within the spirit of the present application. Of course, these changes made in accordance with the spirit of the present application should be included in the scope claimed by the present application.

Claims

1. A manufacturing method of a circuit board, characterized in that, Including the steps of: Providing a carrier board, the carrier board includes a substrate layer and a peelable layer disposed on the substrate layer, the carrier board is provided with a first opening that penetrates through the peelable layer and at least part of the substrate layer; Disposing inner connection pads on the peelable layer, the inner connection pads are spaced apart on the peelable layer; Disposing a dielectric layer on the peelable layer, the dielectric layer covers the inner connection pads, and part of the dielectric layer is filled into the first opening to form positioning posts; Disposing a second opening in the dielectric layer, and the inner connection pads are exposed at the bottom of the second opening; Electroplating an outer connection pad on a side of the dielectric layer facing away from the inner connection pads, and part of the outer connection pad is filled into the second opening to form a conduction body, and the conduction body electrically connects the inner connection pads and the outer connection pads; and Removing the peelable layer and the substrate layer to obtain the circuit board.

2. The manufacturing method according to claim 1, characterized in that, The dielectric layer has the same material as the substrate layer, and the step of "removing the peelable layer and the substrate layer" includes: Removing part of the substrate layer around the positioning posts by means of mechanical drilling or laser irradiation; and Tearing off the peelable layer to separate another part of the substrate layer from the dielectric layer.

3. The manufacturing method according to claim 1, characterized in that, The carrier board further includes a first copper-clad layer, the first copper-clad layer is disposed on a side of the substrate layer facing away from the dielectric layer, the positioning posts are connected to the first copper-clad layer, and the manufacturing method further includes the steps of: Etching the first copper-clad layer to form a plurality of connection blocks, and the connection blocks are disposed on the positioning posts.

4. The manufacturing method according to claim 3, characterized in that, The carrier board further includes a second copper-clad layer, the second copper-clad layer is disposed between the dielectric layer and the substrate layer, and before the step of "removing the peelable layer and the substrate layer", it further includes: Removing part of the second copper-clad layer around the positioning posts; and Removing another part of the second copper-clad layer.

5. The manufacturing method according to claim 1, characterized in that, It further includes the steps of: Disposing solder mask layers on opposite sides of the dielectric layer, the solder mask layers are provided with a plurality of openings, and the connection pads are exposed at the bottoms of the openings.

6. The manufacturing method according to claim 1, characterized in that, It further includes the steps of: Disposing a protective layer on the outer surfaces of the connection pads.

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