Chip optimization design method, chip, electronic equipment and storage medium

Abstract

The application provides a chip optimization design method, a chip, an electronic device and a computer readable storage medium. The chip optimization design method comprises: determining a register combination with similarity according to register array information of a chip; wherein the register combination with similarity comprises a plurality of registers, and the plurality of registers have the same fan-in information and / or fan-out information; and optimizing design of a register array of the chip according to the register combination with similarity. In this way, the problem that a large amount of manpower is consumed and a long time is consumed when the chip is currently optimized and designed can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a chip optimization design method, a chip, an electronic device and a computer readable storage medium. BACKGROUND

[0002] With the development of various fields, the complexity of chip design has also increased significantly, and the requirements for chips are also increasingly developing towards small size, low power consumption and high performance. In the chip design process, when performing layout design on the logic circuit in a high-performance chip, random logic is usually used to combine the logic elements in the high-performance chip to achieve the required logic function.

[0003] In the chip design process, after completing the preliminary layout planning, the logic circuit in the chip needs to be optimized. When optimizing the chip, clock tree synthesis and layout routing optimization of the chip are mainly performed by combining the analysis results of the EDA tool with manual work. However, since the register array in the high-performance chip is relatively large, a large amount of manpower and a long time are required for optimization design by using the above method. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a chip optimization design method, a chip, an electronic device and a computer readable storage medium to improve the problem that a large amount of manpower and a long time are required for optimization design of the chip.

[0005] In a first aspect, the present application provides a chip optimization design method, comprising:

[0006] determining a register combination with similarity according to the register array information of the chip; wherein the register combination with similarity includes a plurality of registers, and the plurality of registers have the same fan-in information and / or fan-out information; and performing optimization design on the register array of the chip according to the register combination with similarity.

[0007] In the embodiments of the present application, before optimization design, the register combination with similarity is determined according to the register array information of the chip. Since each register in the register combination with similarity has the same fan-in information and / or fan-out information, when performing optimization design, the logical relationship between each register in the register combination with similarity is considered, and instead of optimizing a single register, each register in the register combination with similarity is simultaneously optimized, thereby improving the problem that a large amount of manpower and a long time are required for optimization design of the chip.

[0008] In an optional implementation, the determining the register combination with the similarity according to the register array information of the chip comprises: determining timing information of each register according to the register array information of the chip; wherein the timing information of each register is used to represent the timing relationship between the register and other registers; and comparing the timing information of each register, a plurality of registers with the same timing information are taken as the register combination with the similarity.

[0009] In the embodiments of the present application, since the timing information of the register can reflect the fan-in information and the fan-out information of the register, by comparing the timing information of each register, the register combination with the similarity can be quickly and accurately determined.

[0010] In an optional implementation, the determining the register combination with the similarity according to the register array information of the chip comprises: determining logic path information of each register according to the register array information of the chip; wherein the logic path information of each register is used to represent the path connection relationship between the register and other registers; and comparing the logic path information of each register, a plurality of registers with the same logic path information are taken as the register combination with the similarity.

[0011] In the embodiments of the present application, since the logic path information of the register can reflect the fan-in information and the fan-out information of the register, by comparing the logic path information of each register, the register combination with the similarity can be quickly and accurately determined.

[0012] In an optional implementation, the determining the register combination with the similarity according to the register array information of the chip comprises: determining the name of each register according to the register array information of the chip; and comparing the name of each register, a plurality of registers named based on the same naming rule are taken as the register combination with the similarity.

[0013] In the embodiments of the present application, since in the chip design process, the same naming rule is usually used for naming the registers with similar functions, by comparing the name of each register, the register combination with the similarity can be quickly and accurately determined.

[0014] In an optional implementation, the optimizing and designing the register array of the chip according to the register combination with the similarity comprises: performing clock tree synthesis on the register array of the chip according to the register combination with the similarity.

[0015] In the embodiments of the present application, when performing clock tree synthesis, the delay difference on each clock path corresponding to each register in the register combination with similarity is adjusted simultaneously, so that the efficiency is improved and the timing converges quickly.

[0016] In an optional embodiment, the optimizing design of the register array of the chip according to the register combination with similarity comprises: performing layout and routing optimization of the register array of the chip according to the register combination with similarity.

[0017] In the embodiments of the present application, when performing layout and routing optimization, the layout and routing optimization is performed on each register in the register combination with similarity simultaneously, and each register in the register combination with similarity is physically laid out together, so as to reduce the wire length and the timing delay. Compared with performing layout and routing optimization on each independent register separately, the above-mentioned method can improve the efficiency and save engineering resources.

[0018] In an optional embodiment, before the register combination with similarity is determined according to the register array information of the chip, the method further comprises: obtaining the register array information of the chip from the description code of the chip.

[0019] In a second aspect, the present application provides a chip, comprising: a register array, the register array comprising a plurality of register groups with similarity, and the plurality of registers in the register group with similarity are physically laid out together.

[0020] In a third aspect, the present application provides a chip optimization design device, comprising: a determination module configured to determine a register combination with similarity according to register array information of a chip; wherein the register combination with similarity comprises a plurality of registers, and the plurality of registers have the same fan-in information and / or fan-out information; and an optimization module configured to optimize design of a register array of the chip according to the register combination with similarity.

[0021] In a fourth aspect, the present application provides an electronic device, comprising: a memory and a processor, the processor being connected with the memory; the memory is configured to store a program; and the processor is configured to call the program stored in the memory to execute the method in any one of the preceding embodiments.

[0022] In a fifth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program is run by a processor to execute the method in any one of the preceding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 A flow chart of a chip optimization design method provided by the embodiments of the present application;

[0025] Figure 2 A structural block diagram of a chip optimization design device provided by the embodiments of the present application;

[0026] Figure 3 A structural schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below in combination with the drawings in the embodiments of the present application.

[0028] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the relationship terms such as “first”, “second” and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of another identical element in the process, method, article or device including the element.

[0029] In view of the problem that a large amount of manpower is consumed and a long time is taken in the optimization design of a chip at present, the reason is that the register array in a high-performance chip is relatively large, contains thousands of registers, and there is a complex logical relationship between the registers and an influence between each other. When the chip optimization design is performed by manual work combined with the analysis result of an EDA tool, usually, a round of optimization is performed on the registers with problems, then the EDA tool is used to perform analysis again, and according to the analysis result, another round of optimization is performed on the registers with problems, and the above process is repeatedly cycled until the optimization is completed.

[0030] In order to improve the problem that a large amount of manpower and a long time are consumed in the current chip optimization design, an innovative chip optimization design method is provided in the embodiments of the present application, and the chip optimization design method provided in the embodiments of the present application will be described below. Figure 1 The chip optimization design method provided in the embodiments of the present application is described.

[0031] S1: Determine a register combination with similarity according to register array information of a chip.

[0032] In actual chip optimization design, the register array of a high-performance chip is very large, and if the high-performance chip is optimized according to the existing optimization design method, it is necessary to analyze multiple times by using an EDA tool, thereby consuming a large amount of manpower and a long time. Therefore, before optimization design, the register combination with similarity is determined according to the register array information of the high-performance chip. Since each register in the register combination with similarity has the same fan-in information and / or fan-out information, in subsequent optimization design, the logical relationship between each register in the register combination with similarity is considered, and instead of optimizing a single register, each register in the register combination with similarity is simultaneously optimized, thereby improving the problem that a large amount of manpower and a long time are consumed in the current chip optimization design.

[0033] In the embodiments of the present application, one or more register combinations with similarity can be determined according to the register array information of a chip, each register combination with similarity includes multiple registers, and each register in each register combination with similarity has the same fan-in information and / or fan-out information.

[0034] In some embodiments, multiple registers with the same fan-in information are taken as one register combination with similarity. In other embodiments, multiple registers with the same fan-out information are taken as one register combination with similarity. In other embodiments, multiple registers with the same fan-in information and the same fan-out information are taken as one register combination with similarity.

[0035] For example, the data output from the data output pin PIN (Q end) of the register 1 to the register 10 is sent to the data input pin PIN (D end) of the register A. At the same time, the data output from the data output pin PIN (Q end) of the register 1 to the register 10 is sent to the data input pin PIN (D end) of the register B, which indicates that the register A and the register B have the same fan-in information, and the register A and the register B are taken as one register combination with similarity.

[0036] For example, the data outputted from the data output pin PIN (Q end) of register C is sent to the data input pin PIN (D end) of register 1 to register 10. At the same time, the data outputted from the data output pin PIN (Q end) of register D is sent to the data input pin PIN (D end) of register 1 to register 10, which indicates that register C and register D have the same fan-out information, and register C and register D are combined as a register group with similarity.

[0037] Before the step S1, the chip optimization design method provided by the embodiment of the present application further includes: obtaining the register array information of the chip from the description code of the chip.

[0038] The register array information of the chip can be obtained from various description codes used to describe the connection relationship between the circuit elements in the chip. The description codes include, but are not limited to, RTL (Register Transfer Level) code, SDRL (System Register Deception Language) code, RAL (Register Abstraction Language) code or CC (Connectivity Check) code, netlist, etc. Among them, the several description codes in the above examples are common description codes in chip design, which will not be described in detail here.

[0039] The register array information of the chip can include the timing information of each register in the register array, the logic path information of each register, and the name of each register, i.e., the fan-in information and the fan-out information of each register in the chip can be determined according to the timing information of each register or the logic path information of each register or the name of each register, and then the registers with the same fan-in information and / or fan-out information are combined as a register group with similarity.

[0040] As an optional implementation, the specific process of the above S1 can be: determining the timing information of each register according to the register array information of the chip; wherein the timing information of each register is used to represent the timing relationship between the register and other registers; comparing the timing information of each register, and combining the multiple registers with the same timing information as a register group with similarity.

[0041] In the embodiments of the present application, the timing information of a register can reflect the fan-in information and the fan-out information of the register, and the fan-in information and the fan-out information between each register and other registers can be determined by analyzing the timing relationship between each register and other registers. Therefore, when determining the register combination with similarity, the registers with the same timing information are taken as the register combination with similarity by comparing the timing information of each register.

[0042] As another optional implementation, the specific process of S1 can be: determining the logical path information of each register according to the register array information of the chip; wherein the logical path information of each register is used to represent the path connection relationship between the register and other registers; and comparing the logical path information of each register, and taking the registers with the same logical path information as the register combination with similarity.

[0043] In the embodiments of the present application, the logical path information of each register is used to represent the path connection relationship between the register and other registers, and the path connection relationship of the register can reflect the fan-in information and the fan-out information of the register. The fan-in information and the fan-out information between each register and other registers can be determined by analyzing the path connection relationship between each register and other registers. Therefore, when determining the register combination with similarity, the registers with the same logical path information are taken as the register combination with similarity by comparing the logical path information of each register.

[0044] As another optional implementation, the specific process of S1 can be: determining the name of each register according to the register array information of the chip; and comparing the name of each register, and taking the registers named based on the same naming rule as the register combination with similarity.

[0045] In the chip design flow, when naming registers, the same naming rule is usually used for registers with similar functions. For example, the data output by the output data output pin PIN (Q terminal) of register A and register B is sent to the data input pin PIN (D terminal) of register 1 to register 10, register A is named Reg-0-0, and register B is named Reg-0-1. The data output by the output data output pin PIN (Q terminal) of register C and register D is sent to the data input pin PIN (D terminal) of register 11 to register 20, register C is named Reg-1-0, and register D is named Reg-1-1. Register A and register B have the same naming rule and the same fanout information, and register A and register B are combined as a register combination with similarity. Similarly, register C and register D have the same naming rule and the same fanout information, and register C and register D are combined as a register combination with similarity.

[0046] S2: optimizing the register array of the chip according to the register combination with similarity.

[0047] After one or more register combinations with similarity are determined, the register array of the chip can be optimized according to the register combination with similarity. The current optimization method for the chip can include clock tree synthesis and layout routing optimization.

[0048] As an optional implementation, the specific process of S2 can be: performing clock tree synthesis on the register array of the chip according to the register combination with similarity.

[0049] In the embodiments of the present application, clock tree synthesis is performed to reduce the delay difference on each clock path to achieve timing convergence. When performing clock tree synthesis, the delay difference on each clock path corresponding to each register in the register combination with similarity is adjusted at the same time, which improves the efficiency and achieves fast timing convergence.

[0050] As an optional implementation, the specific process of S2 can be: performing layout routing optimization on the register array of the chip according to the register combination with similarity.

[0051] In the embodiments of the present application, the layout and routing optimization is performed to ensure that the key parts in the logic are as close as possible and the wire length is as short as possible, so as to reduce the timing delay. Since each register in the register combination with similarity has the same path connection relationship, when the layout and routing optimization is performed, the layout and routing optimization is simultaneously performed on each register in the register combination with similarity, so that each register in the register combination with similarity is physically laid out together, thereby reducing the wire length and the timing delay. Compared with the layout and routing optimization performed on individual registers, the above-mentioned manner can improve the efficiency and save engineering resources.

[0052] Based on the same inventive concept, the embodiments of the present application also provide a chip, which is optimized by using the chip optimization design method described above, and the chip includes a register array, and the register array includes a plurality of register groups with similarity, and the plurality of registers in the register group with similarity are physically laid out together.

[0053] In addition, the embodiments of the present application also provide a chip optimization design apparatus 100, as shown in Figure 2 The chip optimization design apparatus 100 includes a determination module 101 and an optimization module 102.

[0054] The determination module 101 is configured to determine a register combination with similarity according to register array information of a chip, wherein the register combination with similarity includes a plurality of registers, and the plurality of registers have the same fan-in information and / or fan-out information.

[0055] The optimization module 103 is configured to perform optimization design on the register array of the chip according to the register combination with similarity.

[0056] Optionally, the determination module 101 is configured to determine timing information of each register according to the register array information of the chip, wherein the timing information of each register is used to represent a timing relationship between the register and other registers, and a plurality of registers with the same timing information are taken as the register combination with similarity by comparing the timing information of each register.

[0057] Optionally, the determination module 101 is configured to determine logic path information of each register according to the register array information of the chip, wherein the logic path information of each register is used to represent a path connection relationship between the register and other registers, and a plurality of registers with the same logic path information are taken as the register combination with similarity by comparing the logic path information of each register.

[0058] Optionally, the determining module 101 is configured to determine the name of each register according to the register array information of the chip; and combine the registers named based on the same naming rule as the register combination with the similarity by comparing the name of each register.

[0059] Optionally, the optimizing module 101 is configured to perform clock tree synthesis on the register array of the chip according to the register combination with the similarity.

[0060] Optionally, the optimizing module 101 is configured to perform layout and routing optimization on the register array of the chip according to the register combination with the similarity.

[0061] Optionally, the determining module 101 is further configured to obtain the register array information of the chip from the description code of the chip.

[0062] The chip optimization design apparatus 100 provided by the embodiment of the present application has the same implementation principle and technical effects as the foregoing method embodiment. For brevity, the part not mentioned in the apparatus embodiment can be referred to the corresponding content in the foregoing method embodiment.

[0063] As shown in Figure 3 Figure 3 A structure block diagram of an electronic device 200 is shown. The electronic device 200 includes a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0064] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to realize the transmission or interaction of data. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to transceive data. The memory 220 is used to store computer programs, such as the computer program stored in the memory 220. Figure 2 ​The software function module shown in the figure is a chip optimization design apparatus 100. The chip optimization design apparatus 100 includes at least one software function module stored in the memory 220 in the form of software or firmware or solidified in an operating system (OS) of the electronic device 200. The processor 240 is configured to execute the executable modules stored in the memory 220, such as the software function module or computer program included in the chip optimization design apparatus 100. For example, the processor 240 is configured to determine a register combination with similarity according to register array information of a chip, wherein the register combination with similarity includes a plurality of registers having the same fan-in information and / or fan-out information, and to perform optimization design on the register array of the chip according to the register combination with similarity.

[0065] The memory 220 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), and the like.

[0066] The processor 240 can be an integrated circuit chip with a processing capability of signals. The processor can be a general processor including a central processing unit (CPU), a network processor (NP), and the like, and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor can be a microprocessor or the processor 240 can also be any conventional processor or the like.

[0067] The electronic device 200 includes, but is not limited to, a mobile phone, a tablet, a computer, a server, and the like.

[0068] The application further provides a nonvolatile computer readable storage medium (hereinafter referred to as a storage medium) having a computer program stored thereon, and the computer program is run by a computer such as the electronic device 200 to execute the chip optimization design method shown above.

[0069] It should be noted that each of the embodiments in the present specification adopts a progressive manner for description, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0070] In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. The apparatus embodiments described above are only schematic, for example, the division of the units is only a logical function division, and other division manners can be used in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, and can be electrical, mechanical or other forms.

[0071] In addition, the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the present embodiment.

[0072] Furthermore, each functional module in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0073] It should be noted that, if the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or in the form of a part or the technical solutions of the present application that make contributions to the prior art. The computer software product is stored in a storage medium, includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0074] In this document, relational terms such as first and second and the like can merely be used to distinguish one entity or action from another, without necessarily requiring or implying any such actual relationship or order between or among the entities or actions.

[0075] The above only describes the embodiments of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of chip optimization design, characterized by, The method comprises the following steps: determining a register combination with similarity according to register array information of a chip; wherein the register combination with similarity comprises a plurality of registers with same fan-in information and fan-out information; optimizing design of a register array of the chip according to the register combination with similarity, comprising: clock tree synthesis of the register array of the chip according to the register combination with similarity, wherein when the clock tree synthesis is performed, the delay difference on each clock path corresponding to each register in the register combination with similarity is adjusted simultaneously.

2. The method of claim 1, wherein, The step of determining the register combination with similarity according to the register array information of the chip comprises: determining timing information of each register according to the register array information of the chip; wherein the timing information of each register is used to represent the timing relationship between the register and other registers; comparing the timing information of each register, and taking a plurality of registers with same timing information as the register combination with similarity.

3. The method of claim 1, wherein, The step of determining the register combination with similarity according to the register array information of the chip comprises: determining logic path information of each register according to the register array information of the chip; wherein the logic path information of each register is used to represent the path connection relationship between the register and other registers; comparing the logic path information of each register, and taking a plurality of registers with same logic path information as the register combination with similarity.

4. The method of claim 1, wherein, The step of determining the register combination with similarity according to the register array information of the chip comprises: determining the name of each register according to the register array information of the chip; comparing the name of each register, and taking a plurality of registers named based on same naming rules as the register combination with similarity.

5. The method of claim 1, wherein, The step of optimizing design of the register array of the chip according to the register combination with similarity further comprises: performing layout and routing optimization of the register array of the chip according to the register combination with similarity.

6. The method of claim 1, wherein, Before the step of determining the register combination with similarity according to the register array information of the chip, the method further comprises: obtaining the register array information of the chip from the description code of the chip.

7. A chip, characterized by The method comprises the following steps: a register array comprising a plurality of register combinations with similarity, wherein the plurality of registers in the register combination with similarity are physically arranged together; wherein the plurality of registers have same fan-in information and fan-out information.

8. An electronic device, comprising: The method comprises the following steps: a memory and a processor connected with the memory; the memory is used to store a program; the processor is used to call the program stored in the memory to execute the method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, A computer program is stored on the computer readable medium, and when the computer program is executed by a processor, the method according to any one of claims 1-6 is executed.

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