A 10T computing cell and system for single-bit in-memory computing

Abstract

The application relates to a 10T computing unit and system for single-bit in-memory computing. The 10T computing unit comprises a storage circuit and a computing circuit; the storage circuit is connected with the computing circuit; the computing circuit performs single-bit weight operation based on the weight stored in the storage circuit. The application adopts the computing circuit to perform single-bit weight operation based on the weight stored in the storage circuit, so that the write interference problem can be avoided, and the computing speed is accelerated.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a 10T computing unit and system for single-bit in-memory computing. Background Technology

[0002] Deep convolutional neural networks (DCNNs) continue to demonstrate improved inference accuracy, and deep learning is shifting towards edge computing. This development is driving the work on low-resource machine learning algorithms and their acceleration hardware. The most common operation in DCNNs is multiplication and accumulation (MAC), which controls power and latency. MAC operations are highly regular and parallel, making them well-suited for hardware acceleration. However, memory access demands severely limit the energy efficiency of traditional digital accelerators. Therefore, in-memory computing (CIM) is becoming increasingly attractive for accelerating DCNNs.

[0003] Currently, in-memory computing designs can be categorized by storage medium into SRAM-based designs and designs based on novel non-volatile memories. While SRAM-based designs are technically mature, they also have certain drawbacks. For example, they may cause accidental writes to memory cells during computation, and some voltage domain computations can take a long time. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, this invention provides a 10T computing unit and system for single-bit in-memory computation.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A 10T computing unit for single-bit in-memory computation includes: a storage circuit and a computing circuit;

[0007] The storage circuit is connected to the computing circuit; the computing circuit performs single-bit weight calculations based on the weights stored in the storage circuit.

[0008] Preferably, the storage circuit is a 6T storage unit.

[0009] Preferably, the computing circuit includes a first control module, a second control module, a read line, a first input terminal, and a second input terminal;

[0010] The first port of the first control module and the first port of the second control module are both connected to the weight storage point in the 6T storage unit; the second port of the first control module is connected to the first input terminal; the second port of the second control module is connected to the second input terminal; the third port of the first control module is connected to the third port of the second control module; the fourth port of the first control module and the fourth port of the second control module are both connected to the read bit line.

[0011] Preferably, the first control module includes: a PMOS transistor and a first NMOS transistor;

[0012] The gate of the PMOS transistor is connected to the weighted storage point as the first port of the first control module; the drain of the PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is connected to the first input terminal as the second port of the first control module; the gate of the first NMOS transistor is connected to the third port of the second control module as the third port of the first control module; and the source of the PMOS transistor is connected to the read bit line as the fourth port of the first control module.

[0013] Preferably, the second control module includes: a second NMOS transistor and a third NMOS transistor;

[0014] The gate of the second NMOS transistor is connected to the weighted storage point as the first port of the second control module; the source of the second NMOS transistor is connected to the read bit line as the fourth port of the second control module; the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is connected to the second input terminal as the second port of the second control module; and the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor as the third port of the second control module.

[0015] A computing system for single-bit in-memory computation includes multiple 10T computing units provided above in this invention.

[0016] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0017] The 10T computing unit and system for single-bit in-memory computation provided by this invention employs a computing circuit to perform single-bit weight calculation based on the weights stored in the storage circuit, which can avoid write interference problems while speeding up the computation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of a 10T computing unit for single-bit in-memory computation provided by the present invention;

[0020] Figure 2 This is a schematic diagram of the computing system for single-bit in-memory computation provided by the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The purpose of this invention is to provide a 10T computing unit and system for single-bit in-memory computation, which can avoid write interference problems while speeding up the computation.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1 As shown, the 10T computing unit for single-bit in-memory computation provided by the present invention includes: a storage circuit and a computing circuit.

[0025] The storage circuit is connected to the computing circuit. The computing circuit performs single-bit weight calculations based on the weights stored in the storage circuit. Preferably, the storage circuit uses a classic 6T-SRAM (i.e., 6T memory cells). In the 6T-SRAM, transistors P1 and P2 are PMOS transistors, and transistors N5, N6, N3, and N4 are NMOS transistors. The weight values ​​are stored at point Q (weight storage point). Word lines (WL), bit lines (BL), and inverted bit lines (BLB) are used to write the high and low levels of point Q.

[0026] Figure 1 Of the transistors N3, P1, and N5 on the upper left side, the source of transistor N3 is connected to the bit line BL, the gate of transistor N3 is connected to the word line WL, and the drain of transistor N3 is connected to the Q point. The source of transistor P1 is connected to the power supply VDD, the gate of transistor P1 is connected to the gate of transistor N5 below it, and the drain of transistor P1 is connected to the Q point. The drain of transistor N5 is connected to the Q point, and the source of transistor N5 is grounded (VSS). The gate of transistor N5 is connected to the gate of transistor P1, and then connected to the weighted inverse QB point.

[0027] Figure 1Of the three transistors N4, P2, and N6 at the top right, the source of transistor N4 is connected to the inverted bit line (BLB), the gate of transistor N4 is connected to the word line (WL), and the drain of transistor N4 is connected to the weighted inverted QB point. The source of transistor P2 is connected to the power supply VDD, the gate of transistor P2 is connected to the gate of transistor N6 below it, and the drain of transistor P2 is connected to the weighted inverted QB point. The drain of transistor N6 is connected to the weighted inverted QB point, and the source of transistor N6 is grounded (VSS). The gate of transistor N6 is connected to the gate of transistor P2 and then to the Q point.

[0028] To further improve the computational control effect, the computational circuit used in the present invention includes a first control module, a second control module, a read line, a first input terminal, and a second input terminal.

[0029] The first port of the first control module and the first port of the second control module are both connected to point Q in the 6T storage unit. The second port of the first control module is connected to the first input terminal. The second port of the second control module is connected to the second input terminal. The third port of the first control module is connected to the third port of the second control module. The fourth ports of both the first and second control modules are connected to the read bit line.

[0030] The first control module includes a PMOS transistor P7 and a first NMOS transistor N9.

[0031] The gate of PMOS transistor P7 is connected to the Q point as the first port of the first control module. The drain of PMOS transistor P7 is connected to the drain of the first NMOS transistor N9. The source of the first NMOS transistor N9 is connected to the first input terminal INB as the second port of the first control module. The gate of the first NMOS transistor N9 is connected to the third port of the second control module. The source of PMOS transistor P7 is connected to the read bit line as the fourth port of the first control module.

[0032] The second control module includes: a second NMOS transistor N8 and a third NMOS transistor N10.

[0033] The gate of the second NMOS transistor N8 is connected to the Q point as the first port of the second control module. The source of the second NMOS transistor N8 is connected to the read bit line as the fourth port of the second control module. The drain of the second NMOS transistor N8 is connected to the drain of the third NMOS transistor N10. The source of the third NMOS transistor N10 is connected to the second input terminal as the second port of the second control module. The gate of the third NMOS transistor N10 is connected to the gate of the first NMOS transistor N9 as the third port of the second control module.

[0034] The 10T computing circuit performs a multiplication operation between a 1-bit input (IN) and a 1-bit weight (Q). The 64-row computing unit is connected via read lines (MBL). The results of the 64 multiplication operations are accumulated on the MBL as voltages, thus completing the multiplication-accumulation operation. The specific implementation of multiplication-accumulation is as follows:

[0035] The first step is to drive the 1-bit input to the second input terminal IN and the first input terminal INB. When the input is "+1", the second input terminal IN is driven high and the first input terminal INB is driven low. When the input is "-1", the second input terminal IN is driven low and the first input terminal INB is driven high.

[0036] The second step involves pulling the column control signal CTRL high, which selects the first NMOS transistor N9 and the third NMOS transistor N10. At this time, the Q point of the memory cell is connected to the gate of the PMOS transistor P7 and the second NMOS transistor N8 to control the on / off state of either PMOS transistor P7 or the second NMOS transistor N8.

[0037] When the weight value is "+1", point Q is high, the second NMOS transistor N8 is selected, and the second input terminal IN is connected to the read bit line MBL. When the weight value is "-1", point Q is low, the PMOS transistor P7 is selected, and the first input terminal INB is connected to MBL. When either the second input terminal IN or the first input terminal INB is high, the voltage on the read bit line MBL is pulled high; when either the second input terminal IN or the first input terminal INB is low, the read bit line MBL is pulled low. This completes the multiplication operation of a single bit input and a single bit weight.

[0038] In addition, the present invention also provides a computing system for single-bit in-memory computation, the system comprising multiple 10T computing units provided above by the present invention.

[0039] Figure 2 The diagram shows a column of 10T computing units, each column comprising 64 rows. The signal CTRL controls the computation of an entire column of 10T computing units. The 64 single-bit inputs and 64 weights of a column are multiplied and then accumulated. The accumulated result is reflected as a voltage on the read line MBL. As explained above, the multiplication result of a 10T computing unit pulls the read line MBL up or down. Therefore, the multiplication result of a column of 64 rows pulls the same read line MBL up or down, thus completing the accumulation. The final stable voltage on the read line MBL is the multiplication and accumulation result of a column.

[0040] Once the column control signal CTRL initiates the calculation, the 10T computing unit in one column pulls up and down the read bit line MBL. Because this calculation method does not require pre-charging of the bit line before calculation begins, and the voltage pull-up and pull-down of the transistors can quickly stabilize, this structure can achieve a relatively fast calculation speed.

[0041] Based on the above description of the present invention, its advantage is that it separates storage from computation, avoiding read interference to the storage unit during computation. Furthermore, the computation employs a pull-up / pull-down structure on the input read bit line (MBL), accelerating the computation speed.

[0042] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0043] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A 10T computing cell for single-bit in-memory computing, characterized in that, include: Storage circuits and computing circuits; The storage circuit is a 6T storage unit; The storage circuit is connected to the computing circuit; The calculation circuit performs single-bit weight calculations based on the weights stored in the storage circuit; The computing circuit includes a first control module, a second control module, a read line, a first input terminal, and a second input terminal; Both the first port of the first control module and the first port of the second control module are connected to the weight storage point in the 6T storage unit; The second port of the first control module is connected to the first input terminal; the second port of the second control module is connected to the second input terminal; the third port of the first control module is connected to the third port of the second control module. The fourth port of the first control module and the fourth port of the second control module are both connected to the read bit line; The first control module includes: a PMOS transistor and a first NMOS transistor; The gate of the PMOS transistor is connected to the weighted storage point as the first port of the first control module; the drain of the PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is connected to the first input terminal as the second port of the first control module; the gate of the first NMOS transistor is connected to the third port of the second control module as the third port of the first control module; and the source of the PMOS transistor is connected to the read bit line as the fourth port of the first control module.

2. The 10T computing cell for single-bit in-memory computation of claim 1, wherein, The second control module includes: a second NMOS transistor and a third NMOS transistor; The gate of the second NMOS transistor is connected to the weighted storage point as the first port of the second control module; the source of the second NMOS transistor is connected to the read bit line as the fourth port of the second control module; the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is connected to the second input terminal as the second port of the second control module; and the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor as the third port of the second control module.

3. A computing system for single-bit in-memory computation, the computing system comprising: It includes multiple 10T computing units as described in any one of claims 1-2.

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