Electrostatic protection device

Abstract

The application provides an electrostatic protection device. The electrostatic protection device comprises an N-type epitaxial region, an N-type buffer region and a P-type body region; the N-type buffer region and the P-type body region are respectively embedded on two sides of an upper surface of the N-type epitaxial region, a metal anode arranged on the N-type buffer region is connected with a circuit interface, and a metal cathode is arranged on the N-type epitaxial region and / or the P-type body region; a first N+ region and a first P+ region are embedded on an upper surface of the N-type buffer region, a second P+ region and a second N+ region are embedded on an upper surface between the N-type buffer region and the P-type body region of the N-type epitaxial region, and a third N+ region and a third P+ region are embedded on an upper surface of the P-type body region; a thin gate oxide layer is arranged between the second N+ region and the third N+ region, and the thin gate oxide layer is arranged on a connection between the upper surfaces of the N-type epitaxial region and the P-type body region; a gate electrode is further arranged on the thin gate oxide layer, and the second P+ region, the second N+ region and the gate electrode are electrically connected. The application can reduce the trigger voltage of the electrostatic protection device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and in particular to a static electricity protection device. BACKGROUND

[0002] Electrostatic is a common phenomenon in daily life, and integrated circuits may accumulate electric charges in the process of production, packaging, testing, storage and transportation, and thus are damaged by electro-static discharge (ESD).

[0003] With the continuous reduction of the process node of integrated circuits, the gate oxide layer of the transistor becomes thinner. If no special ESD protection design is performed, the chip is extremely easy to be damaged by ESD high-voltage and large-current impact, and thus thermal breakdown, gate oxide breakdown, and metal line melting failure may occur. The SCR-LDMOS is widely used as an ESD protection device in power management chips because of its strong robustness and ability to discharge ESD large current. However, the trigger voltage of the existing ESD protection device is high, that is, the current discharge function of the ESD protection device is triggered only when the electrostatic voltage reaches a certain height. The high trigger voltage may cause the electrostatic discharge to be not discharged in time, thereby causing damage to the integrated circuit chip.

[0004] Therefore, there is a need for a static electricity protection device with a lower trigger voltage. SUMMARY

[0005] The present application provides a static electricity protection device to solve the technical problem of the existing static electricity protection device with a high trigger voltage, which easily causes damage to the circuit.

[0006] In a first aspect, the present application provides a static electricity protection device, comprising: an N-type epitaxial region, an N-type buffer region and a P-type body region;

[0007] The N-type buffer region and the P-type body region are respectively embedded on both sides of the upper surface of the N-type epitaxial region, a metal anode provided on the N-type buffer region is connected to the circuit interface, and a metal cathode is provided on the N-type epitaxial region and / or the P-type body region;

[0008] The upper surface of the N-type buffer region is embedded with a first N+ region and a first P+ region, the N-type epitaxial region is located on the upper surface between the N-type buffer region and the P-type body region, and is embedded with a second P+ region and a second N+ region, and the upper surface of the P-type body region is embedded with a third N+ region and a third P+ region;

[0009] A thin gate oxide layer is arranged between the second N+ region and the third N+ region, and is located on the junction of the N-type epitaxial region and the upper surface of the P-type body region; a gate electrode is further arranged on the thin gate oxide layer, and the second P+ region, the second N+ region and the gate electrode are electrically connected.

[0010] In a possible implementation, the upper surface of the N-type buffer region is further embedded with a first isolation region, and the first isolation region is used to isolate the first N+ region and the edge of the electrostatic protection device.

[0011] The upper surface between the first P+ region and the second P+ region is further embedded with a second isolation region, and the second isolation region is used to isolate the first P+ region and the second P+ region.

[0012] The upper surface between the second P+ region and the second N+ region is further embedded with a third isolation region, and the third isolation region is used to isolate the second P+ region and the second N+ region.

[0013] The upper surface between the third N+ region and the third P+ region is further embedded with a fourth isolation region, and the fourth isolation region is used to isolate the third N+ region and the third P+ region.

[0014] The upper surface of the P-type body region is further embedded with a fifth isolation region, and the fifth isolation region is used to isolate the third P+ region and the edge of the electrostatic protection device.

[0015] In a possible implementation, the first N+ region and the first P+ region are connected through a first metal wire, and a metal anode is arranged on the first metal wire, and the metal anode is connected with the circuit interface.

[0016] Alternatively, the first N+ region and the first P+ region are connected through a first metal rod group, and a metal anode is arranged on the first metal rod group, and the metal anode is connected with the circuit interface.

[0017] In a possible implementation, the first metal rod group includes a first metal rod, a second metal rod and an eighth metal rod, and a metal anode is arranged on the eighth metal rod.

[0018] The first metal rod is connected with the first N+ region and the eighth metal rod respectively, and the second metal rod is connected with the first P+ region and the eighth metal rod respectively.

[0019] In a possible implementation, the second P+ region, the second N+ region and the gate electrode are connected through a third metal wire.

[0020] Alternatively, the second P+ region, the second N+ region and the gate electrode are connected through a third metal rod group.

[0021] In a possible implementation, a first metal cathode is arranged on the third metal wire, or a first metal cathode is arranged on the third metal rod group.

[0022] In a possible implementation, the second metal rod group includes a third metal rod, a fourth metal rod, a fifth metal rod, and a ninth metal rod, and a first metal cathode is arranged on the ninth metal rod.

[0023] The third metal rod is connected with the second P+ region and the ninth metal rod respectively, the fourth metal rod is connected with the second N+ region and the ninth metal rod respectively, and the fifth metal rod is connected with the gate and the ninth metal rod respectively.

[0024] In a possible implementation, the third N+ region and the third P+ region are connected through a second metal wire.

[0025] Alternatively, the third N+ region and the third P+ region are connected through a second metal rod group.

[0026] In a possible implementation, a second metal cathode is arranged on the second metal wire, and the second metal cathode is arranged to be grounded.

[0027] Alternatively, a second metal cathode is arranged on the second metal rod group, and the second metal cathode is arranged to be grounded.

[0028] In a possible implementation, the third metal rod group includes a sixth metal rod, a seventh metal rod, and a tenth metal rod, and a second metal cathode is arranged on the tenth metal rod.

[0029] The sixth metal rod is connected with the third N+ region and the tenth metal rod respectively, and the seventh metal rod is connected with the third P+ region and the tenth metal rod respectively.

[0030] In a possible implementation, the gate is consistent in size with the thin gate oxide layer and completely covers the thin gate oxide layer.

[0031] In a possible implementation, the electrostatic protection device further includes a P-type substrate layer and a buried oxide layer.

[0032] The buried oxide layer is arranged on the upper surface of the P-type substrate layer, and the N-type epitaxial region is arranged on the upper surface of the buried oxide layer.

[0033] The electrostatic protection device provided by the application can additionally add a second P+ region and a second N+ region on the upper surface of the N-type buffer region between the N-type epitaxial region and the P-type body region, and electrically connect the second P+ region, the second N+ region and the gate electrode on the junction of the upper surface of the N-type epitaxial region and the P-type body region. Through such a setting, after the metal anode provided on the N-type buffer region is connected to static electricity through a circuit interface, the static electricity enters the first P+ region, and the N-type buffer region continuously migrates holes to the second P+ region of the N-type epitaxial region, so that the second P+ region generates positive charges. Since the second P+ region, the second N+ region and the gate electrode are electrically connected, the gate electrode is continuously coupled with a positive voltage, so that the second P+ region and the gate electrode form equal positive voltages; and the gate electrode is covered on the thin gate oxide layer as a medium, so that the thin gate oxide layer also forms a positive voltage. Due to the attraction of the charges, the positive voltage of the thin gate oxide layer causes the surface of the P-type body region below to form an aggregation of minority carrier electrons, thereby gradually forming an inversion layer, together with the N-type epitaxial layer, to form an electron transport channel, so that the P-type body region with a negative voltage and the N-type epitaxial region with a positive voltage generate a charge flow, so that the static electricity can flow out through the first P+ region, the N-type buffer region, the N-type epitaxial region, the second P+ region, the gate electrode, the thin gate oxide layer, and finally through the metal cathode provided on the N-type epitaxial region and / or the P-type body region, to achieve the purpose of current discharge. In addition, during the current discharge process, the charge flow between the P-type body region and the N-type epitaxial region can also continuously break down the interface between the P-type body region and the N-type epitaxial region, thereby opening the main current discharge channel of the protection device: the first P+ region, the N-type buffer region, the N-type epitaxial region, the P-type body region and the third N+ region. The first P+ region, the N-type buffer region, the N-type epitaxial region, the second P+ region, the gate electrode and the thin gate oxide layer can form a PNP1-C structure, the second N+ region, the N-type epitaxial region, the P-type body region, the third N+ region, the gate electrode and the thin gate oxide layer can form an NMOS structure, and the current discharge channel formed by the PNP1-C structure and the NMOS structure can serve as an auxiliary discharge channel of the main current discharge channel of the protection device. Through such a setting, after the metal anode is connected to static electricity through a circuit interface, a smaller static voltage can trigger the opening of the PNP1-C structure, and discharge the current by using the NMOS structure, thereby avoiding the damage of the integrated circuit caused by the failure of the main current discharge channel with a high trigger voltage to open when the static voltage is small, and improving the safety of the circuit. In addition, when the current is discharged through the PNP1-C-NMOS current discharge channel, the interface between the P-type body region and the N-type epitaxial region can also be continuously broken down, thereby opening the main current discharge channel of the protection device, avoiding the damage of the integrated circuit caused by the failure of the static discharge in time when the static voltage is high, and further improving the safety of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0035] Figure 1 A structure diagram of a static protection device in the prior art;

[0036] Figure 2 A structure diagram of a static protection device in an embodiment of the application.

[0037] Reference signs: 10, P-type substrate layer; 11, buried oxygen layer; 12, N-type epitaxial region; 13, N-type buffer region; 14, P-type body region; 15, first N+ region; 16, first P+ region; 17, second P+ region; 18, second N+ region; 19, third N+ region; 20, third P+ region; 21, first isolation region; 22, second isolation region; 23, third isolation region; 24, fourth isolation region; 25, fifth isolation region; A, first metal rod group; B, second metal rod group; C, third metal rod group; 26, first metal rod; 27, second metal rod; 28, third metal rod; 29, fourth metal rod; 30, fifth metal rod; 31, sixth metal rod; 32, seventh metal rod; 33, thin gate oxide layer; 34, gate; 35, eighth metal rod; 36, metal anode; 37, ninth metal rod; 38, first metal cathode; 39, tenth metal rod; 40, second metal cathode.

[0038] The specific embodiments of the application have been shown by the above-described drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the inventive concept in any way, but are merely to illustrate specific embodiments of the application to those skilled in the art. DETAILED DESCRIPTION

[0039] The exemplary embodiments will be described in detail herein below with reference to the drawings. In the following description, the same drawings reference numerals are used to refer to elements having the same or similar functions. The embodiments described in the following exemplary embodiments are not representative of all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application, as detailed in the appended claims.

[0040] It should be noted that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or indirectly on or connected to the other element by way of one or more other elements.

[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0042] In addition, the terms "first", "second", and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is one or more than one, unless otherwise explicitly and specifically limited.

[0043] First, the terms involved in the present application are explained:

[0044] The N+ region refers to an N-type semiconductor formed by adding pentavalent impurities in a pure semiconductor, and the impurities added therein provide additional electrons, referred to as donor atoms; in the N+ region, electrons are the majority carriers and holes are the minority carriers.

[0045] The P+ region refers to a P-type semiconductor formed by adding trivalent impurities in a pure semiconductor, and the impurities added therein provide additional holes, referred to as acceptor atoms; in the P+ region, the majority carriers are holes and the minority carriers are electrons.

[0046] The electrostatic protection device of the present application can be used for the protection of static electricity in integrated circuits, of course, it can also be used for the protection of static electricity in other scenarios, which is not limited here.

[0047] As the manufacturing process node of integrated circuits continues to shrink, the transistor gate oxide layer becomes thinner. If no special ESD protection design is performed, the chip is extremely vulnerable to ESD high-voltage and large-current impact and may occur failure phenomena such as thermal breakdown, gate oxide breakdown, and metal line melting. SCR-LDMOS has strong robustness and can discharge ESD large current, so it is widely used as an ESD protection device in power management chips.

[0048] Figure 1 A structural schematic diagram of a certain electrostatic protection device in the prior art is shown in FIG. 1. Figure 1As shown, the electrostatic protection device (a conventional SCR-LDMOS protection device) comprises a P-type substrate layer 10, a buried oxide layer 11 and an N-type epitaxial region 12. The buried oxide layer 11 is arranged on the upper surface of the P-type substrate layer 10, the N-type epitaxial region 12 is arranged on the upper surface of the buried oxide layer 11, and an N-type buffer region 13 and a P-type body region 14 are respectively embedded on both sides of the upper surface of the N-type epitaxial region 12. The upper surface of the N-type buffer region 13 is embedded with a first N+ region 15 and a first P+ region 16, the first N+ region 15 and the first P+ region 16 are connected by a metal wire, and a metal anode 36 is led out on the metal wire, the metal anode 36 is connected to a circuit interface; the upper surface of the P-type body region 14 is embedded with a third N+ region 19 and a third P+ region 20, the third N+ region 19 and the third P+ region 20 are connected by a metal wire, and a second metal cathode 40 is led out on the metal wire, the second metal cathode 40 is arranged to be grounded. The N-type epitaxial region 12 is located on the upper surface between the N-type buffer region and the P-type body region, and a thin gate oxide layer 33 is further arranged, the thin gate oxide layer 33 is further arranged with a gate electrode 34, the gate electrode 34 can lead out a gate electrode, and the gate electrode is arranged to be grounded. When the metal anode 36 is connected to static electricity through the circuit interface, the static electricity will be released through the current discharge channel in the electrostatic protection device: the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, and the second metal cathode 40 connected to the ground through the metal wire, to complete the current discharge.

[0049] However, due to the difference in material between the N-type buffer region 13 and the N-type epitaxial region 12, the breakdown voltage between them is large, that is, the voltage required to break down the interface between the N-type buffer region 13 and the N-type epitaxial region 12 to make the charge flow between them is high, so that the trigger voltage of the electrostatic protection device is high. Before the static voltage reaches the trigger voltage (the breakdown voltage of the N-type buffer region 13 and the N-type epitaxial region 12), the electrostatic protection device will not start, and there is still static electricity in the circuit connected thereto, which may cause damage to the integrated circuit chip if the static electricity is not discharged in time.

[0050] The electrostatic protection device provided by the application aims to solve the above technical problems in the prior art. The electrostatic protection device can additionally have a second P+ region and a second N+ region on the upper surface of the N-type buffer region between the N-type epitaxial region and the P-type body region, and the second P+ region, the second N+ region and the gate are electrically connected, and the gate is located on the junction of the upper surface of the N-type epitaxial region and the P-type body region. Through such a setting, after the metal anode provided on the N-type buffer region is connected to static electricity through a circuit interface, the static electricity enters the first P+ region, and the N-type buffer region will continuously migrate holes to the second P+ region of the N-type epitaxial region, causing the second P+ region to generate positive charges. Since the second P+ region, the second N+ region and the gate are electrically connected, the gate will be continuously coupled with a positive voltage, causing the second P+ region and the gate to form equal positive voltages; and the gate is covered on the thin gate oxide layer as a medium, so that the thin gate oxide layer also forms a positive voltage. Due to the attraction of the charges, the positive voltage of the thin gate oxide layer will cause the surface of the P-type body region below to form an aggregation of minority carrier electrons, thereby gradually forming an inversion layer, together with the N-type epitaxial layer, to form an electron transport channel, so that the P-type body region with a negative voltage and the N-type epitaxial region with a positive voltage generate a charge flow, so that the static electricity can flow out through the first P+ region, the N-type buffer region, the N-type epitaxial region, the second P+ region, the gate, the thin gate oxide layer, and finally through the metal cathode provided on the N-type epitaxial region and / or the P-type body region, to achieve the purpose of current discharge. In addition, during the current discharge process, the charge flow between the P-type body region and the N-type epitaxial region can also continuously break down the interface between the P-type body region and the N-type epitaxial region, thereby opening the PNPN main current discharge channel of the protection device: the first P+ region, the N-type buffer region, the N-type epitaxial region, the P-type body region, the third N+ region. The first P+ region, the N-type buffer region, the N-type epitaxial region, the second P+ region, the gate and the thin gate oxide layer can constitute a PNP1-C structure, the second N+ region, the N-type epitaxial region, the P-type body region, the third N+ region, the gate and the thin gate oxide layer can constitute an NMOS structure, and the current discharge channel constituted by the PNP1-C structure and the NMOS structure can serve as an auxiliary discharge channel of the main current discharge channel of the protection device. Through such a setting, after the metal anode is connected to static electricity through a circuit interface, a smaller static voltage will trigger the opening of the PNP1-C structure, and the discharge current is discharged through the NMOS structure, thereby avoiding the damage of the integrated circuit caused by the failure of the main current discharge channel with a high trigger voltage to open when the static voltage is small, and improving the safety of the circuit. In addition, when the current is discharged through the PNP1-C-NMOS current discharge channel, the interface between the P-type body region and the N-type epitaxial region can also be continuously broken down, thereby opening the PNPN main current discharge channel of the protection device, avoiding the damage of the integrated circuit caused by the failure of the static discharge in time when the static voltage is high, and further improving the safety of the circuit.

[0051] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0052] Example 1

[0053] Figure 2 This is a schematic structural diagram of an electrostatic protection device according to an embodiment of the present application. Figure 2 As shown, the electrostatic protection device may include:

[0054] N-type epitaxial region 12, N-type buffer region 13 and P-type body region 14; the N-type buffer region 13 and the P-type body region 14 are respectively embedded on both sides of the upper surface of the N-type epitaxial region 12, the metal anode 36 provided on the N-type buffer region 13 is connected to the circuit interface, and a metal cathode is provided on the N-type epitaxial region 12 and / or the P-type body region 14.

[0055] The upper surface of the N-type buffer region 13 is embedded with a first N+ region 15 and a first P+ region 16. The N-type epitaxial region 12 is located on the upper surface between the N-type buffer region 13 and the P-type body region 14, and is embedded with a second P+ region 17 and a second N+ region 18. The upper surface of the P-type body region 14 is embedded with a third N+ region 19 and a third P+ region 20.

[0056] A thin gate oxide layer 33 is provided between the second N+ region 18 and the third N+ region 19. The thin gate oxide layer 33 is located at the connection between the upper surface of the N-type epitaxial region 12 and the P-type body region 14. A gate 34 is also covered on the thin gate oxide layer 33, and the second P+ region 17, the second N+ region 18 and the gate 34 are electrically connected.

[0057] In this embodiment, if Figure 2 As shown, the N-type epitaxial region 12 can be an inverted T-shape, and the N-type buffer region 13 and the P-type body region 14 can be respectively located on two opposite sides of the upper surface of the N-type epitaxial region 12, and form a square with the N-type epitaxial region 12, that is, the side of the N-type buffer region 13 that is not in contact with the N-type epitaxial region 12 is connected to the edge of the side (left side) of the N-type epitaxial region 12, and the side of the P-type body region 14 that is not in contact with the N-type epitaxial region 12 is connected to the edge of the side (right side) of the N-type epitaxial region 12.

[0058] In this embodiment, the N-epi region 12, the N-buffer region 13, and the P-body region 14 may refer to the structure of the electrostatic protection device SCR-LDMOS in the prior art, and are not described in detail here.

[0059] In this embodiment, the N-type epitaxial layer (N-epi) can be set to grow an N-type doped region with a certain thickness but lower doping concentration on the upper surface of the buried oxide layer 11 (BOX) as the drift region of the SCR-LDMOS.

[0060] In this embodiment, the static electricity in the integrated circuit can flow into the electrostatic protection device through the metal anode 36 on the N-type buffer region 13 and be discharged through the thin gate oxide layer 33 or the gate 34 in the N-type epitaxial region 12 or the P-type body region 14. The N-type buffer region 13 can buffer the charges migrated from the first N+ region 15 and the first P+ region 16, thereby blocking the reverse power consumption.

[0061] In this embodiment, the size and shape of the P+ region and the N+ region can be set to be consistent to facilitate the migration of charges, thereby forming a current discharge channel.

[0062] In this embodiment, the gate 34 can be a metal layer, and the thin gate oxide layer 33 can be a dielectric layer. When the gate 34 has a positive voltage, the metal layer of the gate 34 can cause the lower surface of the thin gate oxide layer 33 to also have a positive voltage through the dielectric layer of the thin gate oxide layer 33.

[0063] In this embodiment, after the static electricity in the integrated circuit enters the first metal rod group A through the metal anode 36, the static electricity can flow into the first P+ region 16 through the first metal rod group A, and the PNP1-C structure composed of the first P+ region 16, the N-type epitaxial region 12, the second P+ region 17, the gate 34, and the thin gate oxide layer 33 is turned on, thereby turning on the NMOS structure composed of the second N+ region 18, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, the gate 34, and the thin gate oxide layer 33, and assisting in static electricity discharge.

[0064] In this embodiment, the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the second P+ region 17, the gate 34, and the thin gate oxide layer 33 form a PNP1-C structure. The second N+ region 18, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, the gate 34, and the thin gate oxide layer 33 can form an NMOS structure, and the current discharge channel formed by the PNP1-C structure and the NMOS structure can serve as an auxiliary discharge channel of the main current discharge channel of the protection device. When the auxiliary discharge channel discharges current, it will continuously break down the interface between the P-type body region 14 and the N-type epitaxial region 12, thereby turning on the PNPN main current discharge channel of the protection device: the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the P-type body region 14, and the third N+ region 19.

[0065] In the embodiment, the parasitic PNPN structure of the first P+ region 16, the N-type buffer region 13, the N-type epitaxial layer 12, the P-type body region 14, and the third N+ region 19, on one hand, the existence of the parasitic PNP1 transistor can increase the current flowing through the resistance RN in the N-type buffer region 13 under the action of the ESD signal, which helps to turn on the parasitic PNP transistor; the existence of the parasitic NPN1 transistor can increase the current flowing through the resistance RP in the P-type body region 14, which helps to turn on the parasitic NPN transistor, and the two work together to reduce the trigger voltage. On the other hand, the first P+ region 16 as the emitter of the PNP1 structure is shared with the parasitic PNP transistor, which can reduce the hole concentration injected by the first P+ region 16 into the N-type buffer region 13; the third N+ region 19 as the emitter of the NMOS structure is shared with the parasitic NPN transistor, which can reduce the electron concentration injected by the third N+ region 19 into the P-type body region 14. The conductance modulation effect in the N-type buffer region 13 and the P-type body region 14 is weakened, and the device holding voltage is improved.

[0066] In the embodiment, an additional second P+ region 17 and a second N+ region 18 can be added on the upper surface of the N-type epitaxial region 12 between the N-type buffer region 13 and the P-type body region 14, and the second P+ region 17, the second N+ region 18, and the gate 34 are electrically connected, and the gate 34 is located on the connection of the upper surface of the N-type epitaxial region 12 and the P-type body region 14. Through such a setting, after the metal anode 36 provided on the N-type buffer region 13 is connected to static electricity through the circuit interface, the static electricity enters the first P+ region 16, and the N-type buffer region 13 will continuously migrate holes to the second P+ region 17 of the N-type epitaxial region 12, resulting in the generation of positive charges in the second P+ region 17. Since the second P+ region 17, the second N+ region 18, and the gate 34 are electrically connected, a positive voltage will be continuously coupled to the gate 34, resulting in the formation of equal positive voltage in the second P+ region 17 and the gate 34; and the gate 34 is covered on the thin gate oxide layer 33 as a dielectric, so that the thin gate oxide layer 33 also forms a positive voltage.

[0067] The positive voltage thin gate oxide layer 33 will cause the surface of the underlying P-type body region 14 to form an aggregation of minority carrier electrons due to the attraction of the electric charges, thereby gradually forming an inversion layer, together with the N-type epitaxial layer 12, to form a transport channel for electrons, so that the P-type body region 14 with a negative voltage and the N-type epitaxial region 12 with a positive voltage generate a charge flow, so that the static electricity can flow out through the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the second P+ region 17, the gate 34, the thin gate oxide layer 33, and finally through the metal cathode provided on the N-type epitaxial region and / or the P-type body region, to achieve the purpose of current discharge. In addition, during the current discharge, the charge flow between the P-type body region 14 and the N-type epitaxial region 12 can also continuously break down the interface between the P-type body region 14 and the N-type epitaxial region 12, thereby opening the PNPN main current discharge channel of the protection device: the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the P-type body region 14, and the third N+ region 19.

[0068] The first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the second P+ region 17, the gate 34, and the thin gate oxide layer 33 can constitute a PNP1-C structure, and the second N+ region 18, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, the gate 34, and the thin gate oxide layer 33 can constitute an NMOS structure, and the PNP1-C structure and the NMOS structure have a low opening voltage, and the current discharge channel formed thereby can serve as an auxiliary discharge channel of the main current discharge channel of the protection device. Through such a design, after the metal anode 36 is connected to the static electricity through the circuit interface, a smaller static voltage will trigger the opening of the PNP1-C structure, and the current is discharged through the NMOS structure, thereby avoiding the situation that when the static voltage is relatively low, the main current discharge channel with a high trigger voltage is not opened, which leads to the failure to discharge the static electricity in time and damages the integrated circuit, and improving the safety of the circuit. In addition, when the current is discharged through the PNP1-C-NMOS current discharge channel, the interface between the P-type body region 14 and the N-type epitaxial region 12 can be continuously broken down, thereby opening the PNPN main current discharge channel of the protection device, avoiding the situation that when the static voltage is relatively high, the static electricity is not discharged in time and damages the integrated circuit, and further improving the safety of the circuit.

[0069] In summary, in addition to the original PNPN main current discharge channel, the newly added PNP1-C-NMOS auxiliary current discharge channel provides an additional flow path for electron-hole flow, which can achieve current shunting, weaken the positive feedback effect caused by the internal SCR path of the device, improve the holding voltage of the device, and thereby optimize the ESD window of the device, while maintaining the high robustness of the SCR-LDMOS, effectively reducing the design window, and reducing the risk of device latch-up.

[0070] In one possible implementation, as shown in FIG. 1, the protection device comprises a P-type substrate 10, an N-type epitaxial layer 12, a P-type body region 14, a gate 34, a thin gate oxide layer 33, a first P+ region 16, an N-type buffer region 13, a second P+ region 17, a third N+ region 19, a metal anode 36, and a metal cathode 37. Figure 2As shown, the upper surface of the N-type buffer region 13 can also be embedded with a first isolation region 21, which can be used to isolate the first N+ region 15 and the edge of the electrostatic protection device;

[0071] The upper surface between the first P+ region 16 and the second P+ region 17 can also be embedded with a second isolation region 22, which can be used to isolate the first P+ region 16 and the second P+ region 17;

[0072] The upper surface between the second P+ region 17 and the second N+ region 18 can also be embedded with a third isolation region 23, which can be used to isolate the second P+ region 17 and the second N+ region 18;

[0073] The upper surface between the third N+ region 19 and the third P+ region 20 can also be embedded with a fourth isolation region 24, which can be used to isolate the third N+ region 19 and the third P+ region 20;

[0074] The upper surface of the P-type body region 14 can also be embedded with a fifth isolation region 25, which can be used to isolate the third P+ region 20 and the edge of the electrostatic protection device.

[0075] In the present embodiment, the sizes of the first isolation region 21, the second isolation region 22, the third isolation region 23, the fourth isolation region 24 and the fifth isolation region 25 can be flexibly set, and can be the same or different, which is not limited herein. The smaller the distance between the first P+ region 16 and the second P+ region 17 (the size of the second isolation region 22) is, the smaller the trigger voltage is, but the holding voltage will also be smaller. Therefore, the person skilled in the art can adjust the size of the second isolation region 22 through multiple tests, and compromise between the holding voltage and the trigger voltage to finally determine the appropriate trigger voltage and holding voltage, so as to achieve a better electrostatic discharge effect.

[0076] In the present embodiment, the first isolation region 21, the second isolation region 22, the third isolation region 23, the fourth isolation region 24 and the fifth isolation region 25 can be shallow trench isolation regions, which achieve the purpose of charge isolation by setting shallow trenches.

[0077] In this embodiment, the presence of the first isolation region 21 and the second isolation region 22 ensures that charges generated by the first N+ region 15 and the first P+ region 16 enter only the N-type buffer region 13. The presence of the second isolation region 22 ensures that charges generated by the first P+ region 16 and the second P+ region 17 do not migrate through the N-type buffer region 13 and the upper surface of the N-type epitaxial region 12. The presence of the third isolation region 23 ensures that charges generated by the second P+ region 17 and the second N+ region 18 do not migrate through the upper surface of the N-type epitaxial region 12. The presence of the fourth isolation region 24 and the fifth isolation region 25 ensures that charges generated by the third N+ region 19 and the third P+ region 20 do not migrate through the upper surface of the N-type epitaxial region 12, but flow only into the second metal cathode 40 through the second metal rod group B. This arrangement ensures that static electricity is properly discharged through the current discharge channel between the N-type buffer region 13, the N-type epitaxial region 12, and the P-type body region 14, avoiding charge interference.

[0078] In a possible implementation, the first N+ region 15 and the first P+ region 16 may be connected via a first metal wire, and a metal anode is provided on the first metal wire, and the metal anode is connected to a circuit interface.

[0079] In this embodiment, the first N+ region 15 and the first P+ region 16 can be electrically connected via a first metal wire, which is simple and convenient to operate and has low installation cost.

[0080] Alternatives, such as Figure 2 As shown, first N+ region 15 and first P+ region 16 may also be connected via a first metal rod group A. A metal anode 36 is provided on first metal rod group A, and metal anode 36 is connected to a circuit interface. Static electricity in the integrated circuit can flow into first N+ region 15 and first P+ region 16 through metal anode 36 and first metal rod group A, respectively, to cause charge transfer and flow into N-type buffer region 13.

[0081] In this embodiment, the first N+ region 15 and the first P+ region 16 can also be electrically connected through the first metal rod group A. Since the resistance of the metal rod is lower than that of the metal wire, this arrangement can improve the electrostatic conduction efficiency.

[0082] In one possible implementation, Figure 2 As shown, the first metal rod group A may include a first metal rod 26, a second metal rod 27 and an eighth metal rod 35, and a metal anode 36 may be provided on the eighth metal rod 35; the first metal rod 26 may be connected to the first N+ region 15 and the eighth metal rod 35 respectively, and the second metal rod 27 may be connected to the first P+ region 16 and the eighth metal rod 35 respectively.

[0083] In the embodiment, the first metal rod 26, the second metal rod 27 and the eighth metal rod 35 can be integrally arranged to form the first metal rod group A, or can be separately arranged to form the first metal rod group A by means of component connection, which is not limited herein. In addition, the connection mode of the first metal rod 26 and the first N+ region 15, and the connection mode of the second metal rod 27 and the first P+ region 16 are not limited herein.

[0084] In the embodiment, the first N+ region 15 and the first P+ region 16 can be connected by the first metal rod group A composed of the first metal rod 26, the second metal rod 27 and the eighth metal rod 35, and the resistance of the metal rod is smaller than that of the metal wire. By such an arrangement, the speed of the electrostatic current flowing into the first N+ region 15 and the first P+ region 16 can be improved, and the speed of voltage rising can be accelerated, thereby improving the electrostatic discharge efficiency.

[0085] In a possible embodiment, the second P+ region 17, the second N+ region 18 and the gate 34 can be connected by the third metal wire.

[0086] In the embodiment, the second P+ region 17, the second N+ region 18 and the gate 34 can be electrically connected by the first metal wire, which is simple and convenient to operate and low in installation cost.

[0087] Alternatively, as shown in FIG. 6, the second P+ region 17, the second N+ region 18 and the gate 34 can also be connected by the second metal rod group B. Figure 2

[0088] In the embodiment, the second P+ region 17, the second N+ region 18 and the gate 34 can also be electrically connected by the second metal rod group B. Since the resistance of the metal rod is smaller than that of the metal wire, by such an arrangement, the electrostatic conduction efficiency can be improved.

[0089] In a possible embodiment, the third metal wire can be provided with the first metal cathode 38, or the third metal rod group C can be provided with the first metal cathode 38.

[0090] In the embodiment, after the second metal wire or the second metal rod group B is connected between the third N+ region 19 and the third P+ region 20, if the second metal wire or the second metal rod group B is not provided with a metal cathode (the second metal cathode 40), the current path can be completed by arranging the first metal cathode 38 on the third metal wire or the third metal rod group C to discharge the static electricity. Of course, if the second metal wire or the second metal rod group B is provided with the second metal cathode 40, the current path can also be increased by arranging the first metal cathode 38 on the third metal wire or the third metal rod group C to assist in discharging the static electricity, thereby improving the current discharge efficiency.

[0091] ​In one possible implementation, as shown in Figure 2 The second metal rod group B can include a third metal rod 28, a fourth metal rod 29, a fifth metal rod 30, and a ninth metal rod 37, and the ninth metal rod 37 can be provided with a first metal cathode 38; the third metal rod 28 can be connected with the second P+ region 17 and the ninth metal rod 37 respectively, the fourth metal rod 29 can be connected with the second N+ region 18 and the ninth metal rod 37 respectively, and the fifth metal rod 30 can be connected with the gate 34 and the ninth metal rod 37 respectively.

[0092] In the present embodiment, the third metal rod 28, the fourth metal rod 29, the fifth metal rod 30, and the ninth metal rod 37 can be integrally provided to form a third metal rod group C, or can be separately provided to form the third metal rod group C by means of component connection, which is not limited herein. In addition, the connection modes of the third metal rod 28 with the second P+ region 17, the fourth metal rod 29 with the second N+ region 18, and the fifth metal rod 30 with the gate 34 are not limited. The first metal cathode 38 can be an electrode led out of the ninth metal rod 37, which can be idle or connected with other devices or voltage. For example, two electrostatic protection devices can be connected in series, and the first metal cathode of one electrostatic protection device can be connected with the metal anode or metal cathode of the other electrostatic protection device.

[0093] In the present embodiment, the gate 34 is no longer provided with a ground, but is connected with the second P+ region 17 through the third metal rod group C, so as to be at the same potential as the second P+ region 17, so as to form a PNP1-C structure of the first P+ region 16, the N-type epitaxial region 12, the second P+ region 17, the gate 34, and the thin gate oxide layer 33, and an NMOS structure of the second N+ region 18, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, the gate 34, and the thin gate oxide layer 33, so as to complete the construction of the PNP1-C-NMOS auxiliary current discharge channel. Further, the second P+ region 17, the second N+ region 18, and the gate 34 can be connected through the third metal rod group C composed of the third metal rod 28, the fourth metal rod 29, the fifth metal rod 30, and the ninth metal rod 37, so as to realize the equipotential of the second P+ region 17, the second N+ region 18, and the gate 34. In addition, since the resistance of the metal rod is smaller than that of the metal wire, the presence of the third metal rod group C can also improve the charge flow efficiency, thereby improving the electrostatic discharge efficiency.

[0094] In one possible implementation, the third N+ region 19 and the third P+ region 20 can be connected by a second metal wire.

[0095] In the present embodiment, the third N+ region 19 and the third P+ region 20 can be electrically connected by a first metal wire, which is simple and convenient to operate and has low installation cost.

[0096] Alternatively, as shown inFigure 2 As shown, the third N+ region 19 and the third P+ region 20 may be further connected via a second metal rod group B.

[0097] In this embodiment, the third N+ region 19 and the third P+ region 20 can also be electrically connected through the second metal rod group B. Since the resistance of the metal rod is lower than that of the metal wire, this arrangement can improve the electrostatic conduction efficiency.

[0098] In a possible implementation, a second metal cathode 40 may be provided on the second metal wire, and the second metal cathode 40 is grounded; or a second metal cathode 40 may be provided on the second metal rod group B, and the second metal cathode 40 is grounded.

[0099] In this embodiment, by providing a second metal cathode 40 on the second metal wire or the second metal rod group B, an auxiliary current discharge channel of the PNP1-C-NMOS and a final PNPN main current discharge channel can be formed, thereby improving current discharge efficiency.

[0100] It should be noted that, since the current discharge effect of the channel ultimately formed by the second metal cathode 40 is better than that of the channel formed by the first metal cathode 38, if only one metal cathode can be provided on the electrostatic protection device, it is preferred to provide the second metal cathode 40. Of course, in addition to providing the second metal cathode 40, the first metal cathode 38 can also be provided as an auxiliary and supplementary device.

[0101] In one possible implementation, Figure 2 As shown, the second metal rod group B may include a sixth metal rod 31, a seventh metal rod 32 and a tenth metal rod 39, and a second metal cathode 40 may be provided on the tenth metal rod 39; the sixth metal rod 31 may be connected to the third N+ region 19 and the tenth metal rod 39 respectively, and the seventh metal rod 32 may be connected to the third P+ region 20 and the tenth metal rod 39 respectively.

[0102] In this embodiment, the sixth metal rod 31, the seventh metal rod 32, and the tenth metal rod 39 can be integrally formed to form the second metal rod group B, or they can be separate components connected to form the second metal rod group B, without any limitation. Furthermore, the connection method between the sixth metal rod 31 and the third N+ region 19, and the seventh metal rod 32 and the third P+ region 20, is also not subject to any limitation.

[0103] In this embodiment, the third N+ region 19 and the third P+ region 20 can be connected by a second metal rod group B consisting of a sixth metal rod 31, a seventh metal rod 32 and a tenth metal rod 39. The resistance of the metal rod is smaller than that of the metal wire. Through such a setting, the speed at which static electricity flows into the second metal cathode 40 through the third N+ region 19 can be increased, thereby improving the static electricity discharge efficiency.

[0104] In one possible implementation, as shown in FIG. 4, the gate 34 can be the same size as the thin gate oxide layer 33, and completely covers the thin gate oxide layer 33. Figure 2

[0105] In the present embodiment, the smaller the gate 34 (the thin gate oxide layer 33), the smaller the triggering voltage, and the better the static electricity release effect. Those skilled in the art can determine the appropriate triggering voltage by adjusting the size of the gate 34 (the thin gate oxide layer 33), so as to achieve a better static electricity release effect.

[0106] In the present embodiment, by setting the gate 34 and the thin gate oxide layer 33 to be the same size, and the gate 34 completely covering the thin gate oxide layer 33, the conductive effect of the thin gate oxide layer 33 can be enhanced, thereby enhancing the positive voltage of the lower surface of the thin gate oxide layer 33, and enhancing the negative voltage of the upper surface of the P-type body region 14 in contact with the thin gate oxide layer 33, so that the NMOS structure composed of the second N+ region 18, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, the gate 34 and the thin gate oxide layer 33 is smoothly turned on, to assist in static electricity discharge.

[0107] In one possible implementation, as shown in FIG. 4, the gate 34 can be the same size as the thin gate oxide layer 33, and completely covers the thin gate oxide layer 33. Figure 2

[0108] In the present embodiment, the P-type substrate layer (P-sub) 10 and the buried oxide layer (BOX) 11 can refer to the structure in the prior art static protection device SCR-LDMOS, which will not be described here. The size of the P-type substrate layer 10 and the buried oxide layer 11 can be set to be the same, and the specific size is not limited.

[0109] In the present embodiment, by setting the buried oxide layer 11 on the upper surface of the P-type substrate layer 10, and setting the N-type epitaxial region 12 on the upper surface of the buried oxide layer 11, the smooth static electricity discharge of the static protection device can be ensured.

[0110] The static protection device of the present application will be described below with a specific example.

[0111] Example Two

[0112] In one specific example, the static protection device of the present application is connected to the integrated circuit through a circuit interface. When static electricity is generated in the integrated circuit, the static electricity flows into the static protection device through the circuit interface for discharge.

[0113] ​​Specifically, after the static electricity is connected to the first metal rod group A through the metal anode 36, the static electricity can flow into the first P+ region 16 through the first metal rod group A. The first P+ region 16 will continuously migrate holes to the second P+ region 17 of the N-type epitaxial region 12 through the N-type buffer region 13 and the N-type epitaxial region 12, resulting in the generation of positive charges in the second P+ region 17. The third metal rod group C is connected between the second P+ region 17, the second N+ region 18 and the gate 34, which will continuously couple positive voltage to the gate 34, resulting in the formation of equal positive voltage in the second P+ region 17 and the gate 34. Since the charges are attracted, the positive voltage of the thin gate oxide layer 33 will cause the surface of the P-type body region 14 below to form an aggregation of minority carrier electrons, thereby gradually forming an inversion layer, together with the N-type epitaxial layer 12, to form an electron transport channel, so that the P-type body region 14 with negative voltage and the N-type epitaxial region 12 with positive voltage generate charge flow, so that the static electricity can flow into the second metal cathode 40 grounded on the second metal rod group B through the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the second P+ region 17, the third metal rod group C, the gate 34, the thin gate oxide layer 33, the P-type body region 14 and the third N+ region 19, before the PNPN main current discharge channel is opened, through the newly added PNP1-C-NMOS auxiliary current discharge channel to release static electricity.

[0114] In addition, the charge flow between the P-type body region 14 and the N-type epitaxial region 12 can also continuously break down the interface between the P-type body region 14 and the N-type epitaxial region 12, thereby opening the larger PNPN main current discharge channel, flowing into the second metal cathode 40 grounded on the second metal rod group B through the first P+ region 16, the N-type buffer region 13, the N-type epitaxial region 12, the P-type body region 14, the third N+ region 19, to quickly complete the static electricity release.

[0115] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0116] It is understood that the application is not limited to the precise construction disclosed and illustrated in the accompanying drawings and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is indicated by the following claims.

Claims

1. An electrostatic protection device, characterized in that: include: N-type epitaxial region, N-type buffer region and P-type body region; The N-type buffer region and the P-type body region are respectively embedded on two sides of the upper surface of the N-type epitaxial region. The metal anode provided on the N-type buffer region is connected to the circuit interface. The N-type epitaxial region and / or the P-type body region are provided with a metal cathode. The upper surface of the N-type buffer region is embedded with a first N+ region and a first P+ region, the upper surface of the N-type epitaxial region is located between the N-type buffer region and the P-type body region, and is embedded with a second P+ region and a second N+ region, and the upper surface of the P-type body region is embedded with a third N+ region and a third P+ region; A thin gate oxide layer is provided between the second N+ region and the third N+ region, and the thin gate oxide layer is located at the connection between the N-type epitaxial region and the upper surface of the P-type body region; a gate is also covered on the thin gate oxide layer, and the second P+ region, the second N+ region and the gate are electrically connected.

2. The electrostatic protection device according to claim 1, characterized in that: A first isolation region is further embedded in the upper surface of the N-type buffer region, and the first isolation region is used to isolate the first N+ region from the edge of the electrostatic protection device; A second isolation region is further embedded in the upper surface between the first P+ region and the second P+ region, and the second isolation region is used to isolate the first P+ region from the second P+ region; A third isolation region is further embedded in the upper surface between the second P+ region and the second N+ region, and the third isolation region is used to isolate the second P+ region from the second N+ region; A fourth isolation region is further embedded in the upper surface between the third N+ region and the third P+ region, and the fourth isolation region is used to isolate the third N+ region from the third P+ region; A fifth isolation region is further embedded in the upper surface of the P-type body region, and the fifth isolation region is used to isolate the third P+ region from the edge of the electrostatic protection device.

3. The electrostatic protection device according to claim 1, characterized in that The first N+ region and the first P+ region are connected via a first metal wire, a metal anode is provided on the first metal wire, and the metal anode is connected to the circuit interface; Alternatively, the first N+ region and the first P+ region are connected via a first metal rod group, a metal anode is provided on the first metal rod group, and the metal anode is connected to the circuit interface.

4. The electrostatic protection device according to claim 3, characterized in that: The first metal rod group includes a first metal rod, a second metal rod and an eighth metal rod, and the eighth metal rod is provided with a metal anode; The first metal rod is connected to the first N+ region and the eighth metal rod respectively, and the second metal rod is connected to the first P+ region and the eighth metal rod respectively.

5. The electrostatic protection device according to any one of claims 1 to 4, characterized in that: The second P+ region, the second N+ region and the gate are connected via a third metal wire; Alternatively, the second P+ region, the second N+ region and the gate are connected via a third metal rod group.

6. The electrostatic protection device according to claim 5, characterized in that: The third metal wire is provided with a first metal cathode, or the third metal rod group is provided with a first metal cathode.

7. The electrostatic protection device according to claim 6, characterized in that: The third metal rod group includes a third metal rod, a fourth metal rod, a fifth metal rod and a ninth metal rod, and the ninth metal rod is provided with a first metal cathode; The third metal rod is connected to the second P+ region and the ninth metal rod respectively, the fourth metal rod is connected to the second N+ region and the ninth metal rod respectively, and the fifth metal rod is connected to the gate and the ninth metal rod respectively.

8. The electrostatic protection device according to any one of claims 1 to 4, characterized in that: The third N+ region and the third P+ region are connected via a second metal wire; Alternatively, the third N+ region and the third P+ region are connected via a second metal rod group.

9. The electrostatic protection device according to claim 8, characterized in that: A second metal cathode is provided on the second metal wire, and the second metal cathode is grounded; Alternatively, a second metal cathode is provided on the second metal rod group, and the second metal cathode is grounded.

10. The electrostatic protection device according to claim 9, characterized in that: The second metal rod group includes a sixth metal rod, a seventh metal rod and a tenth metal rod, and the tenth metal rod is provided with a second metal cathode; The sixth metal rod is connected to the third N+ region and the tenth metal rod respectively, and the seventh metal rod is connected to the third P+ region and the tenth metal rod respectively.

11. The electrostatic protection device according to any one of claims 1 to 4, characterized in that: The gate electrode has the same size as the thin gate oxide layer and completely covers the thin gate oxide layer.

12. The electrostatic protection device according to claim 11, characterized in that: The electrostatic protection device further includes a P-type substrate layer and a buried oxide layer; The buried oxide layer is arranged on the upper surface of the P-type substrate layer, and the N-type epitaxial region is arranged on the upper surface of the buried oxide layer.

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