Phase-locked loop circuit

Abstract

A phase-locked loop (PLL) circuit includes: a frequency and phase discrimination unit adapted to compare the phases of a reference signal and a feedback signal, and output a phase difference signal and an enable signal; a charge pump unit adapted to convert the phase difference signal into a first electrical signal; a charge neutralization unit adapted to store the charge corresponding to the first electrical signal and generate a second electrical signal under the action of the first electrical signal, the enable signal, and a power supply, and to store the charge corresponding to the second electrical signal and output the second electrical signal when the first charge and the second charge are equal; a digital-to-analog converter unit adapted to convert the type of the second electrical signal to obtain a third electrical signal output; a loop filter adapted to filter the first electrical signal and the third electrical signal; a voltage-controlled oscillator adapted to generate an output signal of a corresponding frequency under the control of the first current signal and the third current signal; and a feedback unit. Using the above scheme, the charge mismatch phenomenon of the charge pump unit can be eliminated, and the phase noise performance of the PLL circuit can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technology, and in particular to a phase-locked loop circuit. Background Technology

[0002] Phase-locked loops (PLLs), as one of the fundamental modules in analog circuits, are widely used in wireless communication, frequency synthesis, clock recovery, and other fields. Among various PLL structures, charge pump PLLs are among the most widely used due to their high stability and low power consumption.

[0003] A charge pump phase-locked loop includes a frequency and phase detector, a charge pump, a filter, a voltage-controlled oscillator (VCO), and a frequency divider. The VCO generates a clock signal, which is divided by the frequency divider to obtain a divided signal, which is then fed back to the frequency and phase detector. The frequency and phase detector compares the divided signal with the phase of a reference signal. The comparison result is filtered by the charge pump and the filter and then output to the VCO for frequency control to obtain an output signal at a preset frequency.

[0004] In charge pump phase-locked loop (PLL) circuits, the current linearity of the charge pump unit and the magnitude of the charge / discharge current directly affect the performance of the entire PLL. In practical applications, the charge pump unit is affected by factors such as process deviations, charge sharing among internal components, and channel modulation effects, leading to charge mismatch in the charge pump unit and consequently, poor phase noise performance of the entire charge pump PLL.

[0005] Currently, charge pump phase-locked loops are mainly used in integrated circuits (e.g., system-on-a-chip). In order to eliminate the charge mismatch phenomenon of the charge pump unit, components such as digital-to-analog converters, controllers, and registers are usually added to the integrated circuit. The digital-to-analog converter can be coupled to the controller and the charge pump respectively. The controller can achieve the matching of the output charge of the digital-to-analog converter with the output charge of the charge pump through the output of the digital-to-analog converter, thereby eliminating the charge mismatch phenomenon of the charge pump unit.

[0006] However, during the charge matching process, since the relevant parameters of the digital-to-analog converter and the charge pump (e.g., current magnitude and current duration) may change, additional calibration and matching operations are required to ensure that the charge output by the digital-to-analog converter unit is equal to the charge output by the charge pump unit, thereby eliminating the charge mismatch phenomenon of the charge pump unit. Summary of the Invention

[0007] In view of this, embodiments of the present invention provide a phase-locked loop circuit that can eliminate the charge mismatch phenomenon of the charge pump unit and improve the phase noise performance of the phase-locked loop circuit.

[0008] This invention provides a phase-locked loop circuit, comprising: a frequency and phase discrimination unit, a charge pump unit, a charge neutralization unit, a digital-to-analog converter unit, a loop filter, a voltage-controlled oscillator, and a feedback unit, wherein:

[0009] The frequency and phase discrimination unit is coupled to the feedback unit and the charge pump unit respectively, and is adapted to compare the phase of the received reference signal at the input terminal of the phase-locked loop circuit and the phase of the feedback signal output by the feedback unit, and output the corresponding phase difference signal and enable signal to the charge pump unit.

[0010] The charge pump unit is coupled to the loop filter and the charge neutralization unit respectively, and is adapted to convert the phase difference signal into a first electrical signal, and output the first electrical signal and the enable signal to the charge neutralization unit, and output the first electrical signal to the loop filter;

[0011] The charge neutralization unit is coupled to the power supply and the digital-to-analog conversion unit respectively. It is adapted to store the charge corresponding to the first electrical signal and generate the second electrical signal under the action of the first electrical signal, the enable signal and the power supply, and store the charge corresponding to the second electrical signal. When the first charge and the second charge are equal, the second electrical signal is output to the digital-to-analog conversion unit.

[0012] The digital-to-analog converter unit is coupled to the loop filter and is adapted to convert the type of the second electrical signal and output the resulting third electrical signal to the loop filter;

[0013] The loop filter is coupled to the voltage-controlled oscillator and is adapted to filter the first electrical signal and the third electrical signal, and output to the voltage-controlled oscillator.

[0014] The voltage-controlled oscillator is adapted to generate and output an output signal of a corresponding frequency under the control of the first electrical signal and the third electrical signal;

[0015] The feedback unit is coupled to the voltage-controlled oscillator and is adapted to generate the feedback signal based on the output signal and output it to the frequency and phase discrimination unit.

[0016] Compared with the prior art, the technical solutions in the embodiments of the present invention have the following advantages:

[0017] The phase-locked loop circuit in this embodiment of the invention includes a frequency and phase discrimination unit, a charge pump unit, a charge neutralization unit, a digital-to-analog converter (DAC), a loop filter, a voltage-controlled oscillator (VCO), and a feedback unit. The charge pump unit outputs a first electrical signal and the enable signal to the charge neutralization unit and the loop filter based on the phase difference signal and enable signal output by the frequency and phase discrimination unit. The charge neutralization unit, under the action of the first electrical signal, the enable signal, and the power supply, stores the charge corresponding to the first electrical signal, generates a second electrical signal, and stores the charge corresponding to the second electrical signal. When the charge corresponding to the first electrical signal and the charge corresponding to the second electrical signal are equal, the second electrical signal is output to the DAC. The DAC converts the type of the second electrical signal and outputs the resulting third electrical signal to the loop filter. After processing by the loop filter and the VCO, the first electrical signal and the third electrical signal generate and output an output signal of the corresponding frequency. As can be seen from the above process, since the charge neutralization unit outputs the second electrical signal to the digital-to-analog converter (DAC) when the charges corresponding to the first and second electrical signals are the same, and the DAC converts the type of the second electrical signal, outputting the resulting third electrical signal to the loop filter, charge matching of the charge pump unit can be achieved through the superposition of the first and third electrical signals. Therefore, the phase-locked loop (PLL) circuit in this embodiment of the invention can eliminate the charge mismatch phenomenon of the charge pump unit and improve the phase noise performance of the PLL circuit. Attached Figure Description

[0018] Figure 1 A schematic diagram of a phase-locked loop circuit is shown.

[0019] Figure 2 A schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention is shown.

[0020] Figure 3 A schematic diagram of a charge neutralization unit in an embodiment of the present invention is shown.

[0021] Figure 4 The diagram shows the timing variation waveforms of key nodes in the charge neutralization unit in an embodiment of the present invention.

[0022] Figure 5 A schematic diagram of the phase noise curves of the charge pump circuit under different states in an embodiment of the present invention is shown.

[0023] Figure 6 A schematic diagram of another charge neutralization unit in an embodiment of the present invention is shown. Detailed Implementation

[0024] In specific implementations, as described in the background section, a phase-locked loop circuit can be used as part of a system-on-a-chip (SoC) to provide a signal of a preset frequency to the SoC.

[0025] Reference Figure 1 The diagram shows a phase-locked loop (PLL) circuit. The PLL circuit 10 can provide a signal of a preset frequency to the on-chip system. The PLL circuit 10 may include a phase-frequency detector 11, a charge pump 12, a filter 13, a voltage-controlled oscillator 14, and a frequency divider 15. The voltage-controlled oscillator 14 generates a clock signal, which is then divided by the frequency divider 15 to obtain a divided frequency signal F. ck And feed it back to the frequency and phase detector 11, which then divides the frequency signal F. ck With reference signal F ref The phases are compared, and the comparison result is filtered by charge pump 12 and filter 13 and then output to voltage-controlled oscillator 14 for frequency control.

[0026] When charge pump 12 outputs an electrical signal to filter 13 based on the comparison result, charge mismatch occurs in the output signal due to factors such as charge sharing among internal components and channel modulation effects. If the signal is directly output to filter 13, the entire phase-locked loop circuit 10 will have poor phase noise. Therefore, to eliminate the charge mismatch in the output signal of charge pump 12, digital-to-analog converter 1B and delay unit 1A are commonly used in phase-locked loop circuit 10 to neutralize and match the charge in the output signal of charge pump 12.

[0027] Under the action of the drive signal Div, the delay unit 1A can adjust the feedback signal F output by the frequency divider 15. ck Perform a delay and obtain the delay feedback signal F ck The _d output is sent to the frequency and phase detector 11, causing the delayed feedback signal F to... ck _d phase and reference signal F ref Phase alignment is achieved. The frequency-phase detector 11 can output a corresponding phase difference signal to the charge pump 12 based on the phase difference between the two, and the charge pump 12 can output an electrical signal to the filter 13. Due to the charge mismatch phenomenon in the electrical signal output by the charge pump unit 12, the electrical signal of the charge pump unit 12 and the electrical signal of the filter 13 are inconsistent in magnitude. According to Kirchhoff's current law, the digital-to-analog converter 1B can output a corresponding electrical signal to balance the electrical signal of the charge pump 12 and the electrical signal of the filter 13, thereby eliminating the charge mismatch phenomenon of the charge pump 12.

[0028] However, during the charge matching process, the current magnitudes of the charge pump unit and the digital-to-analog converter unit will change. It is necessary to ensure precise matching between the charge pump unit and the digital-to-analog converter at all times in order to eliminate the charge mismatch phenomenon of the charge pump unit.

[0029] To address the aforementioned issues, in this embodiment of the invention, charge matching of the charge pump unit can be achieved by coupling a charge neutralization unit between the charge pump unit and the digital-to-analog converter unit. Specifically, under the influence of a first electrical signal, an enable signal, and a power supply, the charge neutralization unit can store the charge corresponding to the first electrical signal, generate a second electrical signal, and store the charge corresponding to the second electrical signal. When the charges corresponding to the first and second electrical signals are equal, the second electrical signal is output to the digital-to-analog converter unit, which converts the type of the second electrical signal and outputs the resulting third electrical signal to the loop filter. Since the charge neutralization unit outputs the second electrical signal to the digital-to-analog converter unit when the charges corresponding to the first and second electrical signals are equal, and the digital-to-analog converter unit converts the type of the second electrical signal and outputs the resulting third electrical signal to the loop filter, charge matching of the charge pump unit can be achieved through the superposition of the first and third electrical signals, thereby improving the phase noise performance of the phase-locked loop circuit.

[0030] To enable those skilled in the art to better understand and implement the embodiments of the present invention, the following describes the concept, scheme, principle, and advantages of the embodiments of the present invention in detail with reference to the accompanying drawings and through specific application examples.

[0031] Reference Figure 2 The schematic diagram shown is of a phase-locked loop circuit in one embodiment of the present invention. In some embodiments of the present invention, the phase-locked loop circuit 20 may include: a frequency and phase discrimination unit 21, a charge pump unit 22, a charge neutralization unit 23, a digital-to-analog converter unit 24, a loop filter 25, a voltage-controlled oscillator 26, and a feedback unit 27, wherein:

[0032] The frequency and phase discrimination unit 21 is coupled to the feedback unit 27 and the charge pump unit 22, respectively, and is adapted to compare the received reference signal F at the input terminal of the phase-locked loop circuit 20. r and the feedback signal F output by the feedback unit 27 b The phase difference signal and the enable signal are output to the charge pump unit 22.

[0033] The charge pump unit 22 is coupled to the loop filter 25 and the charge neutralization unit 23 respectively, and is adapted to convert the phase difference signal into a first electrical signal, and output the first electrical signal and the enable signal to the charge neutralization unit 23, and output the first electrical signal to the loop filter 25;

[0034] The charge neutralization unit 23 is connected to the power source ( Figure 2 (Not shown) The digital-to-analog converter 24 is coupled to the first electrical signal, the enable signal and the power supply, respectively, and is adapted to store the charge corresponding to the first electrical signal and generate the second electrical signal, and store the charge corresponding to the second electrical signal, and output the second electrical signal to the digital-to-analog converter 24 when the first charge and the second charge are equal.

[0035] The digital-to-analog converter 24 is coupled to the loop filter 25 and is adapted to convert the type of the second electrical signal and output the resulting third electrical signal to the loop filter 25.

[0036] The loop filter 25 is coupled to the voltage-controlled oscillator 26 and is adapted to filter the first electrical signal and the third electrical signal and output them to the voltage-controlled oscillator 26.

[0037] The voltage-controlled oscillator 26 is adapted to generate and output an output signal of a corresponding frequency under the control of the first electrical signal and the third electrical signal;

[0038] The feedback unit 27 is coupled to the voltage-controlled oscillator 26 and is adapted to generate the feedback signal F according to the output signal. b And output it to the frequency and phase discrimination unit 21.

[0039] Using the aforementioned phase-locked loop circuit 20, the frequency and phase discrimination unit 21 determines the feedback signal F output by the feedback unit 25. b and the reference signal F at the input terminal of the phase-locked loop circuit 20 r The phase difference signal and the enable signal are output to the charge pump unit 22. The charge pump unit 22 outputs the first electrical signal obtained according to the phase difference signal to the charge neutralization unit 23 and the loop filter 25 respectively, and outputs the enable signal to the charge neutralization unit 23.

[0040] Under the action of the first electrical signal, the enable signal and the power supply, the charge neutralization unit 23 can store the charge corresponding to the first electrical signal, generate the second electrical signal, store the charge corresponding to the second electrical signal, and output the second electrical signal to the digital-to-analog conversion unit 24 when the charge corresponding to the first electrical signal and the charge corresponding to the second electrical signal are equal.

[0041] The digital-to-analog converter 24 can convert the type of the second electrical signal and output the resulting third electrical signal to the loop filter 25. After the first electrical signal and the third electrical signal are processed by the loop filter 25 and the voltage-controlled oscillator 26, an output signal of the corresponding frequency is generated and output.

[0042] Since the charge neutralization unit 23 outputs the second electrical signal to the digital-to-analog converter 24 when the charge corresponding to the first electrical signal and the charge corresponding to the second electrical signal are the same, and the digital-to-analog converter 24 converts the type of the second electrical signal and outputs the resulting third electrical signal to the loop filter 25, the charge matching of the charge pump unit 22 can be achieved by superimposing the first electrical signal and the third electrical signal.

[0043] In specific implementations, depending on different application scenarios, the electrical signal may include a current signal and a voltage signal. In this embodiment of the invention, the electrical signal is a current signal.

[0044] In some embodiments of the present invention, the feedback unit 27 may include a frequency divider for dividing the output signal to obtain a feedback signal with the same frequency as the input signal. The frequency divider functions to convert the output signal of the voltage-controlled oscillator (VCO) into a signal with the same frequency as the input signal. Wherein, if the frequency of the input signal is set to fin and the frequency of the output signal is set to fout, then fin = N × fout, where N > 1. N corresponds to the frequency division parameter of the frequency divider. For example, if N is 2, the frequency divider is a divide-by-two frequency divider; if N is 4, the frequency divider is a divide-by-four frequency divider.

[0045] To enable those skilled in the art to better understand and implement the embodiments of the present invention, some specific examples of the specific implementation methods of the charge neutralization unit in the embodiments of the present invention are given below.

[0046] Reference Figure 3 The schematic diagram shown in this embodiment of the invention illustrates the structure of a charge neutralization unit 30, wherein the charge neutralization unit 30 includes: a first current mirror module 31, a first switch module 32, a charge neutralization module 33, a second switch module 34, and a second current mirror module 35, wherein:

[0047] The first current mirror module 31 has its first end coupled to the power supply VDD through the charge pump unit 3A, and its third end grounded, which is suitable for mirroring the first electrical signal output by the charge pump unit 3A to the second end of the first current mirror module.

[0048] The first switch module 32 has its first end coupled to the second end of the first charge neutralization module 33 and its second end coupled to the charge pump unit 3A. It is adapted to be coupled to the second end of the first current mirror module 31 under the control of the enable signal to turn on or off the first charging branch.

[0049] The first charge neutralization module 33 has a first terminal coupled to the power supply VDD and a fourth terminal coupled to the charge pump unit 3A. It is adapted to output a corresponding first control signal to the second switch module 34 according to the voltage of its first and second terminals and the enable signal; and is adapted to store the first charge corresponding to the first electrical signal when the first charging branch is turned on; and is adapted to generate the second electrical signal and store the second charge corresponding to the second electrical signal when the second charging branch is turned on.

[0050] The second switch module 34 has a first terminal adapted to be coupled to the second or third terminal of the first charge neutralization module 33 according to the first control signal, so as to turn on or off the second charging branch;

[0051] The second current mirror module 35 has its first end coupled to the power supply VDD, its second end coupled to the second end of the second switch module 34, and its third end grounded through the digital-to-analog converter unit 3B. It is adapted to mirror the second electrical signal to the digital-to-analog converter unit 3B when the second charging branch is turned on.

[0052] When the phase-locked loop circuit is working, the charge pump unit 3A outputs a first electrical signal and an enable signal to the charge neutralization unit 30. When the enable signal is high, the first switch module 32 can be coupled to the second terminal of the first current mirror module 31. On one hand, the first electrical signal output by the charge pump unit 3A can be mirrored to the second terminal of the first current mirror module 31 via the first terminal; on the other hand, a first charging branch is formed between the power supply VDD, the charge neutralization module 33, the first switch module 32, the first current mirror module 31, and ground. Under the action of the power supply VDD and the first electrical signal, the charge neutralization module 33 can store the charge corresponding to the first electrical signal.

[0053] Since the first control signal output by the charge neutralization unit 33 is at a low level, the first terminal of the second switch module 34 is coupled to the third terminal of the charge neutralization module 33, and the second charging branch is still in the open state.

[0054] When the enable signal of the charge pump unit 3A is low, the first switch module 32 is disconnected from the second terminal of the first current mirror module 31, the first charging branch is disconnected, the first control signal output by the first charge neutralization module 33 is high, and the first terminal of the second switch module 34 is connected to the second terminal of the charge neutralization module 33 under the action of the first control signal. On one hand, a second charging branch is formed between the power supply VDD, the second current mirror module 34, the second switch module 34 and the charge neutralization module 33. Under the action of the power supply VDD, the charge neutralization module 33 can generate a second electrical signal corresponding to the first electrical signal and store the charge corresponding to the second electrical signal. On the other hand, when the charge corresponding to the first electrical signal is equal to the charge corresponding to the second electrical signal, the second current mirror module 35 mirrors the second electrical signal at its third terminal to the digital-to-analog converter unit 3B, and the digital-to-analog converter unit 3B converts the type of the second electrical signal and outputs the obtained third electrical signal.

[0055] In some embodiments of the present invention, as specific examples, reference continues to be made. Figure 3 The first current mirror module 31 may include a first transistor NM1 and a second transistor NM2, wherein:

[0056] The first transistor NM1 has its gate and drain connected, and is connected to the gate of the second transistor NM2, serving as the first terminal of the first current mirror module 31; its source is connected to the source of the second transistor NM2, serving as the third terminal of the first current mirror module 31.

[0057] The drain of the second transistor NM2 serves as the second terminal of the first current mirror module 31.

[0058] In a specific implementation, the current mirror ratio of the first current mirror module 31 can be 1:1, that is, the electrical signal mirrored to the charge neutralization module 33 is the same as the first electrical signal output by the charge pump to the charge neutralization unit 30.

[0059] As a specific example, continue to refer to Figure 3 The second current mirror module 35 may include a third transistor PM3 and a fourth transistor PM4, wherein:

[0060] The third transistor PM3 has its gate and drain connected, and is connected to the gate of the fourth transistor PM2, serving as the third terminal of the second current mirror module 35; its source is connected to the source of the fourth transistor PM4, serving as the first terminal of the second current mirror module 35.

[0061] The drain of the fourth transistor PM4 serves as the second terminal of the second current mirror module 35.

[0062] In a specific implementation, the current mirror ratio of the second current mirror module 34 can be 1:1, that is, the electrical signal mirrored to the digital-to-analog conversion unit 3B is the same as the second electrical signal generated by the charge neutralization module 33.

[0063] As a specific example, continue to refer to Figure 3 The charge neutralization module 33 may include a voltage regulator 331, a capacitor C, a comparator CMP, a first inverter P1, and an AND gate 332, wherein:

[0064] The voltage regulator 331 has a first terminal that serves as the first terminal of the charge neutralization module 33, and a second terminal that is coupled to the first terminal of the comparator CMP.

[0065] The capacitor C is coupled between the first and second terminals of the comparator CMP;

[0066] The comparator CMP has its second terminal serving as the second terminal of the charge neutralization module 33, and its output terminal is coupled to the first terminal of the AND gate 332.

[0067] The first inverter P1 has its input terminal serving as the fourth terminal of the charge neutralization module, and its output terminal is coupled to the second terminal of the AND gate 332.

[0068] The output terminal of AND gate 332 is coupled to the second terminal of the second switch module 34.

[0069] In some embodiments of the present invention, the first switching module 32 can be a first transmission gate, wherein the first control terminal of the first transmission gate (e.g., the gate of an NMOS transistor) can be coupled to the charge pump unit 3A, its second control terminal (e.g., the gate of a CMOS transistor) can be grounded, its input terminal can be coupled to the second terminal of the comparator CMP, and its output terminal can be coupled to the source of the second transistor NM2. When the enable signal Φ is high, the first transmission gate is fully turned on, and the first charging branch is turned on; when the enable signal Φ is low, the first transmission gate is turned off, and the first charging branch is turned off.

[0070] The second switching module 34 can be a second transmission gate, wherein the first control terminal of the second transmission gate (e.g., the gate of an NMOS transistor) can be coupled to the output terminal of the AND gate 332, its second control terminal (e.g., the gate of a CMOS transistor) can be grounded, its input terminal can be coupled to the second terminal of the comparator CMP, and its output terminal can be coupled to the drain of the fourth transistor PM4. When the first control signal is high, the second transmission gate is fully turned on, and the second charging branch is turned on; when the first control signal is low, the second transmission gate is turned off, and the second charging branch is turned off.

[0071] In some other embodiments of the present invention, the first switching module and the second switching module may also be switching transistors such as MOSFETs, transistors, IGBTs, or other switching circuits.

[0072] In some embodiments of the present invention, in order to prevent the first charging branch and the second charging branch from being mis-connected due to the first switching module 32 and the second switching module 34, resulting in a large current and thus burning out the circuit, the charge neutralization module 33 may further include a resistor R, coupled between the second terminal of the voltage regulator 331 and the first terminal of the comparator CMP, which is suitable for limiting the current of the first charging branch and the second charging branch.

[0073] To enable those skilled in the art to better understand and implement the embodiments of the present invention, the charge adaptation process of the phase-locked loop circuit is described in detail below with reference to the accompanying drawings and in conjunction with specific application scenarios.

[0074] Combination Figure 3 , refer to Figure 4 The diagram shown illustrates the timing variation waveforms of key nodes in the charge neutralization unit in this embodiment of the invention. Figure 4 The charge value Q of capacitor C and the voltage change across it, as well as the output voltage U of comparator CMP, are shown respectively. out Voltage changes.

[0075] From time 0 to t1, the phase-locked loop circuit is in a steady state, the voltages across comparator CMP are the same, and its output voltage U is... out The voltage U across capacitor C is 0. C Since the value is 0, the corresponding charge value Q of capacitor C is 0.

[0076] Between time t1 and t2, the first electrical signal output by charge pump unit 3A to charge neutralization unit 30 exhibits charge mismatch, and charge neutralization unit 30 begins to operate.

[0077] When the enable signal Φ is high, the second terminal of the first switching module 32 can be connected to the source of the second transistor NM2. The first electrical signal output by the charge pump unit 3A can be mirrored from the source of the first transistor NM1 in the first current mirror module 31 to the source of the second transistor NM2. The power supply VDD, the voltage regulator 331, the resistor R, the capacitor C, the first switching module 32, the fourth transistor NM2, and ground are turned on, forming the first charging branch. Under the action of the power supply VDD and the first electrical signal, the power supply VDD can charge the capacitor C. Figure 4 As shown, the voltage difference between the first and second terminals of the capacitor C gradually increases, and its voltage U C It is greater than 0, and the charge value Q1 corresponding to the first electrical signal is stored.

[0078] At this time, the voltage at the first terminal of capacitor C is greater than the voltage at its second terminal, that is, the voltage at the first terminal of comparator CMP is greater than the voltage at its second terminal, and the voltage U output by comparator CMP is... out The signal is at a high level, but the enable signal Φ is output to the AND gate 332 via the first inverter P1. When the level is low, the first control signal output by AND gate 332 is low, the first terminal of the second switch module S2 is connected to the output terminal of AND gate 332, and the second charging branch is in the open state.

[0079] From time t2 to t3, the enable signal Φ output by the charge pump unit jumps to a low level, the second terminal of the first switching module 32 is disconnected from the second transistor NM2, the first charging branch is disconnected, but the voltage U across capacitor C remains constant. C It is still greater than 0. That is, the voltage at the first terminal of comparator CMP is still greater than the voltage at its second terminal, and the voltage U output by comparator CMP is... out The signal is at a high level, and because the enable signal Φ is output to the AND gate 332 via the first inverter P1. When the first control signal output by AND gate 332 is high, the first terminal of the second switching module is connected to the second terminal of comparator CMP under the action of the first control signal. The power supply VDD, the fourth transistor PM4, the second switching module 34, the capacitor C, the resistor R and the voltage regulator 331 form the second charging branch.

[0080] Under the action of power supply VDD, on the one hand, the charge neutralization module 33 can generate a second electrical signal on the second charging branch, and the capacitor C stores the charge value Q2 corresponding to the second electrical signal; on the other hand, the second electrical signal can be mirrored to the digital-to-analog converter unit 3B through the drain of the fourth transistor PM4 in the second current mirror module 35.

[0081] Since the charging directions of the first charging branch and the second charging branch are opposite, therefore... Figure 4 As shown, the voltage difference between the first and second terminals of capacitor C gradually decreases, and the voltage U of capacitor C... C The value is still greater than 0, and the capacitor C continues to store the charge value Q2 corresponding to the second electrical signal, but the direction of Q2 is opposite to that of Q1.

[0082] like Figure 4 As shown, at time t3, the voltage at the first terminal of capacitor C is the same as the voltage at the second terminal, and is 0. That is, when the charge Q1 corresponding to the first electrical signal is the same as the charge Q2 corresponding to the second electrical signal, the voltage U output by comparator CMP is... outWhen the value equals 0, the first control signal output by AND gate 332 is at a low level. Under the action of the first control signal, the first terminal of the second switch module 34 is connected to the output terminal of AND gate 332, the second charging branch is disconnected, and the mirroring of the second current signal to the digital-to-analog converter unit 3B is stopped, thereby completing the charge adaptation process.

[0083] During the period from t4 to t7, the operation of the charge neutralization module is described above in the description of the period from t1 to t3, and will not be described again here.

[0084] In this embodiment of the invention, the charge neutralization unit can generate a second electrical signal corresponding to the first electrical signal when a charge mismatch occurs in the first electrical signal output by the charge pump unit, and store the charge corresponding to the first electrical signal and the charge corresponding to the second electrical signal. When the charges of the two are the same, the generated second electrical signal is output to the digital-to-analog conversion unit to complete the charge adaptation process.

[0085] Reference Figure 5 The diagram shown is a schematic of the phase noise curves of the charge pump circuit under different states in the embodiment of the present invention. The horizontal axis represents the frequency shift and the vertical axis represents the phase noise, with the unit being dBc.

[0086] Depend on Figure 5 It can be seen that during the frequency shift process of the charge pump circuit, the phase noise peak of curve A, when neither the charge pump neutralization unit nor the digital-to-analog converter unit is activated, is large and the change amplitude is large, indicating poor phase noise performance of the charge pump circuit. Compared with phase noise curve A, the phase noise peak of curve B, when the charge pump neutralization unit is not activated and the digital-to-analog converter unit is activated, is reduced, but the change amplitude is still large, indicating some improvement in the phase noise of the charge pump circuit. Compared with phase noise curves A and B, the phase noise peak of curve C, when both the digital-to-analog converter unit and the charge neutralization unit are activated, is the lowest and the amplitude change is stable, indicating improved phase noise of the charge pump circuit.

[0087] In practical implementation, if the first electrical signal output by the charge pump unit is small, directly outputting the first electrical signal to the charge neutralization unit for charge matching may result in an inconspicuous charge transformation process in the charge neutralization unit. In some embodiments of the present invention, the first electrical signal output by the charge pump unit to the charge neutralization unit can be amplified, and the charge neutralization unit can perform a charge matching process on the amplified electrical signal.

[0088] In specific implementation, refer to Figure 6 The schematic diagram shown in this embodiment of the invention illustrates another charge neutralization unit, as follows: Figure 6As shown, the charge pump neutralization unit 60 may include: a third current mirror module 61, a clamping module 62, a third switch module 63, a charge neutralization module 64, a second switch module 65, and a second current mirror module 66, wherein:

[0089] The third current mirror module 61 has a first terminal coupled to the power supply VDD, a second terminal grounded through the charge pump unit 6A, a third terminal grounded, a fourth terminal coupled to the first terminal of the clamping module 62, and a fifth terminal coupled to the first terminal of the third switch module 63 and the second terminal of the clamping module 62, respectively. It is adapted to mirror the first current signal output by the charge pump unit 6A to the fifth terminal of the third current mirror module 61.

[0090] The output terminal of the clamping module 62 is coupled to the second terminal of the third switching module 63, which is suitable for making the voltages of the fourth and fifth terminals of the third current mirror module 61 the same.

[0091] The third switch module 63 has its third terminal coupled to ground, its fourth terminal coupled to the second terminal of the second charge neutralization module 64, and its fifth and sixth terminals coupled to the charge pump unit 6A, respectively. It is adapted to turn on or off the first charging branch under the control of the enable signal.

[0092] The charge neutralization module 64 has a first terminal coupled to the power supply VDD and a fourth terminal coupled to the charge pump unit 6A. It is adapted to output a corresponding second control signal to the second switch module 66 based on the voltage of its first and second terminals and the enable signal; and is adapted to store the first charge corresponding to the first electrical signal when the first charging branch is turned on; and is adapted to generate the second electrical signal and store the second charge corresponding to the second electrical signal when the second charging branch is turned on.

[0093] The second switch module 65 has a first terminal adapted to be coupled to the second or third terminal of the charge neutralization module 64 according to the second control signal, so as to turn on or off the second charging branch.

[0094] The second current mirror module 66 has its first end coupled to the power supply VDD, its second end coupled to the second end of the second switch module 65, and its third end grounded through the digital-to-analog converter unit 6B. It is adapted to mirror the second electrical signal to the digital-to-analog converter unit 6B when the second charging branch is turned on.

[0095] In the implementation of this invention, reference will continue to be made to... Figure 6 The third current mirror module 61 may include a first current mirror 611, a second current mirror 612, and a third current mirror 613, wherein:

[0096] The first current mirror 611 has a first end serving as the first end of the third current mirror module 61, a second end serving as the second end of the third current mirror module 61, a third end coupled to the first end of the second current mirror 612, and a fourth end coupled to the second end of the second current mirror 612 and the first end of the third current mirror 613.

[0097] The second current mirror 612 has its third end coupled to the second end of the third current mirror 613 and serves as the fourth end of the third current mirror module 61. Its fourth end is coupled to the third end of the third current mirror 613 and serves as the third end of the third current mirror module 613.

[0098] The fourth end of the third current mirror 613 serves as the fifth end of the third current mirror module 61.

[0099] As a specific example, continue to refer to Figure 6 The first current mirror 611 may include a fifth transistor PM5, a sixth transistor PM6, and a seventh transistor PM7, wherein:

[0100] The source of the fifth transistor PM5 is coupled to the sources of the sixth transistor PM6 and the seventh transistor PM7, serving as the first terminal of the first current mirror 611. Its gate is coupled to the gate of the sixth transistor PM6, the gate of the seventh transistor PM7, and the drain, serving as the second terminal of the first current mirror 611. Its drain serves as the fourth terminal of the first current mirror 611.

[0101] The drain of the sixth transistor PM6 serves as the third terminal of the first current mirror 611.

[0102] In a specific implementation, the current mirror ratio of the first current mirror 611 can be N1:1:1, that is, the area ratio of the PN junctions of the fifth transistor PM5, the sixth transistor PM6 and the seventh transistor PM7 is N1:1:1, where N1 is an integer greater than 1.

[0103] The second current mirror 612 includes an eighth transistor NM8 and a ninth transistor NM9, wherein:

[0104] The eighth transistor NM8 has its drain serving as the second terminal of the second current mirror 612, its gate being coupled to the gate and drain of the ninth transistor NM9, serving as the first terminal of the second current mirror 612, and its source serving as the third terminal of the first current mirror module 61.

[0105] The source of the ninth transistor PM9 serves as the fourth terminal of the second current mirror 612.

[0106] In a specific implementation, the current mirror ratio of the second current mirror 612 can be 1:1, that is, the ratio of the PN junction area of ​​the eighth transistor NM8 and the ninth transistor NM9 is 1:1.

[0107] The third current mirror 613 may include a tenth transistor NM10 and an eleventh transistor NM11, wherein:

[0108] The drain of the tenth transistor NM10 serves as the second terminal of the third current mirror 613, its gate is coupled to the gate of the eleventh transistor NM11, serving as the first terminal of the third current mirror 613, and its source is coupled to the source of the eleventh transistor NM11, serving as the third terminal of the third current mirror 613.

[0109] The drain of the eleventh transistor NM11 serves as the fourth terminal of the third current mirror 613.

[0110] In a specific implementation, the current mirror ratio of the third current mirror 613 can be N2:1, that is, the ratio of the PN junction areas of the tenth transistor NM10 and the eleventh transistor NM11 is N2:1, where N2 is an integer greater than 1.

[0111] In the implementation of this invention, reference will continue to be made to... Figure 6 As a specific example, the third switch module 63 includes a first switch S1, a second switch S2, a twelfth transistor NM12, and a second inverter P2, wherein:

[0112] The first switch S1 has its first end coupled to the gate of the twelfth transistor NM12 and the first end of the second switch S2, respectively. Its second end serves as the fifth end of the third switch module 63 and is adapted to be coupled to the second end of the third switch module 63 when the enable signal is high, thereby turning on the first charging branch.

[0113] The second inverter P2 has its input terminal coupled to the charge pump unit 6A and its output terminal coupled to the second terminal of the second switch S2.

[0114] The second switch S2 has its first terminal coupled to the gate of the twelfth transistor NM12, adapted to be grounded when the enable signal is low, and coupled to the third terminal of the third switch module 63 to disconnect the first charging branch.

[0115] The twelfth transistor NM12 has its source serving as the first terminal of the third switching module 63 and its drain serving as the fourth terminal of the third switching module 63.

[0116] As a specific example, continue to refer to Figure 6The second current mirror module 66 includes a third transistor PM3 and a fourth transistor PM4, wherein:

[0117] The gate of the third transistor PM3 is connected to the drain and is also connected to the gate of the fourth transistor PM2, serving as the third terminal of the second current mirror module 66; its source is connected to the source of the fourth transistor PM4, serving as the first terminal of the second current mirror module 66.

[0118] The drain of the fourth transistor PM4 serves as the second terminal of the second current mirror module 66.

[0119] In a specific implementation, the current mirror ratio of the second current mirror module 66 can be M:1, that is, the ratio of the PN junction area of ​​the third transistor PM3 and the fourth transistor PM4 is M:1, where M can be equal to N1*N2, and M is an integer greater than 1.

[0120] As a specific example, continue to refer to Figure 6 The charge neutralization module 64 may include a voltage regulator 641, a capacitor C, a comparator CMP, an AND gate 642, and a first inverter P1, wherein:

[0121] The voltage regulator 641 has a first terminal that serves as the first terminal of the charge neutralization module 64, and a second terminal that is coupled to the first terminal of the comparator CMP.

[0122] The capacitor C is coupled between the first and second terminals of the comparator CMP;

[0123] The comparator CMP has its second terminal serving as the second terminal of the charge neutralization module 64, and its output terminal is coupled to the first terminal of the AND gate 642.

[0124] The first inverter P1 has its input terminal serving as the fourth terminal of the charge neutralization module 64, and its output terminal is coupled to the second terminal of the AND gate 642.

[0125] The output terminal of the AND gate 642 is coupled to the first terminal of the second switch module 65.

[0126] In this embodiment of the invention, the limiting module 62 can be an operational amplifier. When the potentials at its two ends are the same, it can eliminate the channel modulation effect of the twelfth transistor NM12 and improve the stability of the second electrical signal generated on resistor R2.

[0127] In some embodiments of the present invention, the first switch S1 may be a first transmission gate, wherein the first control terminal of the first transmission gate (e.g., the gate of an NMOS transistor) may be coupled to the charge pump unit, its second control terminal (e.g., the gate of a CMOS transistor) may be grounded, its input terminal may be coupled to the output terminal of the limit module 62, and its output terminal may be coupled to the gate of the twelfth transistor NM12. When the enable signal Φ is high, the first transmission gate is fully turned on, and the first charging branch is turned on; when the enable signal Φ is low, the first transmission gate is turned off, and the first charging branch is turned off.

[0128] The second switch S2 can be a second transmission gate, wherein the first control terminal of the second transmission gate (e.g., the gate of an NMOS transistor) can be coupled to the output terminal of the second inverter P2, and its second control terminal (e.g., the gate of a CMOS transistor) can be grounded. When the enable signal Φ is low, the second transmission gate is fully turned on, and the first charging branch is turned off; when the enable signal Φ is high, the first transmission gate is turned off, and the first charging branch is turned on.

[0129] The second switching module 65 can be a third transmission gate, wherein the first control terminal of the second transmission gate (e.g., the gate of an NMOS transistor) can be coupled to the output terminal of the second AND gate 642, its second control terminal (e.g., the gate of a CMOS transistor) can be grounded, its input terminal can be coupled to the drain of the fourteenth transistor PM14, and its output terminal can be coupled to the second terminal of the comparator CMP. When the second control signal is high, the second transmission gate is fully turned on, and the second charging branch is turned on; when the second control signal is low, the second transmission gate is turned off, and the second charging branch is turned off.

[0130] In some other embodiments of the present invention, the first switch, the second switch, and the second switch module may also be switching transistors such as MOSFETs, transistors, IGBTs, or other switching circuits.

[0131] In some embodiments of the present invention, in order to prevent the first charging branch and the second charging branch from being mis-connected due to the third switch module 63 and the second switch module 65, resulting in a large current and thus burning out the circuit, the charge neutralization module 64 may further include a second resistor R, coupled between the second terminal of the voltage regulator 631 and the first terminal of the comparator CMP, which is suitable for limiting the current of the first charging branch and the second charging branch.

[0132] When the enable signal Φ is high, the first electrical signal E1 output by the charge pump unit 6A to the charge neutralization unit 60 is amplified by the first current mirror 611, and the first mirrored electrical signal output by the drain of the fifth transistor PM5 is N1*E1. After being amplified by the second current mirror 612, the resulting second mirrored electrical signal N1*E1 is output to the first terminal of the clamping module 62. Since the voltage at the second terminal of the clamping module 62 is zero, the level output by the clamping module 62 is high. Meanwhile, since the enable signal Φ is high, the second terminal of the second switch S2 is coupled to the output terminal of the second inverter P2, and the second terminal of the first switch S1 can be coupled to the output terminal of the limit module 62. Therefore, the gate of the twelfth transistor NM12 is high, and the twelfth transistor NM12 is turned on. This connects the power supply VDD, the voltage regulator 641, the resistor R, the capacitor C, the twelfth transistor NM12, and the eleventh transistor NM11, forming the first charging branch. Simultaneously, the second mirror signal N1*E1 is mirrored to the drain of the eleventh transistor NM11 via the third current mirror 613, resulting in the third mirror signal N1*N2*E1. Under the influence of the power supply VDD and the third mirror signal N1*N2*E1, the power supply VDD can charge the capacitor C and store the charge corresponding to the third mirror signal N1*N2*E1.

[0133] At this time, due to the signal at the second terminal of AND gate 642 When the signal is low, the second control signal output by the AND gate 642 is low, the first terminal of the second switch module 65 is still coupled to the output terminal of the AND gate 642, and the second charging branch is in the open state.

[0134] During the charging process of capacitor C by power supply VDD, the voltage at the second terminal of clamping module 62 gradually increases. When it is the same as the voltage at its first terminal, the output level of clamping module 62 is low, that is, the gate of the twelfth transistor NM12 is low, the twelfth transistor NM12 is turned off, and the first charging branch is disconnected.

[0135] When the enable signal Φ is low, the second terminal of the second switch S2 is grounded, the gate of the twelfth transistor NM12 is low, the first charging branch is in the open state, but the voltage U across the capacitor C remains low. C It is still greater than 0. That is, the voltage at the first terminal of comparator CMP is greater than the voltage at the second terminal. The signal output by comparator CMP to the first terminal of AND gate 642 is high, and because the signal at the second terminal of AND gate 642 is also high... When the signal is high, the second control signal output by the AND gate 642 is high, and the first terminal of the second switch module 65 can be coupled to the second terminal of the comparator CMP. The power supply VDD, the fourth transistor PM4, the second switch module 65, the capacitor C, the resistor R, and the voltage regulator 641 are connected to form the second charging branch.

[0136] Under the influence of power supply VDD, on the one hand, the charge neutralization module 64 can generate a second electrical signal E2 corresponding to the third mirror electrical signal N1*N2*E1 on the second charging branch, and the capacitor C stores the charge corresponding to the second electrical signal E2; on the other hand, the second electrical signal E2 can be mirrored to the digital-to-analog converter unit 6B through the drain of the fourth transistor PM4 in the second current mirror module 66 to obtain a fourth mirror electrical signal E2 / M. The digital-to-analog converter unit 6B converts the type of the fourth mirror electrical signal E2 / M and uses it as the third electrical signal. Since the charging directions of the second charging branch and the first charging branch are opposite, the voltage difference between the first and second terminals of the capacitor C gradually decreases, and the capacitor C continues to store the charge corresponding to the second electrical signal, but its direction is opposite to the direction of the charge corresponding to the first electrical signal stored in the capacitor C.

[0137] The power supply VDD continues to charge capacitor C along the second charging branch. When the voltage at the first terminal and the voltage at the second terminal of capacitor C are the same, that is, when the charge corresponding to the first electrical signal is the same as the charge corresponding to the second electrical signal, the signal output by comparator CMP to AND gate 642 is low. The level of the second control signal output by AND gate 642 is low. The first terminal of the second switch module 65 is coupled to the output terminal of AND gate 642, the second charging branch is disconnected, and the charge adaptation process is completed.

[0138] It should be noted that the term "an embodiment" or "embodiment" as used in this invention refers to a specific feature, structure, or characteristic that can be included in at least one implementation of the invention. Furthermore, in the description of this invention, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with terms such as "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance. It is understood that such terms can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0139] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A phase-locked loop circuit, characterized in that, include: The system includes a frequency and phase detector unit, a charge pump unit, a charge neutralization unit, a digital-to-analog converter unit, a loop filter, a voltage-controlled oscillator, and a feedback unit, among which: The frequency and phase discrimination unit is coupled to the feedback unit and the charge pump unit respectively, and is adapted to compare the phase of the received reference signal at the input terminal of the phase-locked loop circuit and the phase of the feedback signal output by the feedback unit, and output the corresponding phase difference signal and enable signal to the charge pump unit. The charge pump unit is coupled to the loop filter and the charge neutralization unit respectively, and is adapted to convert the phase difference signal into a first electrical signal, and output the first electrical signal and the enable signal to the charge neutralization unit, and output the first electrical signal to the loop filter; The charge neutralization unit is coupled to the power supply and the digital-to-analog conversion unit respectively. It is adapted to store the first charge corresponding to the first electrical signal and generate the second electrical signal under the action of the first electrical signal, the enable signal and the power supply, and store the second charge corresponding to the second electrical signal. When the first charge and the second charge are equal, the second electrical signal is output to the digital-to-analog conversion unit. The digital-to-analog converter unit is coupled to the loop filter and is adapted to convert the type of the second electrical signal and output the resulting third electrical signal to the loop filter; The loop filter is coupled to the voltage-controlled oscillator and is adapted to filter the first electrical signal and the third electrical signal, and output to the voltage-controlled oscillator. The voltage-controlled oscillator is adapted to generate and output an output signal of a corresponding frequency under the control of the first electrical signal and the third electrical signal; The feedback unit is coupled to the voltage-controlled oscillator and is adapted to generate the feedback signal based on the output signal and output it to the frequency and phase discrimination unit.

2. The phase-locked loop circuit according to claim 1, characterized in that, The charge neutralization unit includes: a first current mirror module, a first switch module, a charge neutralization module, a second current mirror module, and a second switch module, wherein: The first current mirror module has a first terminal coupled to the power supply through the charge pump unit and a third terminal grounded, which is suitable for mirroring the first electrical signal output by the charge pump unit to the second terminal of the first current mirror module. The first switching module has a first terminal coupled to the second terminal of the first charge neutralization module and a second terminal coupled to the charge pump unit. It is adapted to be coupled to the second terminal of the first current mirror module under the control of the enable signal to turn on or off the first charging branch. The charge neutralization module has a first terminal coupled to the power supply and a fourth terminal coupled to the charge pump unit. It is adapted to output a corresponding first control signal to the second switch module according to the voltage of its first and second terminals and the enable signal; and is adapted to store a first charge corresponding to the first electrical signal when the first charging branch is turned on; and is adapted to generate a second electrical signal and store a second charge corresponding to the second electrical signal when the second charging branch is turned on. The second switching module has a first terminal adapted to be coupled to the second or third terminal of the first charge neutralization module according to the first control signal, so as to turn on or off the second charging branch; The second current mirror module has a first end coupled to the power supply, a second end coupled to the second end of the second switch module, and a third end grounded through the digital-to-analog converter unit. It is adapted to mirror the second electrical signal to the digital-to-analog converter unit when the second charging branch is turned on.

3. The phase-locked loop circuit according to claim 2, characterized in that, The first current mirror module includes a first transistor and a second transistor, wherein: The first transistor has its gate and drain connected, and is also connected to the gate of the second transistor, serving as the first terminal of the first current mirror module; its source is connected to the source of the second transistor, serving as the third terminal of the first current mirror module. The drain of the second transistor serves as the second terminal of the first current mirror module.

4. The phase-locked loop circuit according to claim 1, characterized in that, The charge neutralization unit includes a third current mirror module, a clamping module, a third switch module, a charge neutralization module, a second current mirror module, and a second switch module, wherein: The third current mirror module has a first terminal coupled to the power supply, a second terminal grounded through the charge pump unit, a third terminal grounded, a fourth terminal coupled to the first terminal of the clamping module, and a fifth terminal coupled to the first terminal of the third switch module and the second terminal of the clamping module, respectively, and is adapted to mirror the first electrical signal output by the charge pump unit to the fifth terminal of the third current mirror module. The clamping module has its output terminal coupled to the second terminal of the third switching module, which is suitable for making the voltages of the fourth and fifth terminals of the third current mirror module the same. The third switch module has its third terminal coupled to ground, its fourth terminal coupled to the second terminal of the charge neutralization module, and its fifth and sixth terminals coupled to the charge pump unit, respectively, and is adapted to turn on or off the first charging branch under the control of the enable signal. The charge neutralization module has a first terminal coupled to the power supply and a fourth terminal coupled to the charge pump unit. It is adapted to output a corresponding second control signal to the second switch module according to the voltage of its first and second terminals and the enable signal; and is adapted to store the first charge corresponding to the first electrical signal when the first charging branch is turned on; and is adapted to generate the second electrical signal and store the second charge corresponding to the second electrical signal when the second charging branch is turned on. The first terminal of the second switching module is adapted to be coupled to the second or third terminal of the second charge neutralization module according to the second control signal, so as to turn on or off the second charging branch; The second current mirror module has a first end coupled to the power supply, a second end coupled to the first end of the second switch module, and a third end grounded through the digital-to-analog converter unit. It is adapted to mirror the second electrical signal to the digital-to-analog converter unit when the second charging branch is turned on.

5. The phase-locked loop circuit according to claim 2 or 4, characterized in that, The second current mirror module includes: a third transistor and a fourth transistor, wherein: The third transistor has its gate and drain connected, and is also connected to the gate of the fourth transistor, serving as the third terminal of the second current mirror module; its source is connected to the source of the fourth transistor, serving as the first terminal of the second current mirror module. The drain of the fourth transistor serves as the second terminal of the second current mirror module.

6. The phase-locked loop circuit according to claim 4, characterized in that, The third current mirror module includes a first current mirror, a second current mirror, and a third current mirror, wherein: The first current mirror has a first end serving as the first end of the third current mirror module, a second end serving as the second end of the third current mirror module, a third end coupled to the first end of the second current mirror, and a fourth end coupled to the second end of the second current mirror and the first end of the third current mirror. The second current mirror has its third end coupled to the second end of the third current mirror and serving as the fourth end of the third current mirror module. The fourth end of the second current mirror is coupled to the third end of the third current mirror and serves as the third end of the third current mirror module. The fourth end of the third current mirror serves as the fifth end of the third current mirror module.

7. The phase-locked loop circuit according to claim 6, characterized in that, The first current mirror includes a fifth transistor, a sixth transistor, and a seventh transistor, wherein: The source of the fifth transistor is coupled to the source of the sixth and seventh transistors, serving as the first end of the first current mirror; its gate is coupled to the gate of the sixth transistor, the gate of the seventh transistor, and the drain, serving as the second end of the first current mirror; and its drain serves as the fourth end of the first current mirror. The drain of the sixth transistor serves as the third terminal of the first current mirror.

8. The phase-locked loop circuit according to claim 6, characterized in that, The second current mirror includes an eighth transistor and a ninth transistor, wherein: The eighth transistor has its drain serving as the second terminal of the second current mirror, its gate coupled to the gate and drain of the ninth transistor, serving as the first terminal of the second current mirror, and its source serving as the third terminal of the first current mirror module. The source of the ninth transistor serves as the fourth terminal of the second current mirror.

9. The phase-locked loop circuit according to claim 6, characterized in that, The third current mirror includes a tenth transistor and an eleventh transistor, wherein: The drain of the tenth transistor serves as the second terminal of the third current mirror, its gate is coupled to the gate of the eleventh transistor and serves as the first terminal of the third current mirror, and its source is coupled to the source of the eleventh transistor and serves as the third terminal of the third current mirror. The drain of the eleventh transistor serves as the fourth terminal of the third current mirror.

10. The phase-locked loop circuit according to claim 2 or 4, characterized in that, The charge neutralization module includes a voltage regulator, a capacitor, a comparator, a first inverter, and an AND gate, wherein: The voltage regulator has a first terminal that serves as the first terminal of the charge neutralization module, and its second terminal that is coupled to the first terminal of the comparator. The capacitor is coupled between the first and second terminals of the comparator; The comparator has its second terminal serving as the second terminal of the charge neutralization module, and its output terminal is coupled to the first terminal of the AND gate. The first inverter has its input terminal serving as the fourth terminal of the charge neutralization module, and its output terminal is coupled to the second terminal of the AND gate. The AND gate has its output terminal coupled to the second terminal of the second switch module.

11. The phase-locked loop circuit according to claim 10, characterized in that, The charge neutralization module also includes a resistor coupled between the second terminal of the voltage regulator and the first terminal of the comparator, adapted to limit the current in the first charging branch and the second charging branch.

12. The phase-locked loop circuit according to claim 4, characterized in that, The third switching module includes a first switch, a second switch, a twelfth transistor, and a second inverter, wherein: The first switch has its first end coupled to the gate of the twelfth transistor and the first end of the second switch, respectively, and its second end serves as the fifth end of the third switch module. It is adapted to be coupled to the second end of the third switch module when the enable signal is high, thereby turning on the first charging branch. The second inverter has its input terminal coupled to the charge pump unit and its output terminal coupled to the second terminal of the second switch. The second switch has its first terminal coupled to the gate of the twelfth transistor, adapted to be grounded when the enable signal is low, and coupled to the third terminal of the third switch module to disconnect the first charging branch. The twelfth transistor has its source serving as the first terminal of the third switching module and its drain serving as the fourth terminal of the third switching module.

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