A millimeter wave frequency synthesizer

Abstract

The invention discloses a millimeter wave frequency synthesizer. The invention adopts a two-stage phase-locked loop cascade structure. The RMS jitter of the first-stage output can be reduced to below sub-picoseconds through a fully digital phase-locked loop, the frequency of the second-stage output can be locked through a frequency-locked loop, and the phase difference of the two-stage output can be eliminated through a sub-sampling loop, thereby achieving a smaller RMS jitter of the output frequency.

Description

Technical Field

[0001] The invention relates to a millimeter wave frequency synthesizer and belongs to the field of integrated circuit design. Background Art

[0002] With the development of wireless communication systems, people's demand for high-speed communication continues to increase. Some applications, such as holographic projection, XR, super smart cities, remote surgery, high-definition imaging, distance education, and autonomous driving, have been gradually realized. However, these applications require higher communication rates. For example, 16K virtual reality (VR) requires a data transmission rate of 0.9Gbps ​​to meet the user experience.

[0003] Since the spectrum resources of low frequency bands below 6GHz are very tight, the rich spectrum resources of millimeter wave bands have attracted people's attention, such as 28GHz, 36GHz, 77GHz, etc. These bands benefit from their good atmospheric attenuation characteristics, laying the foundation for information security, and these bands have less signal interference and much larger bandwidth than low frequency, which can greatly improve the information transmission rate. To ensure the quality of communication, its transceiver must have a very low error vector magnitude (EVM). For example, to meet the high-order modulation requirements of 256QAM at 28GHz, the EVM caused by the frequency synthesizer must be less than 1.4%. In other words, the RMS jitter of the millimeter wave frequency synthesizer at the output frequency of 28GHz needs to be less than 100fs.

[0004] The performance of millimeter wave frequency synthesizers depends not only on the system architecture, but also on the performance of devices in each circuit module, such as transistor gain, noise performance, passive device loss, etc. In the millimeter wave frequency band, the Q value of CMOS devices drops sharply, causing the out-of-band phase noise generated by the oscillator to deteriorate seriously. Secondly, as the phase-locked loop division ratio increases, the in-band phase noise will deteriorate rapidly, resulting in too much RMS jitter in existing millimeter wave frequency synthesizers, affecting the quality of the communication system. Summary of the invention

[0005] The invention provides a millimeter wave frequency synthesizer, which solves the problem that the RMS jitter of the existing millimeter wave frequency synthesizer is too large.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A millimeter wave frequency synthesizer includes a fully digital phase-locked loop, a selection circuit and a sub-sampling phase-locked loop;

[0008] The sub-sampling phase-locked loop includes a frequency-locked loop, a frequency-locked detector and a sub-sampling loop; the frequency-locked loop receives a first signal output by a full-digital phase-locked loop through a selection circuit, and locks the frequency of a second signal output by the sub-sampling loop according to the first signal; after the frequency is locked, the frequency-locked detector sends an enable signal to the selection circuit and the sub-sampling loop, and the enable signal sent to the selection circuit controls the switching of the selection circuit, so that the connection between the full-digital phase-locked loop and the frequency-locked loop is disconnected, and the connection between the full-digital phase-locked loop and the sub-sampling loop is connected; the sub-sampling loop outputs a second signal according to the first signal and the enable signal, and eliminates the phase difference between the second signal and the first signal.

[0009] The millimeter wave frequency synthesizer also includes a first buffer for buffering the first signal, and the first signal is transmitted to the selection circuit through the first buffer.

[0010] The selection circuit includes inverters f1 to f6 and transmission gates m1 to m2;

[0011] The input terminals of the inverter f1 and the inverter f4 are input with an enable signal, the input terminals of the transmission gate m1 and the transmission gate m2 are both input with a first signal, and the forward control terminals of the transmission gate m1 and the transmission gate m2 are both input with an enable signal;

[0012] The output end of the inverter f1 is connected to the reverse control end of the transmission gate m1, the output end of the transmission gate m1 is connected to the inverter f2 and the inverter f3 in sequence, and the output end of the inverter f3 is connected to the sub-sampling loop;

[0013] The output end of the inverter f4 is connected to the reverse control end of the transmission gate m2, the output end of the transmission gate m2 is connected to the inverter f5 and the inverter f6 in sequence, and the output end of the inverter f6 is connected to the frequency locked loop.

[0014] The frequency locked loop includes a pre-frequency divider, a frequency and phase detector with a dead zone, a charge pump, a main frequency divider, a first loop filter and a voltage controlled oscillator;

[0015] The input end of the pre-divider is connected to an output end of the selection circuit, the pre-divider, the frequency detector with dead zone, the charge pump, the first loop filter and the voltage-controlled oscillator are connected in sequence, the input end of the main frequency divider is connected to the output end of the voltage-controlled oscillator, the output end of the main frequency divider is connected to the input end of the frequency detector with dead zone, and the output end of the frequency detector with dead zone is also connected to the frequency lock detector.

[0016] After the frequency is locked, the frequency lock detector also sends an enable signal to the frequency locked loop to turn off the frequency locked loop.

[0017] The enable signal sent to the frequency locked loop turns off the frequency locked loop's phase frequency detector with dead zone and main frequency divider. The enable signal sent to the frequency locked loop is transmitted to the phase frequency detector with dead zone through inverter f7 and transmitted to the main frequency divider through inverter f8.

[0018] The sub-sampling loop includes a sub-sampling phase detector, a sub-sampling charge pump, a pulse generator, a second buffer, a first loop filter and a voltage-controlled oscillator; wherein the first loop filter in the sub-sampling loop and the first loop filter in the frequency-locked loop are the same loop filter, and the voltage-controlled oscillator in the sub-sampling loop and the voltage-controlled oscillator in the frequency-locked loop are the same voltage-controlled oscillator;

[0019] The input end of the pulse generator is connected to the other output end of the selection circuit and the input enable signal, and the output end of the pulse generator is connected to the input end of the sub-sampling charge pump;

[0020] The input end of the sub-sampling phase detector is connected to another output end of the selection circuit, the sub-sampling phase detector, the sub-sampling charge pump, the first loop filter and the voltage-controlled oscillator are connected in sequence, the input end of the second buffer is connected to the output end of the voltage-controlled oscillator, and the output end of the second buffer is connected to the input end of the sub-sampling phase detector.

[0021] The frequency lock detector includes a frequency divider, a counter, a comparator, a three-input AND gate and an inverter f9.

[0022] The input end of the frequency divider and the input end of the counter are both input with an external clock signal. The three input ends of the three-input AND gate are respectively connected with the output end of the frequency divider, the reverse signal of the level signal DN output by the frequency locked loop, and the level signal UP output by the frequency locked loop. The output end of the three-input AND gate is connected with the control end of the counter, the reset end of the counter is connected with the external reset signal, the output end of the counter is connected with the input end of the comparator, the input end of the inverter f9 is connected with the output end of the frequency divider, the output end of the inverter f9 is connected with the control end of the comparator, and the output end of the comparator outputs an enable signal. Among them, the external clock signal is the input signal of the full digital phase-locked loop.

[0023] The beneficial effects achieved by the present invention are as follows: the present invention adopts a two-stage phase-locked loop cascade structure, and through a fully digital phase-locked loop, the RMS jitter of the first-stage output can be reduced to below sub-picoseconds, the frequency of the second-stage output can be locked through a frequency-locked loop, and the phase difference between the two-stage outputs can be eliminated through a sub-sampling loop, thereby achieving a smaller RMS jitter of the output frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a structural diagram of a millimeter wave frequency synthesizer;

[0025] Figure 2 It is the circuit diagram of the fully digital phase-locked loop;

[0026] Figure 3 A circuit diagram for selecting a circuit;

[0027] Figure 4 This is the circuit diagram of a frequency and phase detector with a dead zone;

[0028] Figure 5 is a circuit diagram of a frequency lock detector;

[0029] Figure 6 is the circuit diagram of the sub-sampling phase detector;

[0030] Figure 7 is the circuit diagram of the pulse generator;

[0031] Figure 8 is a circuit diagram of a sub-sampling charge pump;

[0032] Fig. 9 Circuit diagram of voltage controlled oscillator

[0033] FIG10( a ) is a simulation diagram of a frequency and phase detector with a dead zone when Fref1_N lags behind Fdiv;

[0034] FIG10( b ) is a simulation diagram of a frequency and phase detector with a dead zone when Fref_N is ahead of Fdiv;

[0035] FIG10( c ) is a simulation diagram of the frequency and phase detector with dead zone when Fref_N and Fdiv fall into the dead zone. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0037] A millimeter wave frequency synthesizer comprises a fully digital phase-locked loop, a selection circuit and a sub-sampling phase-locked loop which are connected in sequence; the sub-sampling phase-locked loop comprises a frequency-locked loop, a frequency lock detector and a sub-sampling loop; the frequency-locked loop receives a first signal output by the fully digital phase-locked loop through the selection circuit, and locks the frequency of a second signal output by the sub-sampling loop according to the first signal; after the frequency is locked, the frequency lock detector sends an enable signal to the selection circuit and the sub-sampling loop, and the enable signal sent to the selection circuit controls the switching of the selection circuit, so that the connection between the fully digital phase-locked loop and the frequency-locked loop is disconnected, and the connection between the fully digital phase-locked loop and the sub-sampling loop is connected; the sub-sampling loop outputs a second signal according to the first signal and the enable signal, and eliminates the phase difference between the second signal and the first signal.

[0038] The above-mentioned synthesizer adopts a two-stage phase-locked loop cascade structure. Through the fully digital phase-locked loop, the RMS jitter of the first-stage output can be reduced to below sub-picoseconds. Through the frequency-locked loop, the frequency of the second-stage output can be locked. Through the sub-sampling loop, the phase difference between the two-stage outputs can be eliminated, thereby achieving a smaller RMS jitter of the output frequency.

[0039] An embodiment of the present invention, as Figure 1As shown, a millimeter wave frequency synthesizer includes a fully digital phase-locked loop, a first buffer, a selection circuit and a sub-sampling phase-locked loop connected in sequence. The fully digital phase-locked loop inputs an external clock signal Fref and outputs a first signal, which is buffered by the first buffer and used as a reference signal of the sub-sampling phase-locked loop.

[0040] An embodiment of the present invention, as Figure 2 As shown, the all-digital phase-locked loop may include a first phase frequency detector, a time-to-digital converter, a second loop filter, a ΣΔ modulator, a voltage-controlled oscillator, a multi-mode divider and an automatic frequency calibration module.

[0041] The input end of the first phase frequency detector inputs an external clock signal Fref, the first phase frequency detector, the time digital converter, the second loop filter, the ΣΔ modulator, and the voltage controlled oscillator are connected in sequence, the output end of the voltage controlled oscillator outputs a first signal, the input end of the multi-mode frequency divider is connected to the output end of the voltage controlled oscillator, the output end of the multi-mode frequency divider is connected to the input end of the first phase frequency detector and the input end of the automatic frequency calibration module, the input end of the automatic frequency calibration module also inputs the external clock signal Fref, and the output end of the automatic frequency calibration module is connected to the input end of the voltage controlled oscillator; wherein, the first phase frequency detector has three outputs, two of which are connected to the time digital converter, and the other is externally connected to the input end of the automatic loop gain control circuit; the time digital converter has two inputs and one output; the output of the second loop filter is connected to the input of the ΣΔ modulator; the output of the ΣΔ modulator is connected to the input of the fine tuning capacitor array of the voltage controlled oscillator; the five-bit output of the automatic frequency calibration module is connected to the five-bit input of the coarse tuning capacitor array of the voltage controlled oscillator.

[0042] The first frequency detector of the all-digital phase-locked loop detects the external clock signal Fref and the signal output by the multi-mode divider to generate two signals with phase difference information and symbol information of frequency advance or lag. Then the time-to-digital converter converts the phase difference information into a digital signal. The second loop filter adaptively selects different loop bandwidths according to the symbol information to realize digital signal processing of the phase difference information of the time-to-digital converter, thereby generating a digital control word for controlling the frequency of the voltage-controlled oscillator. The digital control word is input to the ΣΔ modulator for high-frequency dithering to improve the resolution of the voltage-controlled oscillator.

[0043] An embodiment of the present invention, as Figure 3As shown, the selection circuit may include inverters f1 to f6 and transmission gates m1 to m2; the input ends of the inverter f1 and the inverter f4 are input with an enable signal EN, the input ends of the transmission gates m1 and the transmission gates m2 are both input with a first signal, and the forward control ends of the transmission gates m1 and the transmission gates m2 are both input with an enable signal; the output end of the inverter f1 is connected to the reverse control end of the transmission gate m1, the output end of the transmission gate m1 is sequentially connected to the inverter f2 and the inverter f3, and the output end Fref2 of the inverter f3 is connected to the sub-sampling loop; the output end of the inverter f4 is connected to the reverse control end of the transmission gate m2, the output end of the transmission gate m2 is sequentially connected to the inverter f5 and the inverter f6, and the output end Fref1 of the inverter f6 is connected to the frequency locked loop.

[0044] The selection circuit is like a switch, which distributes the signal generated by the first-stage phase-locked loop to the subsequent frequency-locked loop or sub-sampling loop. The external input enable signal EN controls the turn-off or turn-on of the transmission gates m1~m2 to realize the circuit function. The outputs of the two transmission gates are shaped by inverters to avoid excessive clock rise delay time.

[0045] In one embodiment of the present invention, a frequency locked loop may include a pre-divider, a frequency detector with a dead zone, a charge pump, a main frequency divider, a loop filter and a voltage controlled oscillator; the input end of the pre-divider is connected to an output end of a selection circuit, the pre-divider, the frequency detector with a dead zone, the charge pump, the loop filter and the voltage controlled oscillator are connected in sequence, the input end of the main frequency divider is connected to the output end of the voltage controlled oscillator, the output end of the main frequency divider is connected to the input end of the frequency detector with a dead zone, and the output end of the frequency detector with a dead zone is also connected to a frequency lock detector.

[0046] like Figure 4 As shown, the frequency and phase detector with dead zone may include D flip-flops D1-D4, delays Y1-Y3, an inverter f10, AND gates n1-n3 and a transmission gate m3.

[0047] The two input terminals of the AND gate n1 are respectively connected to the output of the prescaler (the output signal Fref1_N of the prescaler) and the enable signal EN, the output terminal of the AND gate n1 is respectively connected to the Clk terminal (clock input terminal) of the D flip-flop D1 and the input terminal of the delay device Y1, the output terminal of the input terminal of the delay device Y1 is connected to the Clk terminal of the D flip-flop D3, the Q terminal of the D flip-flop D1 is respectively connected to the D terminal of the D flip-flop D3 and an input terminal of the AND gate n3, the Q terminal of the D flip-flop D3 is connected to the input terminal of the inverter f10, the output terminal of the inverter f10 outputs the level signal UP, and the two input terminals of the AND gate n2 are respectively connected to the output of the main divider (i.e., the main The output end of the AND gate n2 is connected to the Clk end of the D flip-flop D2 and the input end of the delay device Y2 respectively, the output end of the input end of the delay device Y2 is connected to the Clk end of the D flip-flop D4, the Q end of the D flip-flop D2 is connected to the D end of the D flip-flop D4 and the other input end of the AND gate n3 respectively, the output end of the AND gate n3 is connected to the input end of the delay device Y3, the output end of the delay device Y3 is connected to the Rst end of the D flip-flop D1 and the Rst end of the D flip-flop D2 respectively, the Q end of the D flip-flop D4 is connected to the input end of the transmission gate m3, and the output end of the transmission gate m3 outputs a level signal DN.

[0048] The phase detector with dead zone adopts edge sampling structure to extract the phase difference between the reference signal and the signal output by the main divider. The phase detector with dead zone generates UP / DN level signal by sampling the phase difference after phase detection, so as to increase the conduction time of the MOS switch in the charge pump and speed up the frequency locking. When the frequency is locked, the phase difference between the pre-divided signal and the signal output by the voltage-controlled oscillator through the main divider will fall into the phase detection dead zone. At this time, the UP signal generated is high level and the DN signal is low level, thereby turning off the MOS switch in the charge pump.

[0049] An embodiment of the present invention, as Figure 5 As shown, the frequency lock detector includes a frequency divider, a counter, a comparator, a three-input AND gate and an inverter f9. The input end of the frequency divider and the input end of the counter are both input with an external clock signal Fref. The three input ends of the three-input AND gate are respectively connected with the output end of the frequency divider, the reverse signal of the level signal DN output by the frequency locked loop, and the level signal UP output by the frequency locked loop. The output end of the three-input AND gate is connected with the control end of the counter, the reset end of the counter is connected with the external reset signal Renew, the output end of the counter is connected with the input end of the comparator, the input end of the inverter f9 is connected with the output end of the frequency divider, the output end of the inverter f9 is connected with the control end of the comparator, and the output end of the comparator outputs an enable signal.

[0050] After the frequency is locked, the phase error between the signal of the first-stage output after the pre-divider and the signal of the voltage-controlled oscillator output after the main divider will fall into the dead zone, thereby generating a signal of UP being high and DN being low. The frequency lock detector generates an enable signal EN by taking the external clock signal Fref and UP and DN_N (the inverse signal of DN) through a three-input AND gate. Only when the external clock signal Fre and UP and DN_N are "1" at the same time, the AND gate output will be "1", otherwise the output is "0". At this time, if the counter enable terminal is "1", the counter will start counting Fref; if the counter enable terminal is "0", the counter is reset. The Renew signal is an external input signal to prevent the frequency lock detector from not controlling the selection circuit to switch to the frequency lock loop in time for a new frequency lock when the frequency control word of the fully digital phase-locked loop is updated. When the output of the three-input AND gate is "1", the calculator starts to calculate, and the output of the AND gate provides a control signal to the comparator through the inverter f9. When the comparator's enable signal is "0", the counter's output value is input to the comparator and stored in the comparator; when the comparator's enable signal is "1", the counter's output value stored in the comparator will be compared with the preset target value Ntarget. If the count value N1 output by the counter is greater than the target value Ntarget, it means that the loop has been locked and the output EN is "1"; if the count value N1 output by the counter is less than the target value Ntarget, it means that the loop is not locked and the output EN is "0".

[0051] In order to reduce power consumption, after the frequency is locked, the frequency lock detector also sends an enable signal to the frequency locked loop to shut down the frequency locked loop. Specifically, the enable signal sent to the frequency locked loop shuts down the frequency lock phase detector with dead zone and the main divider of the frequency locked loop. The enable signal sent to the frequency locked loop is transmitted to the frequency lock phase detector with dead zone through inverter f7, and is transmitted to the main divider through inverter f8.

[0052] The frequency lock detector generates an enable signal based on the UP / DN signal, thereby turning off the frequency divider module of the frequency lock loop to save power. At the same time, the enable signal will also select the sub-sampling loop and turn on the pulse generator of the sub-sampling loop to generate Pul- / Pul+ pulse signals, thereby turning on the sub-sampling charge pump to eliminate phase errors.

[0053] In one embodiment of the present invention, a sub-sampling loop may include a sub-sampling phase detector, a sub-sampling charge pump, a pulse generator, a second buffer, a loop filter and a voltage-controlled oscillator; wherein the loop filter in the sub-sampling loop and the loop filter in the frequency-locked loop are the same loop filter, and the voltage-controlled oscillator in the sub-sampling loop and the voltage-controlled oscillator in the frequency-locked loop are the same voltage-controlled oscillator.

[0054] The input end of the pulse generator is connected to the other output end of the selection circuit and the input enable signal, the output end of the pulse generator is connected to the input end of the sub-sampling charge pump, the input end of the sub-sampling phase detector is connected to the other output end of the selection circuit, the sub-sampling phase detector, the sub-sampling charge pump, the loop filter and the voltage-controlled oscillator are connected in sequence, the input end of the second buffer is connected to the output end of the voltage-controlled oscillator, and the output end of the second buffer is connected to the input end of the sub-sampling phase detector.

[0055] like Figure 6 As shown, the sub-sampling phase detector may include PMOS tubes M1-M2 and capacitors C1-C2, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are connected to Fref2, the drain of the PMOS tube M1 is connected to one end of the capacitor C1 and an output port Vsam+, the other end of the capacitor C1 is grounded, the source of the PMOS tube M1 is connected to the differential signal VCO+ output by the voltage-controlled oscillator, the drain of the PMOS tube M2 is connected to one end of the capacitor C2 and another output port Vsam-, the other end of the capacitor C2 is grounded, and the source of the PMOS tube M2 is connected to the differential signal VCO- output by the voltage-controlled oscillator.

[0056] The sub-sampling phase detector samples the differential signals VCO+ and VCO- output by the voltage-controlled oscillator through the output of the first buffer, and the obtained sampling voltage is converted into a current signal by the sub-sampling charge pump of the subsequent stage, thereby realizing the regulation of the loop. When the sub-sampling phase detector samples the differential signal output by the voltage-controlled oscillator, there is no influence of the frequency divider in the loop. At the same time, the gain of the sub-sampling phase detector is very large, which can suppress the in-band phase noise, thereby achieving better performance.

[0057] like Figure 7 As shown, the pulse generator may include inverters f11 to f19, transmission gates m4 to m6, and an OR gate h1; the input end of the inverter f11 is connected to an enable signal EN, the output end of the inverter f11 and Fref2 are respectively connected to two input ends of the OR gate h1, the output end of the OR gate h1 is sequentially connected to inverter f12, inverter f13, and inverter f14, the output end of the inverter f14 is respectively connected to the input end of the inverter f15 and the input end of the inverter f18, the output end of the inverter f15 is sequentially connected to inverter f16, inverter f17 and transmission gate m5, the output end of the transmission gate m5 outputs a pulse signal Pul-, the output end of the inverter f18 is sequentially connected to transmission gates m4, inverter f19 and transmission gate m6, and the output end of the transmission gate m6 outputs a pulse signal Pul+.

[0058] The pulse generator circuit is composed of a single-ended to differential circuit. The external input enable signal and the signal output by the first-stage buffer are used together to generate the pulse signal Pul- / Pul+. When the enable signal is "0", the Pul- generated by the pulse generator is high level and Pul+ is low level. At this time, the generation of Pul- / Pul+ will turn off the sub-sampling charge pump, and the sub-sampling loop will not work; when the enable signal is "1", the Pul- / Pul+ generated by the pulse generator is a pulse signal. At this time, the sub-sampling charge pump works normally, and the sub-sampling loop begins to eliminate the phase error.

[0059] The above sub-sampling charge pump converts the voltage used by the sub-sampling phase detector into current, and charges and discharges the loop filter through the pulse generator. The specific structure can be seen Figure 8 .

[0060] The sub-sampling charge pump mainly includes MOS tubes M3 to M17. M3 and M4 convert the sampling voltage into current and flow into M5 and M6 respectively. M8 copies the current in M5 through the current mirror and generates a charging current at the drain end. Similarly, M6 and M7, M15 and M16 also form a mirror image. M7 and M15 are in the same branch, ensuring that the discharge current generated by M16 is determined by M6. In order to reduce the influence of the drain-source voltage of M15, M17 working in the deep linear region is added to the M7 branch to consume part of the drain-source voltage on M15, so that the current copied from M15 to M16 will not have a large deviation. The complementary pulse signal Pul+ / Pul- controls the MOS tubes M9 to M12 to charge and discharge the next stage. The capacitor Cdummy is added to the drain end of M9 and M11 of the sub-sampling charge pump. When Pul+ is at a low level, the current source charges and discharges the capacitor Cdummy to reduce the charge sharing between the control voltage Vctrl and M8 and M16.

[0061] An embodiment of the present invention, as Fig. 9 As shown, the voltage-controlled oscillator may include NMOS tubes M18-M19, PMOS tubes M20-M21, resistors R1-R2, capacitors C3-C4, a coarse-tuning capacitor array, a voltage-controlled variable capacitor module, and an inductor L1.

[0062] The left and right ends of the inductor L1 are respectively connected to the two-end outputs VP and VN of the voltage-controlled oscillator, and the center tap of the inductor L1 is connected to the power supply voltage VDD. The gate of the NMOS tube M18 is connected to VN and one end of the capacitor C3, the drain of the NMOS tube M18 is connected to VP, the source of the NMOS tube M18 is connected to the source of the PMOS tube M20, the gate of the PMOS tube M20 is connected to the other end of the capacitor C4 and one end of the resistor R1, and the drain of the PMOS tube M20 and the other end of the resistor R1 are grounded. The gate of the NMOS tube M19 is connected to VP and one end of the capacitor C4, the drain of the NMOS tube M19 is connected to VN, the source of the NMOS tube M18 is connected to the source of the PMOS tube M21, the gate of the PMOS tube M21 is connected to the other end of the capacitor C3 and one end of the resistor R2, and the drain of the PMOS tube M21 and the other end of the resistor R2 are grounded.

[0063] The coarse tuning capacitor array has 5 coarse tuning capacitors, which are set between VP and VN, and mainly include NMOS tube M22, capacitors C9~C10, resistors R7~R8, and inverter f20. One end of capacitor C9 is connected to VP, the other end of capacitor C9 is connected to resistor R7 and the source of NMOS tube M22, the other end of resistor R7 is connected to the output of inverter f20 and one end of resistor R8, and the gate of NMOS tube M22 and the input end of inverter f20 are connected to the external binary digital control signal D C [0] is used to control the NMOS switch M22. The drain of the NMOS tube M22 is connected to the other end of the resistor R8 and one end of the capacitor C10. The other end of the capacitor C10 is connected to VN.

[0064] The voltage-controlled variable capacitor module VCCA is also arranged between VP and VN, and mainly includes resistors R3-R5, capacitors C5-C8, and variable capacitors Cvar1-Cvar4. One end of capacitor C5 and one end of capacitor C7 are both connected to VP, the other end of capacitor C5 is connected to one end of variable capacitor Cvar1 and one end of resistor R3, the other end of capacitor C7 is connected to one end of variable capacitor Cvar3 and one end of resistor R5, one end of capacitor C6 and one end of capacitor C8 are both connected to VN, the other end of capacitor C4 is connected to one end of variable capacitor Cvar2 and one end of resistor R4, the other end of capacitor C8 is connected to one end of variable capacitor Cvar4 and one end of resistor R6, the other ends of variable capacitors Cvar1-Cvar4 are all connected to the control voltage Vctrl output by the external loop filter, which is used to control the frequency of the voltage-controlled oscillator, the other ends of resistors R3-R4 are all connected to the external input bias voltage Vbais1, and the other ends of resistors R5-R6 are all connected to the external input bias voltage Vbais2.

[0065] The voltage-controlled oscillator uses a noise circulation structure to reduce the noise current injected into the resonator, thereby achieving lower phase noise. M18, C4 and M20 form a noise circulation path. When M18 generates noise, the noise current will form a circulation loop through M18, C4 and M20, so that part of the noise current of M18 circulates in M18, and the other part will be injected into the resonant cavity to form phase noise, thereby reducing the phase noise caused by M18; similarly, when M20 generates noise current, part of the noise current will pass through M18 to reach the resonant circuit, generating phase noise, and the other part will circulate back to M20 and finally reach the ground. The voltage-controlled oscillator consists of a coarse-tuning capacitor array composed of switched capacitors and a voltage-controlled array composed of variable capacitors. M18 and M19 provide negative resistance for the oscillator to compensate for the energy loss of the resonant cavity. The coarse tuning capacitor array consists of MIM capacitors, resistors, NMOS tubes, and inverters to cover the output frequency range. The voltage-controlled variable capacitor module adopts a high linearity design and adjusts the tuning linearity of the high-voltage controlled oscillator by setting different bias voltages Vbias1 and Vbias2.

[0066] Figures 10(a) to (b) show the transient simulation when the phase difference between the two input clock signals Fref1_N and Fdiv of the frequency detector with dead zone is greater than the dead zone range. Figure 10(a) shows the transient simulation when Fref1_N lags behind Fdiv. It can be seen from Figure 10(a) that the output signals UP and DN of the frequency detector with dead zone are both high level. At this time, the level signals of UP and DN will discharge the charge pump controlled quickly, thereby accelerating the frequency reduction. Similarly, when Fref1_N is ahead of Fdiv, as shown in Figure 10(b), the output signals UP and DN of the frequency detector with dead zone are both low level. At this time, the level signals of UP and DN will charge the charge pump controlled quickly, thereby accelerating the frequency increase. Figure 10(c) is a transient simulation when the phase difference between Fref1_N and Fdiv falls within the dead zone. At this time, the output signal UP of the frequency detector with dead zone is high and DN is low. The level signals of UP and DN will turn off the charge pump, so that the output frequency will not change and the frequency locked loop will be locked.

[0067] The present invention adopts a two-stage phase-locked loop cascade structure, and realizes a smaller RMS jitter of the output frequency through circuit innovation. The first stage can reduce the RMS jitter of the output of the full digital phase-locked loop to below sub-picoseconds by improving the resolution of the time-to-digital converter in the full digital phase-locked loop and reducing the loop bandwidth, and then realize the millimeter wave output frequency through the second stage sub-sampling phase-locked loop. The second stage phase-locked loop adopts the proposed frequency lock detector, and realizes better performance by controlling the selection circuit to connect different circuits. When the frequency is not locked, the selection circuit connects the first stage circuit and the frequency lock loop to realize frequency locking, thereby avoiding the loop locking on the high harmonics of the output frequency of the first stage phase-locked loop. After the frequency is locked, the enable signal generated by the frequency lock detector will turn off the frequency lock loop to save power consumption, and at the same time, the enable signal controls the selection circuit to connect the sub-sampling loop to eliminate the phase error. Through the characteristics of the sub-sampling loop, such as a larger phase-detection gain, no frequency divider in the loop, and a larger loop bandwidth, the entire frequency synthesizer realizes better in-band and out-of-band phase noise, thereby generating a smaller RMS jitter.

[0068] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A millimeter wave frequency synthesizer, It is characterized in that Including full digital phase-locked loop, selection circuit and sub-sampling phase-locked loop; The sub-sampling phase-locked loop comprises a frequency-locked loop, a frequency-locked detector and a sub-sampling loop; the frequency-locked loop receives a first signal output by the full-digital phase-locked loop through a selection circuit, and locks the frequency of a second signal output by the sub-sampling loop according to the first signal; After the frequency is locked, the frequency lock detector sends an enable signal to the selection circuit and the sub-sampling loop. The enable signal sent to the selection circuit controls the selection circuit to switch, so that the connection between the full digital phase-locked loop and the frequency-locked loop is disconnected, and the connection between the full digital phase-locked loop and the sub-sampling loop is connected; The sub-sampling loop outputs a second signal according to the first signal and the enable signal, and eliminates a phase difference between the second signal and the first signal; The frequency lock detector includes a frequency divider, a counter, a comparator, a three-input AND gate and an inverter f9. The input end of the frequency divider and the input end of the counter are both input with an external clock signal. The three input ends of the three-input AND gate are respectively connected with the output end of the frequency divider, the reverse signal of the level signal DN output by the frequency locked loop, and the level signal UP output by the frequency locked loop. The output end of the three-input AND gate is connected with the control end of the counter, the reset end of the counter is connected with the external reset signal, the output end of the counter is connected with the input end of the comparator, the input end of the inverter f9 is connected with the output end of the frequency divider, the output end of the inverter f9 is connected with the control end of the comparator, and the output end of the comparator outputs an enable signal. The external clock signal is the input signal of the full digital phase-locked loop.

2. A millimeter wave frequency synthesizer according to claim 1, It is characterized in that The millimeter wave frequency synthesizer also includes a first buffer for buffering the first signal, and the first signal is transmitted to the selection circuit through the first buffer.

3. A millimeter wave frequency synthesizer according to claim 1 or 2, It is characterized in that The selection circuit includes inverters f1~f6 and transmission gates m1~m2; The input terminals of the inverter f1 and the inverter f4 are input with an enable signal, the input terminals of the transmission gate m1 and the transmission gate m2 are both input with a first signal, and the forward control terminals of the transmission gate m1 and the transmission gate m2 are both input with an enable signal; The output end of the inverter f1 is connected to the reverse control end of the transmission gate m1, the output end of the transmission gate m1 is connected to the inverter f2 and the inverter f3 in sequence, and the output end of the inverter f3 is connected to the sub-sampling loop; The output end of the inverter f4 is connected to the reverse control end of the transmission gate m2, the output end of the transmission gate m2 is connected to the inverter f5 and the inverter f6 in sequence, and the output end of the inverter f6 is connected to the frequency locked loop.

4. A millimeter wave frequency synthesizer according to claim 1, It is characterized in that The frequency locked loop includes a pre-frequency divider, a frequency and phase detector with a dead zone, a charge pump, a main frequency divider, a first loop filter and a voltage controlled oscillator; The input end of the pre-divider is connected to an output end of the selection circuit, the pre-divider, the frequency detector with dead zone, the charge pump, the first loop filter and the voltage-controlled oscillator are connected in sequence, the input end of the main frequency divider is connected to the output end of the voltage-controlled oscillator, the output end of the main frequency divider is connected to the input end of the frequency detector with dead zone, and the output end of the frequency detector with dead zone is also connected to the frequency lock detector.

5. A millimeter wave frequency synthesizer according to claim 4, It is characterized in that After the frequency is locked, the frequency lock detector also sends an enable signal to the frequency locked loop to turn off the frequency locked loop.

6. A millimeter wave frequency synthesizer according to claim 5, It is characterized in that The enable signal sent to the frequency locked loop turns off the frequency locked loop's phase frequency detector with dead zone and main frequency divider. The enable signal sent to the frequency locked loop is transmitted to the phase frequency detector with dead zone through inverter f7 and transmitted to the main frequency divider through inverter f8.

7. A millimeter wave frequency synthesizer according to claim 4, 5 or 6, It is characterized in that The sub-sampling loop includes a sub-sampling phase detector, a sub-sampling charge pump, a pulse generator, a second buffer, a first loop filter and a voltage-controlled oscillator; wherein the first loop filter in the sub-sampling loop and the first loop filter in the frequency-locked loop are the same loop filter, and the voltage-controlled oscillator in the sub-sampling loop and the voltage-controlled oscillator in the frequency-locked loop are the same voltage-controlled oscillator; The input end of the pulse generator is connected to the other output end of the selection circuit and the input enable signal, and the output end of the pulse generator is connected to the input end of the sub-sampling charge pump; The input end of the sub-sampling phase detector is connected to another output end of the selection circuit, the sub-sampling phase detector, the sub-sampling charge pump, the first loop filter and the voltage-controlled oscillator are connected in sequence, the input end of the second buffer is connected to the output end of the voltage-controlled oscillator, and the output end of the second buffer is connected to the input end of the sub-sampling phase detector.

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