A path planning method of a three-pin impedance matching device

Abstract

This invention discloses a path planning method for a three-pin impedance tuner, belonging to the field of impedance matching technology in microwave energy applications. The method involves calculating the optimal depth of the three pins based on the measured reflection coefficient at the port when the load changes; then, based on the calculated optimal pin depth, implementing a low-reflection adjustment strategy to adjust the pin depth, avoiding large reflections during the adjustment process. This method achieves good matching by adjusting two pins, while avoiding large reflections that could damage the microwave source and affect system stability. It requires no complex parameter measurements, is fast and accurate, and is applicable to three-pin rectangular waveguides of various specifications. This invention effectively solves the problems of existing three-pin impedance tuners that do not consider reflection changes during pin adjustment and have complex calculation processes.

Description

Technical Field

[0001] This invention relates to the field of impedance matching technology in microwave energy applications, specifically to a path planning method for a three-pin impedance tuner. Background Technology

[0002] Microwave energy, as an emerging energy source, has been widely used in various aspects of industrial applications, such as microwave heating, microwave plasma, and microwave sterilization. In high-power microwave applications, impedance matching systems are essential to reduce energy reflection and ensure that the load receives maximum power from the microwave source. Impedance mismatch can lead to large reflections, resulting in low efficiency or even equipment damage.

[0003] In existing technologies, three-pin waveguides are often used between microwave sources and loads to perform impedance matching and reduce reflections. When the connected load changes, the insertion depth of the three pins is adjusted to achieve good impedance matching. For example, Chinese Patent CN 111062184 B discloses a fast three-pin automatic impedance matching system. Its matching process involves: based on equivalent circuit analysis, coarse numerical calculations are performed on the three-pin waveguide; through continuous iterative calculations and searches, the basic position of the pin depth that meets the conditions is obtained; after adjustment, a fine-tuning algorithm is used to adjust the three pins to achieve impedance matching. This scheme can achieve good matching results, but it has two problems: first, during the adjustment process, all three pins need to be adjusted, requiring numerous parameters and values, making the calculation process complex; second, it does not consider the changes in reflection during the adjustment process. After calculating the pin depth, adjusting the three pins simultaneously may generate large reflections that could damage the equipment and cause the protection circuit to trip, affecting the stability of the system. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a path planning method for a three-pin impedance matcher, aiming to solve the problems of existing three-pin impedance matchers not considering the reflection changes of the pins during adjustment and having complex calculation processes. To achieve the above objective, this invention provides the following technical solution:

[0005] A path planning method for a three-pin impedance matcher includes the following steps:

[0006] Step S100: When the load changes, calculate the optimal solution for the depth of the three pins based on the reflection coefficient measured at the port.

[0007] Step S200: Based on the calculated optimal solution for the depth of the three pins, implement a low-reflection adjustment strategy to adjust the depth of the three pins to avoid large reflections during the adjustment process.

[0008] Furthermore, when the load changes, the step of calculating the optimal solution for the depth of the three pins based on the reflection coefficient measured at the port includes:

[0009] Step S110: Establish the equivalent circuit model of the three-pin waveguide;

[0010] Step S120: Design impedance matching method.

[0011] Furthermore, the steps of the impedance matching design method include:

[0012] Step S121: Calculate the load: Calculate the load based on the reflection coefficient measured at the port, assuming the initial depth of the three pins is 0.

[0013]

[0014] l is the waveguide length; Γ is the reflection coefficient at the port; β is the phase constant; Z e Z is the equivalent impedance of the waveguide; L The load impedance;

[0015] Step S122: Calculate the equivalent load: There is a waveguide segment between the third pin and the load. The load and this waveguide segment are considered as a new load, i.e., the equivalent load:

[0016]

[0017] η0 is the wave impedance of the waveguide; Z′ L l3 represents the equivalent load; l3 is the waveguide length between the third pin and the load.

[0018] Step S123, Equivalent load region determination:

[0019] Z′ L ∈(Re(Z)>η0)∪((Re(1 / Z)<1 / η0)∩(Im(1 / Z)<0)) (3)

[0020] The equivalent load is located in the upper region. The impedance matching adjustment step in the upper region is performed to obtain the optimal solution for the depth of the three pins.

[0021] Z′ L ∈((Re(Z)<η0)∩((Im(Z)<0)∪((Re(1 / Z)>1 / η0)) (4)

[0022] The equivalent load is located in the lower half region. The impedance matching adjustment step in the lower half region is performed to obtain the optimal solution for the depth of the three pins; Z is the load variable; Re represents taking the real part of a complex number; Im represents taking the imaginary part of a complex number.

[0023] Furthermore, the upper half-region impedance matching adjustment step includes:

[0024] a. Assume that the initial depth of all three pins is 0;

[0025] b. Adjust the third pin: Adjust the third pin so that the input impedance at the third pin port meets the following condition:

[0026]

[0027] c. Impedance Transformation: After passing through a quarter waveguide wavelength, Z3 and Z2 are centrally symmetric about the matching point on the Smith chart, i.e., Z3*Z2=η0 2 ;

[0028] d. Adjust the second pin: Adjust the second pin so that Re(Z2) = η0 to complete the impedance matching;

[0029] e. Select the optimal solution: Adjust the third pin until the maximum adjustment depth h. max Substitute each value h3 of the third pin that satisfies formula (5) into the calculation to obtain a corresponding value h2 of the second pin, thus minimizing the reflection; select the solution with the smallest reflection coefficient from the many sets as the optimal solution:

[0030]

[0031] The optimal depth for the first, second, and third pins is determined at this point. h max h1, h2, and h3 are the maximum adjustment depth of the pins; h1, h2, and h3 are the insertion depths of the three pins; Z1, Z2, and Z3 are the input impedances of the ports of the first, second, and third pins, respectively.

[0032] Furthermore, the lower half-region impedance matching adjustment step includes:

[0033] a. Assume that the initial depth of all three pins is 0;

[0034] b. Impedance transformation: After a quarter waveguide wavelength, Z3 and Z2 are exactly centrally symmetrical about the matching point on the Smith chart, i.e., Z3*Z2=η0. 2 ;

[0035] c. Adjust the second pin: Adjust the second pin so that the input impedance at the second pin port meets the following condition:

[0036]

[0037] d. Impedance transformation: After a quarter waveguide wavelength, Z2 and Z1 are exactly centrally symmetrical about the matching point on the Smith chart, i.e., Z1*Z2=η0 2 ;

[0038] e. Adjust the first pin: Adjust the first pin so that Re(Z1) = η0 to complete the impedance matching;

[0039] f. Select the optimal solution: Adjust the second pin until the maximum adjustment depth h. max Substitute each second pin value h2 that satisfies formula (7) into the calculation to obtain a corresponding first pin value h1, thus minimizing the reflection; select the solution with the smallest reflection coefficient from the many sets as the optimal solution:

[0040]

[0041] The optimal depth for the first, second, and third pins is determined at this point. h max h1, h2, and h3 are the maximum adjustment depth of the pins; h1, h2, and h3 are the insertion depths of the three pins; Z1, Z2, and Z3 are the input impedances of the ports of the first, second, and third pins, respectively.

[0042] Furthermore, the calculation formulas for Z1, Z2, and Z3 are as follows:

[0043]

[0044] P″′0, P″′0, and P′0 are the characteristic impedances of the ports of the third pin, the second pin, and the first pin, respectively; ω is the angular frequency; C1, C2, and C3 are the equivalent capacitances corresponding to the three pins; and l1 and l2 are the waveguide lengths between the pins.

[0045] Furthermore, the step of implementing a low-reflection adjustment strategy to adjust the depth of the three pins based on the calculated optimal solution for the depth of the three pins, and avoiding large reflections during the adjustment process, includes:

[0046] Step S210, Matching status determination: When the load value does not change, execute the static matching path adjustment strategy; when the load value changes, execute the dynamic matching path adjustment strategy.

[0047] Step S220, the static matching path adjustment strategy steps include:

[0048] Step S221: Calculate the equivalent load and determine the equivalent load region;

[0049] Step S222: Execute the corresponding path adjustment strategy according to the region where the equivalent load is located;

[0050] When the equivalent load is located in the upper half of the region, the depth of the first pin is 0:

[0051] ′

[0052] If Z L ∈((Re(1 / Z)<1 / η0)∩(Im(1 / Z)<0)), first adjust the third pin to make Im(Z3)=0, then adjust the third pin and the second pin at the same time;

[0053] ′

[0054] If Z L ∈((Re(Z)>η0)∩(Im(Z)<0)), and simultaneously adjust the third pin and the second pin;

[0055] When the equivalent load is located in the lower half of the region, the depth of the third pin is 0:

[0056] ′

[0057] If Z L ∈((Re(Z)<η0)∩(Im(Z)<0)), first adjust the second pin to make Im(Z2)=0, then adjust the second pin and the first pin at the same time;

[0058] ′

[0059] If Z L ∈((Re(1 / Z)>1 / η0)∩(Im(1 / Z)<0)), and simultaneously adjust the second pin and the first pin;

[0060] Step S230, the dynamic matching path adjustment strategy steps include:

[0061] Step S231: Calculate the equivalent load and determine the equivalent load region;

[0062] When the equivalent load only changes in the upper half of the region, the depth of the first pin is 0. First adjust the third pin, then adjust the second pin.

[0063] When the equivalent load only changes in the lower half of the region, the depth of the third pin is 0. First adjust the second pin, then adjust the first pin.

[0064] When the equivalent load changes from the upper half region to the lower half region, first adjust the depth of the third pin to 0, and then adjust the second pin and the first pin at the same time.

[0065] When the equivalent load changes from the lower half of the region to the upper half of the region, first adjust the depth of the first pin to 0, then adjust the third pin, and finally adjust the second pin.

[0066] The beneficial effects of this invention are:

[0067] This invention discloses a path planning method for a three-pin impedance tuner, belonging to the field of impedance matching technology in microwave energy applications. The method involves calculating the optimal depth of the three pins based on the measured reflection coefficient at the port when the load changes; then, based on the calculated optimal pin depth, implementing a low-reflection adjustment strategy to adjust the pin depth, avoiding large reflections during the adjustment process. This method achieves good matching by adjusting two pins, while avoiding large reflections that could damage the microwave source and affect system stability. It requires no complex parameter measurements, is fast and accurate, and is applicable to three-pin rectangular waveguides of various specifications. This invention effectively solves the problems of existing three-pin impedance tuners that do not consider reflection changes during pin adjustment and have complex calculation processes. Attached Figure Description

[0068] Figure 1 This is a schematic diagram of the three-pin impedance adjuster model of the present invention;

[0069] Figure 2 This is a schematic diagram of the upper and lower halves of the Smith chart of this invention.

[0070] Figure 3 This is the equivalent impedance matching circuit diagram of the three-pin impedance adjuster of the present invention.

[0071] Figure 4 This is a flowchart illustrating the path planning method for the three-pin impedance modulator of the present invention.

[0072] Figure 5 This is a flowchart of the impedance matching method of the present invention;

[0073] Figure 6 This is a schematic diagram of the waveguide of the present invention;

[0074] Figure 7 This is a schematic diagram of the impedance matching process of the load in the upper region of the present invention;

[0075] Figure 8 This is a diagram showing the relationship between the characteristic impedance and equivalent capacitance at the pin port under different pin depths according to the present invention.

[0076] Figure 9 This is a schematic diagram of the simulation results of the path planning method under load change of the present invention;

[0077] Figure 10 This is a schematic diagram of the simulation results of the path planning method of the present invention when the load changes continuously;

[0078] Figure 11This is a schematic diagram illustrating the division of the upper half of the invention into two regions and the lower half of the invention into two regions;

[0079] In the attached diagram: 1-first pin, 2-second pin, 3-third pin, 4-waveguide, 5-load diaphragm, 6-measurement plane. Detailed Implementation

[0080] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, but the present invention is not limited to the following embodiments.

[0081] Example 1:

[0082] See attached Figures 1-11 A path planning method for a three-pin impedance matcher includes the following steps:

[0083] Step S100: When the load changes, calculate the optimal solution for the depth of the three pins based on the reflection coefficient measured at the port.

[0084] Step S200: Based on the calculated optimal solution for the depth of the three pins, implement a low-reflection adjustment strategy to adjust the depth of the three pins to avoid large reflections during the adjustment process.

[0085] As can be seen from the above structure, three-pin waveguides are commonly used to achieve impedance matching in high-power microwave energy transmission. When the connected load changes, the depth of the three pins needs to be adjusted accordingly to achieve good impedance matching. When the load changes, the load impedance also changes accordingly, causing a change in the port's reflection coefficient. The port's reflection coefficient can be measured using equipment, for example, by measuring the port's reflection coefficient on measurement plane 6 using a vector network analyzer. Then, the load impedance is calculated based on the port's reflection coefficient, thereby calculating the optimal solution for the three-pin depth corresponding to the load. Once the optimal solution for the three-pin depth is calculated, to avoid large reflections during the adjustment process damaging the microwave source and affecting the system's stability, a low-reflection adjustment strategy is implemented to adjust the depth of the three pins. That is, the order of adjustment of the three pins is determined, and the three pins are adjusted sequentially to the optimal depth to complete impedance matching.

[0086] Example 2:

[0087] See attached Figures 1-11 Based on Example 1, the steps for calculating the optimal solution for the depth of the three pins according to the reflection coefficient measured at the port when the load changes include:

[0088] Step S110: Establish the equivalent circuit model of the three-pin waveguide;

[0089] Step S120: Design impedance matching method.

[0090] As can be seen from the above structure, the three-pin impedance matching circuit model structure is as follows: Figure 1 As shown, three pins are sequentially arranged on waveguide 4, forming a structure where a pin and a waveguide segment are arranged in sequence. According to existing waveguide transmission line theory, within a certain depth, a pin can be approximately equivalent to a capacitor, and a waveguide segment can be equivalent to a transmission line segment. Therefore, the three-pin impedance matching circuit can be considered equivalent to a circuit. By adjusting different pins, the three-pin impedance matching circuit can be equivalent to different impedance matching circuits. In reality, a pin cannot be equivalent to an ideal capacitor, and the actual matching process differs from the ideal situation described above, but is roughly the same. By designing a matching method, the relationship between pin depth, load impedance, and reflection coefficient is established, obtaining the reflection coefficient under different loads and pin depths. The depth combination with the minimum reflection coefficient is selected as the optimal solution.

[0091] Specifically, the steps for establishing the equivalent circuit model of the three-pin waveguide include:

[0092] Step S111: Divide the Smith chart into an upper and lower region. Two distributed impedance matching circuits can be found to match the load in both regions. The distributed impedance matching circuit includes two adjustable capacitors and several transmission lines. The length of each transmission line is one-quarter of the waveguide wavelength. The Smith chart is a calculation diagram plotted on the reflection plane with a family of normalized input impedance or admittance equivalent circles, mainly used for impedance matching of transmission lines. Figure 2 As shown, the Smith chart is divided into an upper and lower half. For loads located in the upper half, a distributed impedance matching circuit can be found to match the load, such as... Figure 3 As shown in the upper part, this distributed impedance matching circuit includes two adjustable capacitors, a transmission line, and a load. Different loads in the upper region correspond to two adjustable capacitors of different sizes on this distributed impedance matching circuit. For loads located in the lower region, a distributed impedance matching circuit can also be found to match them, such as... Figure 3 As shown in the lower half, this distributed impedance matching circuit includes two adjustable capacitors, two transmission lines, and a load. Different loads in the lower half correspond to two adjustable capacitors of different sizes on this distributed impedance matching circuit. Figure 3 As shown in the lower half, the load in the lower half first passes through a transmission line. The length of the transmission line is set to one-quarter of the waveguide wavelength. One-quarter of the waveguide wavelength is the impedance matching distance. Therefore, after the load in the lower half passes through a one-quarter waveguide wavelength, its impedance value is transformed to the upper half. The subsequent adjustment process is the same as that in the upper half, reducing the amount of calculation and complexity.

[0093] Step S112: The three pins are set sequentially, and the spacing between the three pins is designed to be one-quarter of the waveguide wavelength; the pin closer to the load end is the third pin 3, and the pin farther from the load end is the first pin 1; l1 and l2 are the waveguide lengths between the pins; λ g Waveguide wavelength; Based on the Smith chart, a three-pin impedance tuner is constructed, such as... Figure 1 As shown, the three pins in the three-pin impedance tuner are arranged sequentially as pin 1, pin 2, and pin 3, and the spacing between the three pins is designed to be one-quarter of the waveguide wavelength.

[0094] Step S113: Equivalently treat a single pin with a certain depth as a parallel capacitor; C1, C2, and C3 are the equivalent capacitors corresponding to the three pins.

[0095] Step S114: Equivalent the waveguide to a series transmission line.

[0096] Step S115: Cascade the equivalent parallel capacitance of the three pins and the equivalent series transmission line of the waveguide to establish an equivalent circuit model consisting of the cascaded parallel equivalent capacitance and the series equivalent transmission line. When the depth h1 of the first pin 1 is 0, the equivalent circuit model corresponds to the distributed impedance matching circuit in the upper half region. When the depth h3 of the third pin 3 is 0, the equivalent circuit model corresponds to the distributed impedance matching circuit in the lower half region. h1, h2, and h3 are the insertion depths of the three pins. From the above structure, it can be seen that when the depth h1 of the first pin 1 is 0, the corresponding equivalent capacitance C1 is 0. The corresponding equivalent circuit model includes two capacitors C2 and C3, the waveguide l2 between C2 and C3, and the load. The equivalent circuit model can correspond to the distributed impedance matching circuit in the upper half region of the Smith chart. Adjusting the third pin 3 is equivalent to adjusting capacitor C3, and adjusting the second pin 2 is equivalent to adjusting capacitor C2. Therefore, for the load located in the upper half region, impedance matching can be completed by adjusting only the third pin 3 and the second pin 2. When the depth h3 of the third pin 3 is 0, the corresponding equivalent capacitance C3 is 0. The corresponding equivalent circuit model includes two capacitors C1 and C2, waveguide l1 between C1 and C2, waveguide l2 between C2 and C3, and the load. This equivalent circuit model corresponds to the distributed impedance matching circuit in the lower half of the Smith chart. Adjusting the first pin 1 is equivalent to adjusting capacitor C1, and adjusting the second pin 2 is equivalent to adjusting capacitor C2. Therefore, for loads located in the lower half of the chart, impedance matching can be achieved by adjusting only the second pin 2 and the first pin 1. Thus, this invention, for different loads, only requires determining whether the load is located in the upper or lower half of the Smith chart to achieve impedance matching by adjusting the corresponding two pins.

[0097] Specifically, the steps of the impedance matching design method include:

[0098] Step S121: Calculate the load: Calculate the load based on the reflection coefficient measured at the port, assuming the initial depth of the three pins is 0.

[0099]

[0100] like Figure 6 As shown, l is the waveguide length; Γ is the reflection coefficient of the port, which can be measured using a vector network analyzer; β is the phase constant; Z L Z is the load impedance; e The equivalent impedance of the waveguide can be calculated using existing formulas: η0 is the characteristic impedance, a is the wide wall length of the waveguide 4-port, and b is the narrow wall length of the waveguide 4-port.

[0101] Step S122: Calculate the equivalent load: There is a waveguide segment between the third pin 3 and the load. The load and this waveguide segment are considered as a new load, i.e., the equivalent load:

[0102]

[0103] η0 is the wave impedance of the waveguide; Z′ L The equivalent load is l3; l3 is the waveguide length between the third pin 3 and the load.

[0104] Step S123, Equivalent load region determination:

[0105] Z′ L ∈(Re(Z)>η0)∪((Re(1 / Z)<1 / η0)∩(Im(1 / Z)<0)) (3)

[0106] If formula (3) is satisfied, the equivalent load is located in the upper half region. The upper half region impedance matching adjustment step is performed to obtain the optimal solution for the depth of the three pins.

[0107] Z′ L ∈((Re(Z)<η0)∩((Im(Z)<0)∪((Re(1 / Z)>1 / η0)) (4)

[0108] If formula (4) is satisfied, the equivalent load is located in the lower half region. The impedance matching adjustment step in the lower half region is performed to obtain the optimal solution for the depth of the three pins; z is the load variable; Re represents taking the real part of a complex number; Im represents taking the imaginary part of a complex number.

[0109] Specifically, the impedance matching adjustment steps in the upper half region include:

[0110] a. Assume that the initial depth of all three pins is 0;

[0111] b. Adjust the third pin 3: Adjust the third pin 3 so that the input impedance at the port of the third pin 3 meets the following conditions:

[0112]

[0113] Ideally, Re(Z3) = η0. However, since the pin cannot be equivalent to an ideal capacitor, the impedance will shift towards the conductance circle during pin adjustment. Therefore, setting 0 < Re(Z3) - η0 < 200 is appropriate. This range is large enough to allow Z3 to be adjusted to a suitable range without significantly increasing the computational load. The value of 200 can also be taken within this range. Figure 7 As shown, assuming the equivalent load is located at position A, first adjust the third pin 3 to satisfy formula (5), such that Z3 reaches position B.

[0114] c. Impedance Transformation: After passing through a quarter waveguide wavelength, Z3 and Z2 are centrally symmetric about the matching point on the Smith chart, i.e., Z3*Z2=η0 2 ,like Figure 7 As shown, the impedance transformation reaches position C.

[0115] d. Adjust the second pin 2: Adjust the second pin 2 so that Re(Z2) = η0, that is, reach position D. The center of the Smith chart is the position with the best impedance matching, and the impedance matching is completed.

[0116] e. Select the optimal solution: Adjust the third pin 3 until the maximum adjustment depth h. max Substitute each value h3 of the third pin that satisfies formula (5) into the calculation to obtain a corresponding value h2 of the second pin, thus minimizing the reflection; select the solution with the smallest reflection coefficient from the many sets as the optimal solution:

[0117]

[0118] The optimal depth for the first, second, and third pins is determined at this point. h max h1, h2, and h3 are the maximum adjustment depth of the pins; h1, h2, and h3 are the insertion depths of the three pins; Z1, Z2, and Z3 are the input impedances of the ports of the first, second, and third pins, respectively.

[0119] Specifically, the impedance matching adjustment steps in the lower half-region include:

[0120] a. Assume that the initial depth of all three pins is 0;

[0121] b. Impedance transformation: After a quarter waveguide wavelength, Z3 and Z2 are exactly centrally symmetrical about the matching point on the Smith chart, i.e., Z3*Z2=η0. 2 ;

[0122] c. Adjust the second pin 2: Adjust the second pin 2 so that the input impedance at the port of the second pin 2 meets the following conditions:

[0123]

[0124] d. Impedance transformation: After a quarter waveguide wavelength, Z2 and Z1 are exactly centrally symmetrical about the matching point on the Smith chart, i.e., Z1*Z2=η0 2 ;

[0125] e. Adjust the first pin 1: Adjust the first pin 1 so that Re(Z1) = η0, and complete the impedance matching;

[0126] f. Select the optimal solution: Adjust the second pin 2 until the maximum adjustment depth h. max Substitute each second pin value h2 that satisfies formula (7) into the calculation to obtain a corresponding first pin value h1, minimizing the reflection; select the solution with the smallest reflection coefficient from the many sets as the optimal solution.

[0127]

[0128] The load in the lower half of the region first passes through a quarter of the waveguide wavelength, and its impedance value is transformed to the upper half of the region. Therefore, its adjustment process is roughly the same as that in the upper half of the region.

[0129] Specifically, the calculation formulas for Z1, Z2, and Z3 are as follows:

[0130]

[0131] P″′0, P″0, and P′0 represent the characteristic impedances of the ports of the third pin 3, the second pin 2, and the first pin 1, respectively; ω is the angular frequency. From the above structure, it can be seen that the characteristic impedance and equivalent capacitance of the pin ports change with the pin depth and can be calculated in advance in the simulation software. When calculating Z1, Z2, and Z3, the characteristic impedance and equivalent capacitance of the pin ports are known regardless of the pin depth. During measurement, a matched load must be connected; the calculation method is as follows:

[0132]

[0133] Y inThe input admittance at the pin port for different pin depths can be directly obtained in the simulation software; ω represents the angular frequency, and the values ​​of P0 and C for different pin depths are as follows: Figure 8 As shown.

[0134] Matching performance test:

[0135] Different diaphragms of varying sizes were used to simulate different load impedances, with each diaphragm representing a different load. Waveguide 4 was first calibrated using a waveguide calibration kit. Then, an external load diaphragm 5 was connected. The reflection coefficient measured at the port was substituted into the program for calculation, and manual adjustment was performed after obtaining the result. In the experiment, waveguide 4, model BJ26, was used. At a microwave frequency f = 2.45 GHz, the wavelengths of waveguide 4 were l = 173.3 mm, a = 86.4 mm, b = 43.2 mm, the phase constant β = 36.258 rad / m, the characteristic impedance η0 = 328.88 Ω, the pin radius was 8.5 mm, the pin was adjusted in 0.2 mm increments, the maximum adjustable depth was 25 mm, l3 = 106 mm, and the quarter-waveguide wavelength was 43.33 mm.

[0136] Table 1 Matching Calculation Results

[0137]

[0138] As shown in Table 1, the matching method of the present invention can quickly and accurately calculate the optimal depth of the pins, and only requires adjusting the depths of two pins to complete the matching. The reflection coefficients after adjustment are significantly reduced compared to those before adjustment, effectively verifying the effectiveness of the matching method of the present invention. Wherein, dB(S) 11 )=20lg|Γ|.

[0139] Example 3:

[0140] See attached Figures 1-11 Based on Example 2, the step of implementing a low-reflection adjustment strategy to adjust the depth of the three pins according to the calculated optimal solution for the depth of the three pins, and avoiding large reflections during the adjustment process, includes:

[0141] Step S210, Matching status determination: When the load value does not change, execute the static matching path adjustment strategy; when the load value changes, execute the dynamic matching path adjustment strategy.

[0142] Step S220, the static matching path adjustment strategy steps include:

[0143] Step S221: Calculate the equivalent load and determine the equivalent load region;

[0144] Step S222: Execute the corresponding path adjustment strategy according to the region where the equivalent load is located;

[0145] When the equivalent load is located in the upper half of the region, the depth of the first pin is 0:

[0146] If Z′ L ∈((Re(1 / z)<1 / η0)∩(Im(1 / Z)<0)), first adjust the third pin to make Im(Z3)=0, then adjust the third pin and the second pin at the same time;

[0147] If Z′ L ∈((Re(Z)>η0)∩(Im(Z)<0)), while adjusting the third pin and the second pin;

[0148] When the equivalent load is located in the lower half of the region, the depth of the third pin is 0:

[0149] If Z′ L ∈((Re(Z)<η0)∩(Im(Z)<0)), first adjust the second pin to make Im(Z2)=0, then adjust the second pin and the first pin at the same time;

[0150] If Z′ L ∈((Re(1 / Z)>1 / η0)∩(Im(1 / Z)<0)), and simultaneously adjust the second pin and the first pin;

[0151] In static matching, the load value remains unchanged, and the initial depth of the three pins is 0. The calculation and determination methods for the equivalent load are shown in formulas (2), (3), and (4). When the equivalent load is located in the upper region, according to the impedance matching method described above, the depth of the first pin 1 is 0. Impedance matching can be completed simply by adjusting the second pin 2 and the third pin 3 to their optimal positions. Figure 11 As shown, the upper region is further divided into two regions, namely A. U and B U The lower half of the region was also divided into two regions, namely A. L and B L ,in:

[0152] A U =((Re(1 / Z)<1 / η0)∩(Im(1 / Z)<0))

[0153] B U =((Re(Z)>η0)∩(Im(Z)<0))

[0154] A L =((Re(Z)<η0)∩(Im(Z)<0))

[0155] B L=((Re(1 / Z)>1 / η0)∩(Im(1 / Z)<0)) (11)

[0156] When the equivalent load is in the upper half region, its imaginary part is zero, and the admittance value is X. According to the ideal equivalent circuit model analysis, when only the third pin 3 is present, the magnitude of the reflection coefficient at the port of the second pin 2 is:

[0157]

[0158] When the third pin 3 and the second pin 2 are adjusted simultaneously, the magnitude of the reflection coefficient at the port of the second pin 2 is:

[0159]

[0160] Where Z0 is the characteristic impedance of the equivalent transmission line, and D = Z0 2 ω 2 C2C3(-2+Z0 2 ω 2 C2C3)+Z0 4 X 2 ω 2 C2 2 Since the reflection coefficient |Γ1| is zero when C2 and C3 reach their maximum values, and (Z0X-1) 2 +(Z0ωC3) 2 Since D > 0, it can be inferred that D < 0 before C2 and C3 reach their maximum values. When D < 0, |Γ1| < |Γ0|, therefore, when the equivalent load is in the upper half of the region, if the load value is located at B... U When the load is in region A, simultaneously adjusting the third pin 3 and the second pin 2 can better suppress the increase in reflection; if the load value is in region A... U When the equivalent load is in the lower half of the region, first adjust the third pin 3 to make Im(Z3) = 0, then simultaneously adjust the third pin 3 and the second pin 2. Similarly, when the equivalent load is in the lower half of the region, if the load value is located at A... L When the load value is in region B, first adjust the second pin 2 to make Im(Z2) = 0, then simultaneously adjust the second pin 2 and the first pin 1; L When adjusting the area, simultaneously adjust the second pin 2 and the first pin 1.

[0161] Step S230, the dynamic matching path adjustment strategy steps include:

[0162] Step S231: Calculate the equivalent load and determine the equivalent load area. The calculation of the equivalent load is shown in formula (2). Assume Z″ L This represents the changed equivalent load. During dynamic matching, the load value changes, and the initial depth of the three pins is not all 0.

[0163] When the equivalent load varies only in the upper half of the region, that is:

[0164]

[0165] As described above, when the load only varies in the upper half of the region, the depth of the first pin 1 is always 0. The second pin 2 and the third pin 3 already have a certain depth and generally only require fine-tuning. First, adjust the third pin 3 to bring the pin port impedance to a suitable position. During this process, the port impedance of the second pin 2 moves closer to the matching point. Then, adjust the second pin 2 again to reach the matching point. Throughout this process, the reflection coefficient decreases. When the equivalent load only varies in the upper half of the region, the depth of the first pin 1 is 0. First, adjust the third pin 3, then adjust the second pin.

[0166] When the equivalent load varies only in the lower half of the region, i.e.:

[0167]

[0168] As can be seen from the above, when the load only changes in the lower half of the region, the depth of the third pin 3 is 0. After passing through a quarter waveguide wavelength, the input impedance of the port of the second pin 2 changes to the upper half of the region. The remaining adjustment process is exactly the same as that in the upper half of the region. Therefore, when the equivalent load only changes in the lower half of the region, the depth of the third pin 3 is 0. First adjust the second pin 2, and then adjust the first pin.

[0169] When the equivalent load changes from the upper half region to the lower half region, that is:

[0170]

[0171] As can be seen from the impedance matching method described above, when the equivalent load is in the lower half-region, the depth of the third pin 3 is 0, while when the original equivalent load is in the upper half-region, the depth of the third pin 3 is not 0. Since the third pin 3 no longer contributes to impedance matching, it needs to be adjusted to 0 first; otherwise, adjusting the remaining two pins may cause significant reflections. Since the second pin 2 always has a depth, it can be considered to be in the B region at this point. U Within this region, under these circumstances, according to the derivation of the above formula, simultaneously adjusting the second pin 2 and the first pin 1 can better suppress the increase in reflection. Therefore, when the equivalent load changes from the upper half region to the lower half region, first adjust the depth of the third pin 3 to 0, and then simultaneously adjust the second pin 2 and the first pin 1.

[0172] When the equivalent load changes from the lower half of the region to the upper half of the region, that is:

[0173]

[0174] As described in the impedance matching method above, when the equivalent load is in the upper region, the depth of the first pin 1 is 0, while when the original equivalent load is in the lower region, the depth of the first pin 1 is not 0. Since the first pin 1 no longer contributes to impedance matching, it needs to be adjusted to 0 first; otherwise, adjusting the remaining two pins may result in significant reflection. When the equivalent load changes to different positions in the upper region, the reflection decreases or remains essentially unchanged while adjusting the first pin 1 to 0. Since the equivalent load has moved to the upper region, after adjusting the first pin 1 to 0, the remaining adjustment method is the same as when the load is in the upper region: first adjust the third pin 3, then adjust the second pin 2. Similarly, since the second pin 2 has a fixed depth, fine-tuning is generally sufficient, ensuring that the reflection decreases substantially when adjusting the third pin 3. Therefore, when the equivalent load changes from the lower half region to the upper half region, first adjust the depth of the first pin 1 to 0, then adjust the third pin 3, and finally adjust the second pin 2.

[0175] Experimental test results of the path planning method show that when the external load changes, after finding the optimal solution for the pin depth, the path planning method of this invention can be used for adjustment, such as... Figure 9 and Figure 10 As shown, it can be seen that when the load changes abruptly, large reflections are avoided during the adjustment of the pins. The path planning method of the three-pin impedance tuner of this invention can quickly and accurately calculate the optimal solution for the pin depth, achieving a good matching effect by adjusting two pins; at the same time, it avoids large reflections during the adjustment process that could damage the microwave source and affect the stability of the system.

[0176] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A path planning method for a three-pin impedance modulator, characterized in that, Includes the following steps: Step S100: When the load changes, calculate the optimal solution for the depth of the three pins based on the reflection coefficient measured at the port. Step S200: Based on the calculated optimal solution for the depth of the three pins, implement a low-reflection adjustment strategy to adjust the depth of the three pins to avoid large reflections during the adjustment process. Specifically, in step S100, when the load changes, the optimal solution for calculating the depth of the three pins based on the reflection coefficient measured at the port includes: Step S110: Establish the equivalent circuit model of the three-pin waveguide; Step S120: Design impedance matching method; Step S120, designing the impedance matching method, includes: Step S121: Calculate the load; Step S122: Calculate the equivalent load; Step S123, Equivalent load region determination: （3） The equivalent load is located in the upper region. The impedance matching adjustment step in the upper region is performed to obtain the optimal solution for the depth of the three pins. （4） The equivalent load is located in the lower half region. The impedance matching adjustment step in the lower half region is performed to obtain the optimal solution for the depth of the three pins. Z is the load variable; This indicates taking the real part of a complex number; This indicates taking the imaginary part of a complex number; The wave impedance of the waveguide; Equivalent load; Specifically, step S200, which involves implementing a low-reflection adjustment strategy to adjust the depth of the three pins based on the calculated optimal solution for the pin depths, and avoiding large reflections during the adjustment process, includes: Step S210, Matching status determination: When the load value does not change, execute the static matching path adjustment strategy; when the load value changes, execute the dynamic matching path adjustment strategy. Step S220, the static matching path adjustment strategy steps include: Step S221: Calculate the equivalent load and determine the equivalent load region; Step S222: Execute the corresponding path adjustment strategy according to the region where the equivalent load is located; When the equivalent load is located in the upper half of the region, the depth of the first pin is 0: like First adjust the third pin so that... Then simultaneously adjust the third pin and the second pin; The input impedance is the input impedance of the third pin port; like At the same time, adjust the third pin and the second pin; When the equivalent load is located in the lower half of the region, the depth of the third pin is 0: like First adjust the second pin so that... Then adjust the second pin and the first pin simultaneously; This is the input impedance of the second pin port; like Simultaneously adjust the second pin and the first pin; Step S230, the dynamic matching path adjustment strategy steps include: Step S231: Calculate the equivalent load and determine the equivalent load region; When the equivalent load only changes in the upper half of the region, the depth of the first pin is 0. First adjust the third pin, then adjust the second pin. When the equivalent load only changes in the lower half of the region, the depth of the third pin is 0. First adjust the second pin, then adjust the first pin. When the equivalent load changes from the upper half region to the lower half region, first adjust the depth of the third pin to 0, and then adjust the second pin and the first pin at the same time. When the equivalent load changes from the lower half of the region to the upper half of the region, first adjust the depth of the first pin to 0, then adjust the third pin, and finally adjust the second pin.

2. The path planning method for a three-pin impedance modulator according to claim 1, characterized in that, Step S121, calculating the load, includes: calculating the load based on the reflection coefficient measured at the port, assuming the initial depth of the three pins is 0: （1） It is the length of the waveguide; The reflection coefficient of the port; It is the phase constant; This is the equivalent impedance of the waveguide; The load impedance; Step S122, calculating the equivalent load, includes: there is a waveguide segment between the third pin and the load; the load and this waveguide segment are considered as a new load, i.e., the equivalent load. （2） The waveguide length between the third pin and the load is given.

3. The path planning method for a three-pin impedance modulator according to claim 2, characterized in that, The impedance matching adjustment steps in the upper half region include: a. Assume that the initial depth of all three pins is 0; b. Adjust the third pin: Adjust the third pin so that the input impedance at the third pin port meets the following condition: （5） c. Impedance transformation: After passing through a quarter waveguide wavelength and The points are centrally symmetric about the matching point on the Smith chart, i.e. ; d. Adjust the second pin: Adjust the second pin so that... This completes impedance matching; e. Select the optimal solution: Adjust the third pin until the maximum adjustment depth is reached. The value of the third pin that satisfies formula (5) Substitute all the values ​​and calculate them to obtain a corresponding value for the second pin. To minimize the resulting reflection, the optimal solution is selected from among many sets of solutions, choosing the set with the smallest reflection coefficient. （6） , , The optimal depth for the first, second, and third pins is determined at this point. =0; This is the maximum adjustment depth of the pin; , , This represents the depth to which the three pins are inserted. This is the input impedance of the first pin socket.

4. The path planning method for a three-pin impedance modulator according to claim 2, characterized in that, The impedance matching adjustment steps in the lower half-region include: a. Assume that the initial depth of all three pins is 0; b. Impedance transformation: After passing through a quarter waveguide wavelength and On the Smith chart, it is exactly centrally symmetric about the matching point, that is... ; c. Adjust the second pin: Adjust the second pin so that the input impedance at the second pin port meets the following condition: （7） d. Impedance transformation: After passing through a quarter waveguide wavelength, and On the Smith chart, it is exactly centrally symmetric about the matching point, that is... ; e. Adjust the first pin: Adjust the first pin so that... This completes impedance matching; f. Select the optimal solution: Adjust the second pin until the maximum adjustment depth is reached. The value of the second pin that satisfies formula (7) Substitute all the values ​​and calculate them to obtain a corresponding value for the first pin. To minimize the resulting reflection, the optimal solution is selected from among many sets of solutions, choosing the set with the smallest reflection coefficient. （8） , , The optimal depth for the first, second, and third pins is determined at this point. =0; This is the maximum adjustment depth of the pin; , , This represents the depth to which the three pins are inserted. This is the input impedance of the first pin port.

5. A path planning method for a three-pin impedance modulator according to claim 3 or 4, characterized in that, The , , The calculation formula is: （9） , , These are the characteristic impedances of the ports of the third pin, the second pin, and the first pin, respectively. Angular frequency; , , This is the equivalent capacitance corresponding to the three pins; , The waveguide length between the pins is denoted as .

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