Substrate and power amplifier device

Abstract

Embodiments of the present application provide a substrate and power amplifier device, relating to the field of semiconductor technology. This invention implements a novel composite substrate that reduces transistor dependence on silicon carbide semiconductor substrates and effectively controls costs. The substrate is used for a transistor, wherein the transistor's epitaxial structure is generated on the substrate. The substrate comprises: a base and a first epitaxial layer formed on the base, the first epitaxial layer being a semiconductor; wherein the base and the first epitaxial layer comprise SiC material; and the first epitaxial layer is doped with a transition metal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate and a power amplifier device. Background Art

[0002] High-electron-mobility transistors (HEMTs) are primarily used as power amplifiers in electronic devices. For example, the radio frequency (RF) signal generated by the RF modulation circuits of electronic devices is very low in power and requires a series of amplification steps to obtain sufficient RF power before it can be fed to the antenna for radiation. To achieve sufficient RF power, an RF power amplifier (PA) must be used to amplify the RF signal. RF PAs are widely used in radar, wireless communications, navigation, satellite communications, electronic countermeasures, and other systems, and are key components in modern wireless communications.

[0003] In the traditional third-generation wireless communications technologies (3G) / 4G era, RF power amplifiers were based on silicon (Si) or gallium arsenide (GaAs) materials. In the 5G era, high-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are widely used in base stations and other equipment due to their high performance. GaN-based HEMTs are typically fabricated by epitaxial growth on high-purity silicon carbide substrates.

[0004] Currently, substrates are typically made of silicon carbide (SiC). The substrate formation process primarily involves sublimating high-purity SiC powder at temperatures exceeding 2000°C using a physical vapor transport (PVT) process to produce SiC crystals. During the SiC crystal growth process, a high-purity growth environment must be maintained (requiring isolation from nitrogen in the air). The SiC crystals are then processed through wire cutting, grinding, and polishing to produce the SiC substrate. High-purity SiC powder is primarily obtained by purifying and reacting high-purity carbon powder and high-purity silicon powder. This requires high material purity, typically exceeding 99.999%. The resulting substrate is an intrinsic semiconductor (or a semiconductor in an intrinsic state), exhibiting a resistivity greater than 1e5 Ω·cm (ohm·cm) and a thickness of 500 μm ± 25 μm. The SiC crystal growth and substrate processing techniques are complex and demanding, resulting in very high substrate costs, which in turn leads to high device costs, limiting the wider application of HEMT devices. In addition, the size of silicon carbide semiconductor substrates is mainly 100mm (4 inches). Further expanding the size to 150mm (6 inches) and 200mm (8 inches) is technically challenging and more expensive. Summary of the Invention

[0005] The present application provides a substrate and a power amplifier device, realizing a new type of composite substrate, reducing the dependence of transistors on silicon carbide semiconductor substrates, and effectively controlling costs.

[0006] In a first aspect, a substrate is provided. The substrate is used for a transistor, such as a HEMT, in which the epitaxial structure of the transistor is formed on the substrate. The substrate comprises: a base and a first epitaxial layer formed on the base, the first epitaxial layer being a semiconductor; wherein the base and the first epitaxial layer comprise SiC material; the first epitaxial layer is doped with a transition metal, and the base is doped with carrier-providing impurities. In the above solution, the substrate can comprise at least two material layers: the base and the first epitaxial layer, wherein the base is primarily SiC material doped with carrier-providing impurities, and the first epitaxial layer is SiC material doped with a transition metal. Since the first epitaxial layer is made of transition metal-doped SiC material, the transition metal compensates for the impurities in the SiC material, thereby increasing the resistivity of the first epitaxial layer, giving it semi-insulating properties and meeting the fabrication requirements of the epitaxial structure. Since the epitaxial structure is not directly fabricated on the base, embodiments of the present application reduce the requirements for the base. This reduces the transistor's reliance on an intrinsic silicon carbide substrate, effectively controlling costs. For example, in the embodiments of the present application, SiC material is used to form the substrate, and transition metal-doped silicon carbide material is used to form the first epitaxial layer having semi-insulating properties. Compared with the prior art which uses all silicon carbide materials to form an intrinsic silicon carbide substrate, the substrate of the present application uses a composite substrate form of a substrate and a first epitaxial layer, which can reduce the amount of intrinsic silicon carbide material used. The substrate can be made of a conductive silicon carbide material doped with impurities that can provide carriers, so that the growth process requirements are much lower than those of the intrinsic silicon carbide material; for example, the substrate can be a conductive SiC material (that is, doped with impurities that can provide carriers), so that the resistivity of the first epitaxial layer is greater than that of the substrate; since the resistivity requirements for the substrate are relatively low, the purity and doping requirements for the silicon carbide powder in the substrate manufacturing process are relatively low, for example, the substrate adopts an N-type substrate (doped with N-type elements) with a relatively low manufacturing cost; in this way, when using SiC powder to form SiC crystals, there is no need to completely isolate the air, and there are no requirements for impurities such as nitrogen N, aluminum Al, and boron B that can provide carriers introduced by unintentional doping in the production process.

[0007] In one possible embodiment, a second epitaxial layer is included between the first epitaxial layer and the substrate, and the second epitaxial layer includes SiC material, wherein the second epitaxial layer and the substrate are formed using different processing techniques. When two or more epitaxial layers are used, at least the second epitaxial layer is included between the first epitaxial layer and the substrate. In this case, only the top epitaxial layer (e.g., the first epitaxial layer) needs to be doped with a transition metal, which can minimize the thickness of the first epitaxial layer. The requirements for the second epitaxial layer are similar to those for the substrate, which can further reduce the amount of intrinsic silicon carbide material used. In addition, the second epitaxial layer and the substrate are formed using different processing techniques. For example, the substrate is mainly formed by growing SiC crystals from silicon carbide powder using a physical vapor transport process (PVT). The SiC crystals are then processed into the substrate through processes such as wire cutting, grinding, and polishing. Since the substrate can be a conductive substrate, the purity of the silicon carbide powder and the process complexity of the PVT are relatively low. Then, the second epitaxial layer is epitaxially grown on the substrate using high-temperature chemical vapor deposition (CVD).

[0008] In one possible embodiment, the second epitaxial layer can be made of conductive silicon carbide material or semi-insulating silicon carbide material. For example, when two or more epitaxial layers are used, only the top epitaxial layer (such as the first epitaxial layer) needs to be doped with transition metals to form a semi-insulating silicon carbide material; while the epitaxial layer in the middle (such as the second epitaxial layer) uses conductive silicon carbide material. This can minimize the thickness of the first epitaxial layer, thereby reducing the amount of transition metal used during doping and reducing the occurrence of crystal defects and crystal polymorphism problems. Alternatively, the second epitaxial layer can be a semi-insulating silicon carbide material formed by doping with transition metals (such as vanadium V or iron Fe) through reactive gas during the epitaxial growth process.

[0009] In one possible implementation, the resistivity of the first epitaxial layer is greater than the resistivity of the substrate. For example, the resistivity of the first epitaxial layer is greater than 1e5 Ω·cm, and the resistivity of the substrate is less than 0.03 Ω·cm.

[0010] In one possible embodiment, the resistivity of the second epitaxial layer is equal to the resistivity of the substrate, for example: the resistivity of the second epitaxial layer is less than 0.03Ω·cm; or the resistivity of the second epitaxial layer is greater than the resistivity of the substrate and less than the resistivity of the first epitaxial layer. For example: the resistivity of the second epitaxial layer can be greater than or equal to 0.03Ω·cm and less than 1e5Ω·cm. In this way, a gradual transition of the resistivity from the substrate to the first epitaxial layer can be achieved. Specifically, the resistivity can be adjusted by controlling the concentration of doped transition metals, so that when the doping concentration of the transition metal in the second epitaxial layer is less than that of the first epitaxial layer, the resistivity of the second epitaxial layer is less than that of the first epitaxial layer. This can also avoid the occurrence of crystal defects and crystal polymorphism problems caused by excessive differences in material properties when the first epitaxial layer is directly made on the substrate. In addition, the resistivity of the second epitaxial layer can also be adjusted by controlling Si vacancies and / or C vacancies during the SiC epitaxial growth process.

[0011] In one possible embodiment, the transition metal includes vanadium V or iron Fe. The first epitaxial layer is mainly realized by doping transition metals during the homoepitaxial growth process of chemical vapor deposition CVD, and the transition metals include vanadium V or iron Fe. When the transition metal vanadium V is used for doping, the vanadium doping is achieved by introducing an appropriate amount of reaction gas of a vanadium compound (such as: VCl4) during the epitaxial growth process. The vanadium impurities in the SiC crystal can serve as deep energy level compensation centers, which can compensate for the nitrogen N and boron B that are not intentionally doped in the SiC crystal, thereby achieving the semi-insulator characteristics of the first epitaxial layer. In addition, it should be noted that when the transition metal iron is used for doping, the vanadium doping is achieved by introducing an appropriate amount of reaction gas of an iron compound (such as: tert-butylferrocene C 14 H 17 Fe) to achieve iron doping.

[0012] In one possible implementation, the doping concentration of the transition metal in the first epitaxial layer 312 is 1e14 cm^-3 to 1e17 cm^-3.

[0013] In one possible embodiment, the thickness of the first epitaxial layer is 1 to 100 μm. When the substrate includes only the base and the epitaxial layer, the thickness of the base is 350 μm ± 25 μm, and the thickness of the first epitaxial layer is 1 to 100 μm, so that the substrate thickness can meet the requirements of the epitaxial structure of the epitaxial transistor.

[0014] In one possible embodiment, the thickness of the first epitaxial layer is 1 to 50 μm, and the thickness of the second epitaxial layer is 1 to 50 μm. When the substrate comprises only a base and at least two epitaxial layers, the thickness of each of the two epitaxial layers can be thinned to 1 to 50 μm, thereby minimizing the thickness of the top first epitaxial layer.

[0015] In a possible implementation, the unit cell of the SiC material adopts a 4H structure.

[0016] In a second aspect, a method for manufacturing a substrate is provided, wherein the substrate is used for a transistor, wherein an epitaxial structure of the transistor is generated on the substrate, and the manufacturing method comprises: performing surface processing on a surface of the substrate; manufacturing a first epitaxial layer on the substrate, wherein the substrate and the first epitaxial layer comprise SiC material; the first epitaxial layer is doped with a transition metal, and the substrate is doped with impurities that provide carriers.

[0017] In a possible implementation, before forming the first epitaxial layer on the substrate, the method further includes forming a second epitaxial layer on the substrate, wherein the second epitaxial layer includes SiC material.

[0018] In one possible embodiment, the surface processing includes one or more of cutting, grinding, and polishing. After the surface of the substrate is processed, the surface roughness of the substrate is less than or equal to 0.5 nm.

[0019] In a possible embodiment, after surface processing the substrate, the method further includes etching the substrate surface to form atomic-scale steps, wherein the steps have a width of 1 nm to 3 μm and a height of 0.25 nm to 2 nm.

[0020] In a possible implementation, forming the first epitaxial layer on the substrate includes: epitaxially growing the first epitaxial layer on the substrate using a chemical vapor deposition process.

[0021] In a possible implementation, the gases used in the chemical vapor deposition process include: silane SiH4, propane C3H8, and a transition metal compound.

[0022] In one possible embodiment, the transition metal compound includes vanadium tetrachloride VCL4 or tert-butylferrocene C 14 H 17 Fe.

[0023] In a possible implementation, forming the second epitaxial layer on the substrate includes: epitaxially growing the second epitaxial layer on the substrate using a chemical vapor deposition process.

[0024] In a possible implementation, the gases used in the chemical vapor deposition process include: SiH4, propane C3H8.

[0025] In a possible implementation, after forming the second epitaxial layer on the substrate, the method further includes: performing surface processing on the second epitaxial layer so that the surface roughness of the second epitaxial layer is less than 0.5 nm.

[0026] In a possible implementation, after forming the first epitaxial layer on the substrate, the method further includes: performing surface processing on the first epitaxial layer so that the surface roughness of the first epitaxial layer is less than 0.5 nm.

[0027] In a third aspect, a power amplifier device is provided, comprising a substrate and an epitaxial structure of a transistor formed on the substrate, wherein the substrate comprises the substrate as described above.

[0028] In a possible implementation, the epitaxial structure includes: a buffer layer disposed on the first epitaxial layer; a barrier layer disposed on the buffer layer; and an electrode is disposed on the barrier layer.

[0029] In a possible implementation, the epitaxial structure further includes: a nucleation layer disposed between the first epitaxial layer and the buffer layer.

[0030] In a possible implementation, the epitaxial structure further includes: an insertion layer disposed between the buffer layer and the barrier layer.

[0031] In a fourth aspect, an electronic device is provided, comprising a power amplifier device and an antenna, wherein the power amplifier device is used to amplify a radio frequency signal and output the amplified signal to the antenna for outward radiation, and the power amplifier device comprises the power amplifier device described above.

[0032] In a fifth aspect, a non-transitory computer-readable storage medium is provided for use with a computer having software for designing integrated circuits, the computer-readable storage medium having one or more computer-readable data structures stored thereon, and the process equipment using the above-mentioned one or more computer-readable data structures to manufacture the substrate provided above.

[0033] Among them, the technical effects brought about by any possible implementation method in the second to fifth aspects can refer to the technical effects brought about by the different implementation methods in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a hexagonal crystal system provided in an embodiment of the present application;

[0035] Figure 2 A schematic structural diagram of a base station provided in an embodiment of the present application;

[0036] Figure 3 A schematic structural diagram of a base station provided in another embodiment of the present application;

[0037] Figure 4 A schematic structural diagram of a power amplifier device provided in an embodiment of the present application;

[0038] Figure 5 A schematic structural diagram of a substrate provided in an embodiment of the present application;

[0039] Figure 6 A schematic structural diagram of a substrate provided in another embodiment of the present application;

[0040] Figure 7 A schematic structural diagram of a substrate provided in yet another embodiment of the present application;

[0041] Figure 8 A schematic structural diagram of a substrate provided in yet another embodiment of the present application;

[0042] Figure 9 A schematic flow chart of a method for manufacturing a substrate provided in an embodiment of the present application;

[0043] Figure 10 A schematic diagram of the structure of a substrate during the manufacturing process provided in an embodiment of the present application Figure 1 ;

[0044] Figure 11 A schematic diagram of the structure of a substrate during the manufacturing process provided in an embodiment of the present application Figure 2 ;

[0045] Figure 12 A schematic diagram of the structure of a substrate during the manufacturing process provided in an embodiment of the present application Figure 3 ;

[0046] Figure 13 A schematic flow chart of a method for manufacturing a substrate provided in accordance with another embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0048] The following are the technical terms used in the embodiments of the present application:

[0049] Hexagonal crystal system refers to the crystal system with six-fold or six-fold anti-axis symmetry elements in the direction of the c-axis, which is the only high-order axis. The hexagonal crystal system is also called "hexagonal galaxy" and belongs to the intermediate crystal family. Figure 1As shown, in the hexagonal crystal system, the four crystal axes a1, a2, a3 and c are usually used to calibrate the crystal plane index and crystal direction index to reflect the crystal direction and crystal plane of the hexagonal atoms. Among them, the crystal direction refers to the direction of the array of points in the space lattice (the direction of the straight line connecting any node column in the lattice). In the hexagonal crystal system, the crystal direction is used to indicate certain directions in the crystal, involving the position of atoms in the crystal, the direction of atomic columns, and identifies the direction of a group of parallel straight lines with the same direction. A crystal plane refers to a plane passing through any lattice point in the space lattice (a plane formed by nodes in the lattice). In the hexagonal crystal system, a crystal plane is used to indicate a plane formed by atoms in the crystal. For example, in Figure 1 Taking the hexagonal crystal structure of SiC as an example, the crystal direction of the c-axis is

[0001] , and the crystal direction of the a1 axis is The crystal direction of the a2 axis is The crystal direction of the a3 axis is Figure 1 Two crystal planes are also shown and in Figure 1 The white dots in the middle are Si atoms, and the black dots are C atoms.

[0050] Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, with equal concentrations of electrons and holes, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor. Among them, the impurities doped into the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, where impurity semiconductors doped with impurities that provide electrons (such as pentavalent phosphorus) are also called electron-type semiconductors or N (negative)-type semiconductors, and impurity semiconductors doped with impurities that provide holes (such as trivalent boron) are also called hole-type semiconductors or P (positive)-type semiconductors), which can improve the conductivity of the intrinsic semiconductor. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of the present application, this type of impurity semiconductor is also called a conductive semiconductor. For example, the conductive silicon carbide material is doped with impurities such as nitrogen N, boron B, aluminum Al, etc. Furthermore, when the impurities introduced into the impurity semiconductor are capable of impurity compensation for the impurity semiconductor, the donor electrons are just sufficient to fill the acceptor energy levels, but are unable to provide electrons and holes to the conduction and valence bands, resulting in a wide-bandgap semiconductor material with a resistivity similar to that of an insulator. For example, in the embodiments of the present application, doping a silicon carbide material with a transition metal achieves impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also referred to as a semi-insulating semiconductor or semi-insulator, or has semi-insulating properties.

[0051] Unless otherwise defined, all scientific and technological terms used herein have the same meaning as those known to those of ordinary skill in the art. In this application, "at least one" refers to one or more, and "a plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, wherein A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following items" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit quantity and order.

[0052] In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0053] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0054] The technical solutions of this application can be applied to electronic devices, including various types of user equipment or terminal devices, such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices. These electronic devices can also be network devices such as base stations. The electronic devices can also be devices such as power amplifiers used in these electronic devices. The embodiments of this application do not impose any particular restrictions on the specific form of these electronic devices.

[0055] The electronic device provided in the embodiment of the present application takes a 5G base station as an example. The 5G base station can be divided into different architectures such as baseband unit (BBU)-active antenna unit (AAU), central unit-distribute unit (CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, and integrated 5G base station (5G node base station, gNB). Taking the base station with BBU-AAU architecture as an example, refer to Figure 2 As shown, the base station includes a BBU 11 and an AAU 12; wherein the BBU 11 transmits the generated baseband digital signal through the AAU 12. Figure 3 As shown, the AAU includes a digital-to-analog conversion module 121 (for example, a DAC (digital to analog converter), a radio frequency unit 122, a power amplifier 123 (PA), and an antenna 124. The digital-to-analog conversion module 121 is used to convert the baseband digital signal output by the baseband processing unit into an analog signal, the radio frequency unit 122 is used to convert the analog signal into a low-power radio frequency signal, and the power amplifier 123 is used to amplify the low-power radio frequency signal and output it to the antenna 124 for outward radiation. Figure 3 The AAU shown includes n antennas 124, each antenna 124 corresponds to a set of digital-to-analog conversion modules 121, radio frequency units 122, and power amplifiers 123. Of course, the embodiments of the present application are not limited to the above. Figure 2 、 Figure 3 The base station shown, it can be understood that any of the above electronic devices that need to use a power amplifier to amplify the signal belongs to the application scenario of the embodiment of the present application.

[0056] Among them, such as Figure 4 As shown, the embodiment of the present application provides a power amplifier device 30 (wherein the power amplifier device 30 may be Figure 3The power amplifier 123 in the embodiment mainly includes a substrate 31 and an epitaxial structure 32 of a transistor fabricated on the substrate 31. The epitaxial structure 32 mainly includes a nucleation layer 321, a buffer layer 322, an insertion layer 323, and a barrier layer 324 disposed on the substrate 31. Electrodes, such as a gate 35, a source 33, and a drain 34, are disposed on the epitaxial structure 32. The electrodes are covered with a passivation layer 36. Taking a high electron mobility transistor (HEMT) as an example, the transistor is a high electron mobility transistor (HEMT). The nucleation layer 321 in the epitaxial structure 32 is typically made of aluminum nitride (AlN) material, the buffer layer 322 is typically made of GaN material, the insertion layer 323 is typically made of aluminum nitride (AlN) material, the barrier layer 324 is typically made of aluminum gallium nitride (AlGaN) material, and the electrodes are typically made of metal material. The source 33 and the drain 34 respectively form conductive ohmic contacts with the barrier layer 324, and the gate 35 forms a Schottky contact with the barrier layer 324. The dotted line in the buffer layer 322 represents the two-dimensional electron gas (2DEG) generated in the heterostructure formed by the buffer layer 322 and the barrier layer 324 in the HEMT. The two-dimensional electron gas moves along the plane direction (such as Figure 3 In the figure, the mobility of the buffer layer 322 (dashed line) is very high and is fundamental to the operation of the HEMT. The insertion layer 323 functions to increase the density, localization, and mobility of the two-dimensional electron gas, thereby improving device performance, such as achieving excellent switching performance. Therefore, the insertion layer 323 is an optional structure. Without the insertion layer 323 in the HEMT, device performance will be reduced. Furthermore, the nucleation layer 321 is also an optional structure, and its main function is to serve as a transition when the crystal structures of the buffer layer 322 and the substrate 31 materials differ significantly. For example, when the crystal structures of the buffer layer 322 and the substrate 31 differ significantly, the nucleation layer 321 can be first epitaxially grown on the substrate, with a crystal structure less different from that of the substrate 31, and then the buffer layer 322 can be epitaxially formed on the nucleation layer 32.

[0057] In the embodiment of the present application, the substrate 31 is a composite substrate, such as Figure 5 As shown, the substrate 31 includes a base 311 and a first epitaxial layer 312 formed on the base 311. The first epitaxial layer 312 is a semiconductor. The base 311 and the first epitaxial layer 312 are made of SiC material. The first epitaxial layer 312 is doped with a transition metal, and the base 311 is doped with impurities that provide carriers.

[0058] In one embodiment, the unit cell of the SiC crystal formed by SiC material in the first epitaxial layer 312 and the substrate 311 mainly adopts a 4H (4-hexagonal, 4 layers of carbon silicon atoms in a hexagonal crystal system) structure. The resistivity of the first epitaxial layer 312 is greater than the resistivity of the substrate. Specifically, the substrate can adopt a conductive SiC material. For example, the resistivity of the substrate 311 is less than 0.03Ω·cm, the thickness of the substrate 311 is 350μm±25μm, and the diameter is 100mm, 150mm or 200mm. The first epitaxial layer 312 is mainly realized by doping transition metals during homoepitaxial growth by chemical vapor deposition (CVD), and the transition metals include vanadium V or iron Fe. When transition metal vanadium V is used for doping, vanadium doping is achieved by introducing an appropriate amount of reaction gas of a vanadium compound (such as VCl4) during the epitaxial growth process. The vanadium impurities in the SiC crystal can serve as deep energy level compensation centers, which can compensate for the nitrogen N and boron B that are not intentionally doped in the SiC crystal, thereby achieving the semi-insulator characteristics of the first epitaxial layer 312. The doping concentration of the transition metal in the first epitaxial layer 312 is 1e14cm^-3 to 1e17cm^-3, the resistivity of the first epitaxial layer 312 is greater than 1e5Ω·cm, and the thickness of the first epitaxial layer 312 is 1 to 100μm. In addition, it should be noted that when transition metal iron is used for doping, it is achieved by introducing an appropriate amount of reaction gas of an iron compound (such as tert-butylferrocene C 14 H 17 Fe) to achieve iron doping.

[0059] The substrate formation process primarily involves using silicon carbide powder, which is sublimated at high temperatures using PVT to produce SiC crystals, which are then cut using wire cutting. When the substrate resistivity requirement is low, the substrate manufacturing process also requires lower purity and doping of the silicon carbide powder. For example, the substrate can use a relatively low-cost N-type substrate (doped with N-type elements). This eliminates the need for complete isolation from air when using SiC powder to form SiC crystals, and eliminates the need for nitrogen (N), aluminum (Al), and boron (B) introduced unintentionally during the production process.

[0060] In addition, combined Figure 5 、 Figure 6 As shown, since the first epitaxial layer 312 is formed by epitaxial growth directly on the substrate, the first epitaxial layer 312 and the SiC crystal in the substrate 311 are in the same direction. Figure 5 As shown, the vertical surface of the substrate 31 adopts the

[0001] crystal axis of the SiC crystal, or is close to the

[0001] crystal axis, such as the axial deviation angle α (0 to 4 degrees) (refer to Figure 7 As shown). Figure 5 、 Figure 6 As shown, the primary orientation flat of the horizontal surface of the substrate 31 is direction (also called large cutting edge), the secondary crystal direction (second orientation flat) is In addition, the ratio of the length of the large cutting edge to the length of the small cutting edge is generally less than 2. For example, the length of the large cutting edge is 32.5 mm and the length of the small cutting edge is 18 mm.

[0061] In the above scheme, the substrate can be made of at least two material layers, namely a base and a first epitaxial layer, wherein the base is mainly made of SiC material and doped with impurities that provide carriers, and the first epitaxial layer is made of SiC material doped with a transition metal. In this way, since the first epitaxial layer is made of SiC material doped with a transition metal, the impurities of the SiC material are compensated by the transition metal, thereby increasing the resistivity of the first epitaxial layer, so that the first epitaxial layer has the characteristics of a semi-insulator, meeting the production requirements of the epitaxial structure. Since the epitaxial structure is not directly produced on the base, the embodiment of the present application reduces the requirements for the base. Thus, the dependence of the transistor on the intrinsic state of silicon carbide substrate is reduced, effectively controlling the cost. For example: in the embodiment of the present application, SiC material is used to form the base, and transition metal-doped silicon carbide material is used to form the first epitaxial layer with semi-insulator characteristics. Compared with the prior art that uses all silicon carbide materials to form the intrinsic state of silicon carbide substrate, the substrate of the present application uses a composite substrate form of the base and the first epitaxial layer, which can reduce the amount of intrinsic state silicon carbide material used. The substrate can be made of a conductive silicon carbide material doped with impurities that can provide carriers, so that the growth process requirements are much lower than those of the intrinsic silicon carbide material; for example, the substrate can be a conductive SiC material (that is, doped with impurities that can provide carriers), so that the resistivity of the first epitaxial layer is greater than the resistivity of the substrate; since the resistivity requirements for the substrate are relatively low, the purity and doping requirements for the silicon carbide powder in the substrate manufacturing process are relatively low, for example, the substrate adopts an N-type substrate with a relatively low manufacturing cost (doped with N-type elements); in this way, when using SiC powder to form SiC crystals, there is no need to completely isolate the air, and there are no requirements for impurities such as nitrogen N, aluminum Al, and boron B that can provide carriers introduced by unintentional doping in the production process.

[0062] In one embodiment, the substrate 31 may be in the form of multiple epitaxial layers on a base 311, such as Figure 8As shown, a second epitaxial layer 313 is included between the first epitaxial layer 312 and the substrate 311, and the second epitaxial layer 313 includes SiC material, wherein the second epitaxial layer and the substrate are formed using different processing techniques. When the second epitaxial layer is included between the first epitaxial layer and the substrate, the thickness of the first epitaxial layer can be reduced as much as possible, wherein the requirements for the second epitaxial layer are similar to those for the substrate, which can further reduce the amount of intrinsic silicon carbide material used. The second epitaxial layer can be made of conductive silicon carbide material or silicon carbide material with semi-insulating properties. The resistivity of the second epitaxial layer can be equal to the resistivity of the substrate, for example: the resistivity of the second epitaxial layer is less than 0.03Ω·cm. When two or more epitaxial layers are used, only the top epitaxial layer (e.g., the first epitaxial layer 313) needs to be doped with transition metal to form a semiconductor; and the epitaxial layer in the middle (e.g., the second epitaxial layer) uses a conductive epitaxial layer, which can minimize the thickness of the first epitaxial layer. For example, the thickness of the first epitaxial layer is 1 to 50 μm, and the thickness of the second epitaxial layer is 1 to 50 μm. The sum of the thickness of the substrate, the first epitaxial layer, and the second epitaxial layer is substantially the same. Figure 3The substrate shown is equivalent, but since only the first epitaxial layer needs to be doped, the amount of transition metal used during doping is reduced, and the occurrence of crystal defects and crystal polymorphism problems is also reduced. In addition, the resistivity of the second epitaxial layer is greater than the resistivity of the substrate and less than the resistivity of the first epitaxial layer. For example, the resistivity of the second epitaxial layer can also be greater than or equal to 0.03Ω·cm and less than 1e5Ω·cm. This can achieve a gradual transition in resistivity from the substrate to the first epitaxial layer. The second epitaxial layer can be a semi-insulating silicon carbide material formed by doping a transition metal (such as vanadium V or iron Fe) with a reactive gas during the epitaxial growth process. The resistivity can be adjusted by controlling the concentration of the doped transition metal. In this way, when the doping concentration of the transition metal in the second epitaxial layer is less than that of the first epitaxial layer, the resistivity of the second epitaxial layer is less than that of the first epitaxial layer. This can also avoid the occurrence of crystal defects and crystal polymorphism problems caused by excessive differences in material properties when the first epitaxial layer is directly formed on the substrate. Furthermore, the resistivity of the second epitaxial layer can also be adjusted by controlling the Si vacancies and / or C vacancies during the SiC epitaxial growth process. This adjustment can be achieved by controlling the ratio of C atoms to Si atoms in the gas used for epitaxial growth of the second epitaxial layer. In this embodiment, the SiC crystal formed by the SiC material of the second epitaxial layer 313 primarily adopts a 4H structure. Of course, more epitaxial layers can be included between the first epitaxial layer and the substrate. When more epitaxial layers are used, the structure of these epitaxial layers is the same as that of the second epitaxial layer. Furthermore, the second epitaxial layer and the substrate are formed using different processing techniques. For example, the substrate is primarily formed by growing SiC crystals using physical vapor transport (PVT) using silicon carbide powder. The SiC crystals are then processed through wire cutting, grinding, and polishing to obtain the substrate. Since the substrate can be a conductive substrate, the purity of the silicon carbide powder and the complexity of the PVT process are less demanding. The second epitaxial layer is then epitaxially grown on the substrate using high-temperature chemical vapor deposition (CVD).

[0063] In one embodiment, an embodiment of the present application provides a method for manufacturing a substrate, comprising the following steps:

[0064] 101. Perform surface processing on the surface of the substrate.

[0065] The surface roughness of the substrate after surface processing, including one or more of cutting, grinding, and planing and milling, is ≤0.5nm. The substrate is primarily made of silicon carbide powder grown via physical vapor transport (PVT) to obtain SiC crystals, which are then processed through wire cutting, grinding, and polishing to obtain the substrate. Since the substrate can be a conductive substrate (e.g., doped with carrier-providing impurities), the purity of the silicon carbide powder and the complexity of the PVT process are relatively low.

[0066] 102. A first epitaxial layer is fabricated on a substrate, wherein the substrate and the first epitaxial layer include SiC material; the first epitaxial layer is doped with a transition metal and is a semiconductor.

[0067] Specifically, in one embodiment, when making Figure 5 The substrate shown is referenced Figure 9 As shown, the specific steps include:

[0068] 201. Perform surface processing on the surface of the substrate 311.

[0069] In the embodiment of the present application, the substrate 311 is made of a conductive material, and the substrate 311 includes a SiC material. For example, the SiC material in the substrate can be a SiC crystal whose unit cell mainly adopts a 4H (4-hexagonal, 4 layers of carbon silicon atoms in a hexagonal system) structure. The resistivity of the substrate 311 is less than 0.03Ω·cm, the thickness of the substrate 311 is 350μm±25μm, and the diameter is 100mm, 150mm or 200mm. Figure 10 As shown, referring to the partial enlarged view of the surface of the substrate 311, the vertical surface of the substrate 311 adopts the

[0001] crystal axis of the SiC crystal, or is close to the

[0001] crystal axis, such as the axial deviation angle α (0-4 degrees).

[0070] 202. Etch the surface of the substrate 311 to form steps of atomic size.

[0071] In step 202, the surface of the substrate 311 is further etched by an etching process to obtain a step 3110 of atomic size. Figure 11 As shown in the partially enlarged schematic diagram of the step 3110, the width of the step 3110 is generally 1nm to 3um, and the height of the step 3110 is generally 0.25nm to 2nm. In this step, the etching process adopts hydrogen H2 etching, the etching temperature is 1500 to 1700 degrees, and the etching time is from 10 minutes to 200 minutes. The purpose of making the atomic-scale step in step 202 is to adjust the effect of the axial deflection angle α on the production of the first epitaxial layer, for example, Figure 10 As shown, when the vertical surface of the substrate 311 has an axial deviation angle α to the left, as shown in Figure 11 The steps shown extend from left to right. When the vertical surface of substrate 311 has an axial deviation angle α to the right, the steps extend from right to left. In addition, the steps can be continuously distributed on the surface of substrate 311 or periodically distributed on the surface of substrate 311. Therefore, when the vertical surface of substrate 311 adopts the

[0001] crystal axis of SiC crystal, step 202 can be omitted.

[0072] 203 . Form a first epitaxial layer 312 on the substrate 311 .

[0073] The first epitaxial layer 312 includes SiC material; the first epitaxial layer 312 is doped with transition metal. In step 203, the first epitaxial layer 312 is epitaxially grown on the substrate using a chemical vapor deposition process. Figure 12 As shown. After the surface etching of the substrate is completed, homogeneous epitaxy of the conductive SiC substrate is carried out (that is, the first epitaxial layer and the substrate use the same SiC material). Epitaxy is completed in a high-temperature chemical vapor deposition (CVD) device. The temperature of epitaxial growth is 1400-1700 degrees. The gases used for epitaxy are mainly silane SiH4, propane C3H8, HCl, H2 and VCl4. Among them, silane SiH4 and propane C3H8 are mainly used to react to obtain SiC. Vanadium tetrachloride VCl4 gas is mainly used to provide the transition metal V element for doping. H2 is a carrier gas, and HCl is a growth additive. Its main function is to promote the growth rate of the silicon carbide epitaxial layer. By doping with the V element, the first epitaxial layer is obtained. The resistivity of the first epitaxial layer is greater than 1e5Ω·cm. Usually the V doping concentration is between 1e14 and 1e17cm^-3. The thickness of the first epitaxial layer is generally 10 to 100um. By adjusting the ratio of different gases, flow rates and growth process conditions, an epitaxial crystal structure based on 4H-SiC (SiC crystal with 4H structure) can be obtained. Usually, the etching process of step 202 and the epitaxial process of step 203 are completed in the same CVD equipment to ensure that the substrate after etching is not contaminated by secondary contamination. In addition, in step 203, if the first epitaxial layer is doped with transition metal iron, a certain proportion of tert-butylferrocene (C 14 H 17 Fe) gas replaces vanadium tetrachloride VCl4 gas to achieve silicon carbide doping.

[0074] 204 . Perform a surface processing on the first epitaxial layer 312 .

[0075] In the process of epitaxially growing the first epitaxial layer on the substrate, impurities and defects are prone to appear due to the instability of the process. For example, vanadium compounds react with the gas used for silicon carbide epitaxy to form intermediate products or precipitates or generate other crystal forms (such as 3C-SiC crystal form, 3-cubic, 3-layer carbon silicon atomic cubic crystal system) to cause impurities or micro defects. A step of surface processing (such as grinding, polishing, cutting) is required to remove some impurities 3121 and micro defects 3122 on the surface of the first epitaxial layer, so that the surface roughness of the first epitaxial layer is less than 0.5nm. Finally, the result is as follows. Figure 5 The substrate shown.

[0076] At this point, the epitaxial structure 32 of the transistor (such as Figure 4 Then, through device processing technology, the electrodes forming the transistor are obtained to form the transistor.

[0077] Specifically, in one embodiment, when making Figure 8 The substrate is referred to as Figure 13 As shown, the specific steps include:

[0078] 301. Perform surface processing on the surface of the substrate.

[0079] Among them, the specific process of step 301 can refer to the production process of step 201, and will not be described in detail.

[0080] 302. Etch the surface of the substrate to form atomic-scale steps.

[0081] Among them, the specific steps of step 302 can refer to the production process of step 202, and will not be described in detail.

[0082] 303. Fabricate a second epitaxial layer on the substrate.

[0083] The second epitaxial layer includes SiC material; wherein in step 303, a chemical vapor deposition process is specifically used to epitaxially grow the second epitaxial layer on the substrate. After completing the surface etching of the substrate, homogeneous epitaxy of the conductive SiC substrate is performed (that is, the second epitaxial layer and the substrate use the same SiC material). Epitaxy is completed in a high-temperature chemical vapor deposition (CVD) device. The temperature of epitaxial growth is 1400-1700 degrees. The gases used for epitaxy are mainly silane SiH4, propane C3H8, HCl, H2 and other gases, among which silane SiH4 and propane C3H8 are mainly used to react to obtain SiC. The resistivity of the second epitaxial layer is less than 0.03Ω·cm. By adjusting the ratio of different gases, flow rate and growth process conditions, an epitaxial crystal structure mainly composed of 4H-SiC (SiC crystal with 4H structure) can be obtained. In step 303, a transition metal (such as vanadium (V) or iron (Fe)) can be doped with a reactive gas during the epitaxial growth of the second epitaxial layer. The resistivity can be adjusted by controlling the concentration of the doped transition metal. Alternatively, the resistivity of the second epitaxial layer can be adjusted by controlling Si vacancies during the SiC epitaxial growth process. Typically, the etching process in step 302 and the epitaxial process in step 303 are performed within the same CVD equipment to prevent secondary contamination of the etched substrate.

[0084] 304. Perform surface processing on the second epitaxial layer.

[0085] During the epitaxial growth of the second epitaxial layer on the substrate, impurities and defects are prone to appear due to process instability. For example, the formation of other crystal forms (such as 3C-SiC) may cause impurities or microscopic defects. Surface processing (such as cutting, grinding, and polishing) is required to remove some impurities and microscopic defects on the surface of the second epitaxial layer, so that the surface roughness of the second epitaxial layer is less than 0.5 nm. Of course, if the surface roughness of the second epitaxial layer meets the requirements for the next step of forming the first epitaxial layer after step 303, step 304 can be omitted.

[0086] 305. Fabricate a first epitaxial layer on the second epitaxial layer.

[0087] The process of forming the first epitaxial layer on the second epitaxial layer also adopts homoepitaxial growth, so the process is the same as the method of forming the first epitaxial layer on the substrate. For details, please refer to step 204 and will not be repeated here.

[0088] 306. Perform surface processing on the first epitaxial layer.

[0089] The specific details of step 306 may refer to the production process of step 204 and will not be described in detail.

[0090] At this point, the epitaxial structure 32 of the transistor (such as Figure 4 Then, through device processing technology, the electrodes forming the transistor are obtained to form the transistor.

[0091] In another aspect of the present application, a non-transitory computer-readable storage medium for use with a computer is provided, wherein the computer has software for designing integrated circuits, and one or more computer-readable data structures are stored on the computer-readable storage medium, and the process equipment uses the above-mentioned one or more computer-readable data structures to manufacture the substrate provided above.

[0092] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A substrate, characterized in that For a transistor, the transistor includes a HEMT, wherein the epitaxial structure of the transistor is generated on the substrate, the substrate includes: a base and a first epitaxial layer formed on the base, the first epitaxial layer is a semiconductor; the epitaxial structure includes a buffer layer provided on the substrate; Wherein, the substrate and the first epitaxial layer include SiC material; The first epitaxial layer is doped with a transition metal, and the substrate is doped with impurities that provide carriers; a second epitaxial layer is included between the first epitaxial layer and the substrate, and the second epitaxial layer includes SiC material, wherein the second epitaxial layer and the substrate are formed using different processing techniques; the resistivity of the second epitaxial layer is greater than the resistivity of the substrate, and the resistivity of the second epitaxial layer is less than the resistivity of the first epitaxial layer.

2. The substrate according to claim 1, wherein The resistivity of the first epitaxial layer is greater than the resistivity of the substrate.

3. The substrate according to claim 1 or 2, characterized in that The transition metal includes vanadium V or iron Fe.

4. The substrate according to any one of claims 1 to 3, characterized in that The doping concentration of the transition metal in the first epitaxial layer is 1e14 cm^-3 to 1e17 cm^-3.

5. The substrate according to any one of claims 1 to 4, characterized in that The resistivity of the substrate is less than 0.03Ω·cm.

6. The substrate according to any one of claims 1 to 5, characterized in that The resistivity of the first epitaxial layer is greater than 1e5Ω·cm.

7. The substrate according to claim 1, wherein The resistivity of the second epitaxial layer is less than 0.03Ω·cm.

8. The substrate according to any one of claims 1 to 7, characterized in that The unit cell of the SiC material adopts a 4H structure.

9. A method for manufacturing a substrate, characterized in that: The substrate is used for a transistor, the transistor including a HEMT, wherein an epitaxial structure of the transistor is generated on the substrate, the epitaxial structure including a buffer layer provided on the substrate; The preparation method comprises: performing surface processing on the surface of the substrate; Before forming the first epitaxial layer on the substrate, the method further includes: forming a second epitaxial layer on the substrate, wherein the second epitaxial layer includes SiC material; A first epitaxial layer is fabricated on the substrate, wherein the substrate and the first epitaxial layer comprise SiC material; the first epitaxial layer is doped with a transition metal, the first epitaxial layer is a semiconductor, and the substrate is doped with impurities that provide carriers; the resistivity of the second epitaxial layer is greater than the resistivity of the substrate, and the resistivity of the second epitaxial layer is less than the resistivity of the first epitaxial layer.

10. The method for manufacturing a substrate according to claim 9, wherein: The surface processing includes one or more of cutting, grinding and polishing.

11. The method for manufacturing a substrate according to claim 9 or 10, characterized in that: After surface processing is performed on the surface of the substrate, the method further comprises: The surface of the substrate is etched to form steps of atomic size.

12. The method for manufacturing a substrate according to any one of claims 9 to 11, characterized in that: Producing a first epitaxial layer on the substrate includes: A first epitaxial layer is epitaxially grown on the substrate by adopting a chemical vapor deposition process.

13. The method for manufacturing a substrate according to claim 12, wherein: The gases used in the chemical vapor deposition process include silane SiH4, propane C3H8, and transition metal compounds.

14. The method for manufacturing a substrate according to claim 13, wherein: The transition metal compound includes vanadium tetrachloride VCL4 or tert-butylferrocene C 14 H 17 Fe.

15. A power amplifier device, characterized in that: The invention comprises a substrate and an epitaxial structure of a transistor formed on the substrate, wherein the substrate comprises the substrate according to any one of claims 1 to 8.

16. The power amplifier device according to claim 15, wherein: The epitaxial structure includes: a buffer layer disposed on the first epitaxial layer, and a barrier layer disposed on the buffer layer; and an electrode is disposed on the barrier layer.

17. The power amplifier device according to claim 16, wherein: The epitaxial structure further includes a nucleation layer disposed between the first epitaxial layer and the buffer layer.

18. The power amplifier device according to claim 17, wherein: The epitaxial structure further includes an insertion layer disposed between the buffer layer and the barrier layer.

19. An electronic device, characterized in that: It comprises a power amplifier device and an antenna, wherein the power amplifier device is used to amplify the radio frequency signal and output it to the antenna for outward radiation, and the power amplifier device comprises the power amplifier device according to any one of claims 15 to 18.

Images