A power supply current detection circuit

Abstract

The present invention discloses a power supply current detection circuit, comprising: a first drive unit and a second drive unit, wherein when the first drive unit is turned on and the second drive unit is turned off, the current flowing through the first drive unit is a first current; when the first drive unit is turned off and the second drive unit is turned on, the current flowing through the second drive unit is a second current; a first detection unit, connected to the first drive unit, converting the first current into a first voltage form; a second detection unit, connected to the second drive unit, converting the second current into a second voltage form; an inductor, wherein one end, the second end of the first drive unit, and the first end of the second drive unit are connected, and the other end of the inductor is a power supply voltage output end; a sampling unit, configured to sample and store the first voltage when the first drive unit is turned off; and to sample and store the second voltage when the second drive unit is turned on; a buffer unit, configured to buffer the first voltage and the second voltage and output them. The power supply current detection circuit of the present invention simplifies the processing process after the sampling circuit by sampling the current peak value, thereby making the current signal more accurate.

Description

Technical Field

[0001] The present invention mainly relates to the field of power supply detection, and in particular to a power supply current detection circuit. Background Art

[0002] With the advancement of technology, electronic products are becoming increasingly common. Existing electronic products generally utilize fixed-voltage power supplies. Different electronic products require different fixed voltages for operation, so a fixed voltage output is often required. In power management systems, input or output current detection is often required to establish a constant current control system. In conventional power management systems, the current flowing through a current sampling resistor, connected between the input or output port of the power management system and the power supply or load port in the port current detection circuit, is detected by measuring the voltage across the resistor. The detected current is then fed back to the main circuit to establish a stable current output. Existing current detection circuits detect the current value by measuring the output voltage of the sampling resistor. The output voltage of the sampling resistor is then compared with two reference voltages, resulting in two indication signals, one indicating whether the current has reached the set value normally or the other indicating whether the current has exceeded the set value abnormally. Therefore, traditional methods continuously sample the current and then process the sampled current to obtain the peak current. This results in complex subsequent processing circuits and can be contaminated with noise signals. Summary of the Invention

[0003] The present invention provides a power supply current detection circuit, comprising: a first drive unit and a second drive unit, wherein when the first drive unit is turned on and the second drive unit is turned off, the current flowing through the first drive unit is a first current; when the first drive unit is turned off and the second drive unit is turned on, the current flowing through the second drive unit is a second current; a first detection unit, connected to the first drive unit, and converting the first current into a first voltage form; a second detection unit, connected to the second drive unit, and converting the second current into a second voltage form; an inductor, wherein one end, the second end of the first drive unit, and the first end of the second drive unit are connected, and the other end of the inductor is a power supply voltage output end; a sampling unit, configured to sample and store a first voltage when the first drive unit is turned off; and to sample and store a second voltage when the second drive unit is turned on; and a buffer unit, configured to buffer the first voltage and the second voltage and output them.

[0004] The power supply current detection circuit of the present invention samples the current peak value, thereby simplifying the processing process after the sampling circuit, and making the current signal more accurate.

[0005] In a preferred solution of the present invention, since the sampling time can be controlled so that two current sampling paths share one buffer unit, the circuit is further simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which like reference numerals generally represent like components.

[0007] Figure 1 A structural diagram of an embodiment of the present invention is shown;

[0008] Figure 2 shows a schematic diagram of a circuit structure according to an embodiment of the present invention;

[0009] Figure 3 Shown Figure 2 The working timing diagram of the embodiment shown;

[0010] Figure 4 FIG. 2 shows a schematic diagram of a circuit structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] The present invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention may be implemented in various forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present invention more thorough and complete and to fully convey the scope of the present invention to those skilled in the art.

[0012] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0013] Example 1

[0014] like Figure 1As shown, a power supply current detection circuit includes a first drive unit 10 and a second drive unit 20. When the first drive unit 10 is turned on and the second drive unit 20 is turned off, the current flowing through the first drive unit 10 is a first current; when the first drive unit 10 is turned off and the second drive unit 20 is turned on, the current flowing through the second drive unit 20 is a second current; a first detection unit 30 is connected to the first drive unit 10 and converts the first current into a first voltage form; a second detection unit 40 is connected to the second drive unit and converts the second current into a second voltage form; an inductor 50, one end of which, the second end of the first drive unit 10, and the first end of the second drive unit 20 are connected, and the other end of the inductor 50 is a power supply voltage output end; a sampling unit 60 is used to sample and store the first voltage when the first drive unit 10 is turned off; and to sample and store the second voltage when the second drive unit 20 is turned on; a buffer unit 70 is used to buffer the first voltage and the second voltage and output them.

[0015] In this embodiment, the first driving unit 10 and the second driving unit 20 are connected in series between the high level and the low level, and the connection point is the output end, which outputs the power supply voltage to the outside through the inductor 50.

[0016] The sampling unit 60 includes a first sampling unit 610 and a second sampling unit 620. The first sampling unit 610 is connected to the first driving unit 10 and the first detection unit 30, and the second sampling unit 620 is connected to the second driving unit 20 and the second detection unit 40. The first driving unit 10 and the first sampling unit 610 are controlled by a first PWM signal. When the first driving unit 10 is turned on, the first sampling unit 610 and the first driving unit 10 are turned on to store the first current in the first sampling unit 610, and the first sampling unit 610 is disconnected from its output terminal. When the first driving unit 10 is turned off, the first sampling unit 610 and the first driving unit 10 are disconnected. The output end is turned on and the sampled current is output to the outside; the second driving unit 20 and the second sampling unit 620 are controlled by the second PWM signal. When the second driving unit 20 is turned on, the second sampling unit 620 and the second driving unit 20 are turned on, the second current is stored in the second sampling unit 620, and the second sampling unit 620 is disconnected from its output end; when the second driving unit 20 is turned off, the second sampling unit 620 and the second driving unit 20 are disconnected, the second sampling unit 620 and the output end are turned on, and the sampled current is output to the outside; the pulse widths of the first PWM signal and the second PWM signal do not overlap, ensuring that the first driving unit 10 and the second driving unit 20 are not turned on at the same time.

[0017] In this embodiment, specifically Figure 2 The circuit shown is used as an example for explanation.

[0018] The power supply current detection circuit of this embodiment includes: a first driving unit 10, a first detection unit 30, a second driving unit 20, a second detection unit 40, an inductor 50, a sampling unit 60, and a buffer unit 70. In this embodiment, the first driving unit 10 is a first transistor 110, the first detection unit 30 is a first resistor 130, the second driving unit 20 is a second transistor 120, and the second detection unit 40 is a second resistor 140. One end of the first resistor 130 is connected to a high voltage VDD, and the other end is connected to the first transistor 110. The gate of the first transistor 110 receives a first PWM signal. The other end of the first transistor 110 is connected to the second transistor 120 and the inductor 50. The gate of the second transistor 120 receives a second PWM signal. The other end of the second transistor 120 is connected to the second resistor 140, and the other end of the second resistor 140 is connected to a low voltage.

[0019] The first PWM signal and the second PWM signal ensure that when one of the first transistor 110 and the second transistor 120 is turned off, the other is turned on. One end of the inductor 50, one end of the first transistor 110 and one end of the second transistor 120 are connected. Since the current flowing through the first driving unit 10 is as follows Figure 3 As shown, the maximum peak value occurs at the moment the first transistor 110 is turned off. Therefore, the sampling unit 60 samples the peak value of the current flowing through the first transistor 110 at the moment the first transistor 110 is turned off. In this embodiment, the first detection unit 30 is used to convert the first current into a voltage form, i.e., a first voltage, and stores the first voltage through the sampling unit 60. Similarly, the sampling unit 60 samples the current value flowing through the second transistor 120 at the moment the second transistor 120 is turned off. In this embodiment, the second detection unit 40 is used to convert the second current into a voltage form, i.e., a second voltage, and stores the second voltage through the sampling unit 60. The buffer unit 70 is used to buffer the first voltage and the second voltage and output them.

[0020] In this embodiment, the first transistor 110 is a PMOS transistor, and the second transistor 120 is an NMOS transistor. Therefore, when the first PWM signal is at a low level, the first transistor 110 is turned on, and when the second PWM signal is at a low level, the second transistor 120 is turned off. The detection unit converts the current flowing through the first transistor into a first voltage sampled by the voltage sampling unit. At the same time, in the inductor 20 branch, the current flows from the first transistor to the inductor 20.

[0021] In this embodiment, the sampling unit 60 includes a first sampling unit 610 and a second sampling unit 620. The first sampling unit 610 includes: a first switch 310, a first capacitor 320, and a second switch 330. The first end of the first switch 310, the first end of the first capacitor 320, and the first end of the second switch 330 are connected. The second end of the first capacitor 320 is connected to a low level. The second end of the second switch 330 is connected to the buffer unit 70. The control end of the first switch 310 is connected to the first PWM signal to control the first transistor 110 to be turned off at the moment of disconnection. Since Figure 3 As shown, the current flowing through the first transistor 110 at the moment of disconnection is a peak current. Therefore, the first detection unit 30 converts the peak value of the first current flowing through the first transistor 110 into a voltage form, i.e., a first voltage. The post-sampling unit 60 stores the first voltage on the first capacitor 320. When the first switch 310 is turned on and the second switch 330 is turned off, the first capacitor 320 discharges to the cache unit 70 through the second switch 330. In this embodiment, preferably, the control terminal of the first switch 310 is closed by a low-level input, and the control terminal of the second switch 330 is closed by a high-level input. For example, the first switch 310 can be a PMOS transistor switch, and the second switch 330 can be an NMOS transistor switch. The control terminal of the first switch 310 is connected to the first PWM signal, and the control terminal of the second switch 330 is connected to the first PWM signal.

[0022] The second sampling unit 620 further includes a third switch 340, a second capacitor 350, and a fourth switch 360. The first end of the third switch 340, the first end of the second capacitor 350, and the first end of the fourth switch 360 are connected to each other. The second end of the second capacitor 350 is connected to a low level. The second end of the third switch 340 is connected to the buffer unit 70. In this embodiment, preferably, the control end of the third switch 340 is input with a high level to close, and the control end of the fourth switch 350 is input with a low level to close. For example, in this embodiment, the third switch 340 is an NMOS transistor, and its control end is connected to the second PWM signal. The fourth switch 360 is a PMOS transistor, and its control end is connected to the second PWM signal. When the third switch 340 is turned on and the fourth switch 360 is turned off, the inductor charges the second capacitor 350, and the second detection unit 40 converts the second current into a voltage, which is stored in the second capacitor 350. When the third switch 340 is turned off and the fourth switch 350 is turned on, the second capacitor outputs the voltage to the buffer unit. In another embodiment, the first PWM signal and the second PWM signal can be the same signal.

[0023] refer to Figure 2During operation, the first sampling unit 610 operates as follows: When the first PWM signal is low, the first transistor 110 (PMOS transistor) is turned on. When the second PWM signal is low, the second transistor 120 (NMOS transistor) is turned off. Therefore, current flows from the high-level VDD terminal to the inductor 50 and the first switch. The first switch is turned on as a PMOS transistor, and the second switch is turned off as an NMOS transistor. The first detection unit converts the first current into a voltage and charges the first capacitor. Therefore, the first capacitor stores the peak voltage of the first current, i.e., the first voltage. When the first PWM signal jumps from a low level to a high level, the first transistor is turned off, the first switch 310 is turned off, and the second switch is turned on. The first capacitor discharges and outputs the voltage to the buffer unit.

[0024] refer to Figure 2 The working principle of the second sampling unit is as follows: when the first PWM signal is at a high level and the second PWM signal jumps from a low level to a high level, the first transistor is a PMOS transistor and is turned off, the second transistor is an NMOS transistor and is turned on, the inductor discharges in the reverse direction and flows to the second sampling unit through the second transistor and the second detection unit. The second detection unit converts the current flowing through the second transistor into a voltage and charges the second capacitor; when the second PWM signal jumps from a high level to a low level, the third switch is turned off and the fourth switch is turned on, and the second capacitor discharges and outputs to the cache unit.

[0025] In this embodiment, the buffer charging unit includes two buffer modules, a first buffer module and a second buffer module, which are respectively connected to the first sampling unit and the second sampling unit, and the output currents of the two buffer modules are summed and output.

[0026] In other embodiments, the first transistor and the second transistor may also be of other types, and the first switch, the second switch, the third switch and the fourth switch may also be of other types. For example, PMOS transistors and NMOS transistors may be arbitrarily selected, so that the clock signal used as the control may also be selected differently.

[0027] Example 2

[0028] like Figure 4 As shown, in another optional solution, the buffer unit includes a differential circuit, the first sampling unit and the second sampling unit are connected to the differential circuit, and the differential circuit sums the first current and the second current and outputs the sum. Because the sampling unit is used in the present invention to achieve time-sharing sampling of the first current and the second current, the peak summation of the first current and the second current can be achieved through timing control, replacing the existing two-way buffer module solution, thereby simplifying the circuit structure and saving chip area.

[0029] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A power supply current detection circuit, characterized in that: The device comprises a first drive unit and a second drive unit, wherein when the first drive unit is turned on and the second drive unit is turned off, the current flowing through the first drive unit is a first current; and when the first drive unit is turned off and the second drive unit is turned on, the current flowing through the second drive unit is a second current; A first detection unit, connected to the first driving unit, converts the first current into a first voltage form; a second detection unit connected to the second driving unit, and converting the second current into a second voltage form; an inductor, wherein one end, the second end of the first driving unit, and the first end of the second driving unit are connected, and the other end of the inductor is a power supply voltage output end; A sampling unit, configured to sample and store the first voltage when the first driving unit is turned off; When the second driving unit is turned on, sampling and storing the second voltage; a buffer unit, configured to buffer the first voltage and the second voltage and then output them; The first driving unit and the second driving unit are connected in series between the high level and the low level, and the connection point is the output end, which outputs the power supply voltage of the power supply to the outside through the inductor; The sampling unit includes a first sampling unit and a second sampling unit, the first sampling unit is connected to the first driving unit and the first detection unit, and the second sampling unit is connected to the second driving unit and the second detection unit; The first driving unit and the first sampling unit are controlled by a first PWM signal. When the first driving unit is turned on, the first sampling unit and the first driving unit are turned on to store the first current in the first sampling unit, and the first sampling unit is disconnected from its output terminal. When the first driving unit is turned off, the first sampling unit and the first driving unit are disconnected, and the first sampling unit and the output end are connected to output the sampled current to the outside; The second driving unit and the second sampling unit are controlled by a second PWM signal. When the second driving unit is turned on, the second sampling unit and the second driving unit are turned on to store the second current in the second sampling unit, and the second sampling unit is disconnected from its output terminal. When the second driving unit is turned off, the second sampling unit and the second driving unit are disconnected, and the second sampling unit and the output end are connected to output the sampled current to the outside; The pulse widths of the first PWM signal and the second PWM signal do not overlap, ensuring that the first drive unit and the second drive unit are not turned on at the same time; The high-level pulse width of the first PWM signal is greater than the high-level pulse width of the second PWM signal; The buffer unit includes a differential circuit, and the first sampling unit and the second sampling unit are commonly connected to an input end of the differential circuit.

2. The power supply current detection circuit according to claim 1, wherein: The first sampling unit includes a first switch, a first capacitor, and a second switch, wherein a first end of the first switch, a first end of the first capacitor, and a first end of the second switch are connected, a second end of the first capacitor is connected to a low level, and a second end of the second switch is connected to a buffer unit, and control ends of the first switch and the second switch are connected to a first PWM signal to control the first switch and the second switch to be alternately turned on and off; The second sampling unit includes a third switch, a second capacitor, and a fourth switch. The first end of the third switch, the first end of the second capacitor, and the first end of the fourth switch are connected. The second end of the second capacitor is connected to a low level. The second end of the third switch is connected to the buffer unit. The control ends of the third switch and the fourth switch are connected to the second PWM signal to control the third switch and the fourth switch to be alternately turned on and off.

3. The power supply current detection circuit according to claim 2, wherein: The first switch is a PMOS transistor, the second switch is an NMOS transistor, the third switch is an NMOS transistor, and the fourth switch is a PMOS transistor.

4. The power supply current detection circuit according to claim 2, wherein: The first drive unit is disconnected when the first PWM signal is at a high level, and is turned on when the first PWM signal is at a low level; the second drive unit is disconnected when the second PWM signal is at a low level, and is turned on when the second PWM signal is at a high level.

5. The power supply current detection circuit according to claim 4, wherein: The buffer unit includes two buffer modules, the first sampling unit is connected to the first buffer module, and the second sampling unit is connected to the second buffer module.

6. The power supply current detection circuit according to claim 3, wherein: The first driving unit includes a PMOS transistor, and the second driving unit includes an NMOS transistor.

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