Enhancement circuit and voltage regulator

Abstract

The application relates to an enhanced circuit and a voltage stabilizer. The enhanced circuit is applied to the voltage stabilizer, the voltage stabilizer comprises an error amplifier and a power tube, an input end of the enhanced circuit is connected with a power supply and a first output end of the error amplifier respectively, an output end of the enhanced circuit is connected with a gate of the power tube, and a second output end of the error amplifier is connected with the gate of the power tube; the enhanced circuit is used for increasing the ripple noise input to the gate of the power tube. The enhanced circuit provided by the application can improve the power supply rejection ratio of the voltage stabilizer, thereby improving the voltage stabilization performance of the voltage stabilizer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management, in particular to an enhancement circuit and a voltage regulator. BACKGROUND

[0002] The low-voltage linear voltage regulator is an important device in the power management module, which can adjust the output voltage of the power supply to stabilize the output voltage within the set value range, and provide stable voltage for various circuits and resistive devices. With the wide use of power supply, it is necessary to improve the power supply rejection ratio of the low-voltage linear voltage regulator to improve the voltage regulation performance of the low-voltage linear voltage regulator.

[0003] Therefore, there is an urgent need for a method that can effectively improve the power supply rejection ratio. SUMMARY

[0004] Therefore, it is necessary to provide an enhancement circuit and a voltage regulator that can improve the power supply rejection ratio to solve the above technical problems.

[0005] In a first aspect, the present application provides an enhancement circuit applied to a voltage regulator, the voltage regulator comprising an error amplifier and a power tube, the input end of the enhancement circuit being connected with a power supply and a first output end of the error amplifier respectively, the output end of the enhancement circuit being connected with a gate of the power tube, and a second output end of the error amplifier being connected with the gate of the power tube.

[0006] The enhancement circuit is used to increase the ripple noise input to the gate of the power tube.

[0007] In one of the embodiments, the enhancement circuit further comprises an amplification circuit and a current mirror biasing circuit.

[0008] The input end of the current mirror biasing circuit is connected with the power supply and the first output end of the error amplifier respectively.

[0009] The input end of the amplification circuit is connected with the output end of the current mirror biasing circuit, the power supply and the first output end of the error amplifier respectively, and the output end of the amplification circuit is connected with the gate of the power tube.

[0010] In one of the embodiments, the current mirror biasing circuit comprises a first field effect tube and a second field effect tube.

[0011] The gate of the first field effect tube is connected with the first output end of the error amplifier, the drain of the first field effect tube is connected with the drain of the second field effect tube, and the source of the first field effect tube is grounded.

[0012] The source of the second field effect tube is connected with the power supply, the gate of the second field effect tube is connected with the drain of the second field effect tube, and the gate of the second field effect tube is connected with the input end of the amplification circuit.

[0013] In one of the embodiments, the amplification circuit comprises at least one common-source amplification sub-circuit, input terminals of the common-source amplification sub-circuit are connected with the output terminal of the current mirror biasing circuit, the power supply and the first output terminal of the error amplifier respectively, and an output terminal of the common-source amplification sub-circuit is connected with the gate of the power tube.

[0014] In one of the embodiments, the common-source amplification sub-circuit comprises a third field effect tube and a fourth field effect tube.

[0015] The gate of the third field effect tube is connected with the output terminal of the current mirror biasing circuit, the source of the third field effect tube is connected with the power supply, and the drain of the third field effect tube is connected with the drain of the fourth field effect tube.

[0016] The gate of the fourth field effect tube is connected with the first output terminal of the error amplifier, the source of the fourth field effect tube is grounded, and the drain of the fourth field effect tube is connected with the gate of the power tube.

[0017] In one of the embodiments, the common-source amplification sub-circuit further comprises a switching circuit, the switching circuit is connected with the third field effect tube and the fourth field effect tube respectively.

[0018] The switching circuit is used for controlling the conduction state of the third field effect tube and the fourth field effect tube.

[0019] In one of the embodiments, the switching circuit comprises a first switch tube and a second switch tube.

[0020] The first switch tube is connected between the drain of the third field effect tube and the drain of the fourth field effect tube.

[0021] The second switch tube is connected between the source of the fourth field effect tube and the ground.

[0022] In one of the embodiments, the enhancement circuit further comprises a filter circuit, the filter circuit is connected between the current mirror biasing circuit and the amplification circuit.

[0023] The filter circuit is used for filtering out the ripple noise in the voltage transmitted from the current mirror biasing circuit to the amplification circuit.

[0024] In one of the embodiments, the filter circuit comprises a resistor and a capacitor.

[0025] A first terminal of the resistor is connected with the output terminal of the current mirror biasing circuit, and a second terminal of the resistor is connected with the input terminal of the amplification circuit.

[0026] A first terminal of the capacitor is connected with the second terminal of the resistor, and a second terminal of the capacitor is grounded.

[0027] In the second aspect, one of the embodiments further provides a voltage stabilizer, the voltage stabilizer comprises an error amplifier, a power tube and the enhancement circuit provided by the above-mentioned embodiments.

[0028] The application discloses an enhanced circuit and a voltage stabilizer. The enhanced circuit is applied to the voltage stabilizer, and the voltage stabilizer comprises an error amplifier and a power tube. An input end of the enhanced circuit is connected with a power supply and a first output end of the error amplifier respectively, an output end of the enhanced circuit is connected with a gate of the power tube, and a second output end of the error amplifier is connected with the gate of the power tube. The enhanced circuit is used for increasing the ripple noise input to the gate of the power tube. In the embodiment, compared with the prior art, in addition to one path in which the second output end of the error amplifier is directly connected with the gate of the power tube, there is another path in which the first output end of the error amplifier is connected with the gate of the power tube through the enhanced circuit. The ripple noise of the power supply is included in the two paths connected with the gate of the power tube, that is, the ripple noise transmitted to the gate of the power tube can be increased through the enhanced circuit, and the ripple noise transmitted to the gate of the power tube through the two paths can be superimposed to offset the ripple noise from the source to the drain in the power tube, so that the ripple noise in the voltage output from the drain of the power tube can be reduced, and the power supply rejection ratio of the voltage stabilizer can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0030] Figure 1 It is a structural schematic diagram of the voltage stabilizer in one embodiment;

[0031] Figure 2 It is a structural schematic diagram of the error amplifier in one embodiment;

[0032] Figure 3 It is a structural schematic diagram of the enhanced circuit in one embodiment;

[0033] Figure 4 It is a structural schematic diagram of the enhanced circuit in another embodiment;

[0034] Figure 5 It is a structural schematic diagram of the enhanced circuit in another embodiment;

[0035] Figure 6 It is a structural schematic diagram of the enhanced circuit in another embodiment;

[0036] Figure 7 It is a structural schematic diagram of the enhanced circuit in another embodiment.

[0037] Marked explanation:

[0038] 1, error amplifier; 2, power tube; 100, enhancement circuit; 110, amplification circuit; 101, common-source amplification sub-circuit; 111, third field effect tube; 112, fourth field effect tube; 113, switching circuit; 114, first switch tube; 115, second switch tube; 116, fifth field effect tube; 117, sixth field effect tube; 118, seventh field effect tube; 119, eighth field effect tube; 120, current mirror bias circuit; 121, first field effect tube; 122, second field effect tube; 130, filter circuit; 131, resistor; 132, capacitor. DETAILED DESCRIPTION

[0039] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0040] The serial numbers of components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and have no any sequence or technical meaning. In this application, "connection" and "coupling" include direct and indirect connection (coupling) unless otherwise specified. In the description of the present application, it should be understood that the orientation or position relationship indicated by the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0041] In this application, unless otherwise expressly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0042] Before the technical solutions of the embodiments of the present application are specifically introduced, the technical background or the technical evolution context based on which the embodiments of the present application are introduced. In the field of power management, low-voltage linear voltage regulator is an important device in the power management module. The low-voltage linear voltage regulator can adjust the output voltage of the power supply, so that the output voltage is stabilized within the set value range, and provides stable voltage for various circuits and resistance devices. With the wide use of power supply, it is necessary to improve the power supply rejection ratio of the low-voltage linear voltage regulator to improve the voltage stabilizing performance of the low-voltage linear voltage regulator. Therefore, a method for effectively improving the power supply rejection ratio of the low-voltage linear voltage regulator is needed. In this regard, the present application provides an enhancement circuit.

[0043] The technical solutions related to the embodiments of the present application will be introduced in combination with the scene to which the embodiments of the present application are applied.

[0044] The enhancement circuit provided by the embodiments of the present application is applied to a voltage regulator. Please refer to Figure 1 , the voltage regulator includes an error amplifier 1 and a power tube 2. The output of the error amplifier 1 is connected with the gate of the power tube 2, the first input end of the error amplifier 1 is connected with a basic voltage source (VREF), and the second input end of the error amplifier 1 is connected with the drain of the power tube 2. That is, the drain of the power tube 2 is taken as the second input end of the error amplifier 1, that is, the voltage output by the drain of the power tube 2 is output to the error amplifier 1 through the second input end of the error amplifier 1. The source of the power tube 2 is connected with a power supply (VDD), and the drain of the power tube 2 passes through two resistors for voltage division. The specific structure of the error amplifier 1 is shown in Figure 2 , which is a cross-coupled amplifier and can improve the gain.

[0045] Please refer to Figure 3 , one embodiment of the present application provides an enhancement circuit 100, the input ends of the enhancement circuit 100 are respectively connected with a power supply and the first output end of the error amplifier 1, the output end of the enhancement circuit 100 is connected with the gate of the power tube 2, and the second output end of the error amplifier 1 is connected with the gate of the power tube 2. The enhancement circuit 100 is used to increase the ripple noise input to the gate of the power tube 2.

[0046] The enhancement circuit 100 includes a first input end and a second input end. The error amplifier 1 includes a first output end VEA1 and a second output end VEA2. The first input end of the enhancement circuit 100 is connected with the first output end VEA1 of the error amplifier 1, and the second input end of the enhancement circuit 100 is connected with a power supply. The second output end VEA2 of the error amplifier 1 is connected with the gate of the power tube 2.

[0047] The specific structure of the error amplifier 1 is shown in the above embodiment, and will not be described here again. The enhancement circuit 100 is used to increase the ripple noise input to the gate of the power tube 2. The core element of the enhancement circuit 100 is a transistor, and the type and specific structure of the enhancement circuit 100 are not limited in the embodiment, as long as the function thereof can be realized.

[0048] The working principle of the enhancement circuit 100 provided in the embodiment is as follows:

[0049] The error amplifier 1 has two output terminals, one of which is directly connected to the gate of the power tube 2, and the other of which is connected to the gate of the power tube 2 through the enhancement circuit 100. The voltage output from the second output terminal VEA2 of the error amplifier 1 to the power tube 2 includes the ripple noise of the power supply; the voltage output from the first output terminal VEA1 of the error amplifier 1 through the enhancement circuit 100 also includes the ripple noise of the power supply. That is to say, the ripple noise is included in both paths input to the gate of the power tube 2, and the ripple noise in the two paths is superimposed and output to the gate of the power tube 2. The source of the power tube 2 is connected to the power supply, and the ripple noise of the power supply will be transmitted from the source to the drain of the power tube 2. The ripple noise input to the gate of the power tube 2 will be offset by the ripple noise from the source to the drain.

[0050] The enhancement circuit 100 provided in the embodiment is applied to a voltage stabilizer, and the voltage stabilizer includes the error amplifier 1 and the power tube 2. The input terminals of the enhancement circuit 100 are respectively connected to the power supply and the first output terminal of the error amplifier 1, the output terminal of the enhancement circuit 100 is connected to the power tube 2, and the second output terminal of the error amplifier 1 is connected to the power tube 2; the enhancement circuit 100 is used to increase the ripple noise input to the gate of the power tube 2. In the embodiment, compared with the prior art, in addition to the one path that the second output terminal VEA2 of the error amplifier 1 is directly connected to the gate of the power tube 2, there is another path that the first output terminal VEA1 of the error amplifier 1 is connected to the gate of the power tube 2 through the enhancement circuit 100. The ripple noise of the power supply is included in both paths connected to the gate of the power tube 2, that is, the ripple noise transmitted to the gate of the power tube 2 can be increased through the enhancement circuit 100, and the ripple noise in the two paths is superimposed and transmitted to the gate of the power tube 2, so as to offset the ripple noise from the source to the drain in the power tube 2, thereby reducing the ripple noise in the voltage output from the drain of the power tube 2, and further improving the power supply rejection ratio of the voltage stabilizer.

[0051] In addition, the error amplifier 1 in the embodiment adopts the structure of two output terminals, so as to improve the output swing, and thereby improve the amplification capability of the error amplifier 1.

[0052] Please refer to Figure 4In one embodiment, the enhancement circuit 100 further comprises an amplification circuit 110 and a current mirror biasing circuit 120. The input terminals of the current mirror biasing circuit 120 are connected to a power supply and the first output terminal of the error amplifier 1 respectively; the input terminals of the amplification circuit 110 are connected to the output terminals of the current mirror biasing circuit 120, the power supply and the first output terminal of the error amplifier 1 respectively, and the output terminal of the amplification circuit 110 is connected to the gate of the power tube 2.

[0053] The current mirror biasing circuit 120 comprises a first input terminal, a second input terminal and an output terminal. The first input terminal of the current mirror biasing circuit 120 is connected to the first output terminal VEA1 of the error amplifier 1, i.e. the first input terminal of the current mirror biasing circuit 120 is connected to the first output terminal VEA1 of the error amplifier 1 as the first input terminal of the enhancement circuit 100. The second input terminal of the current mirror biasing circuit 120 is connected to a power supply, and the output terminal of the current mirror biasing circuit 120 is connected to the input terminal of the amplification circuit 110. In other words, the biasing source of the current mirror of the current mirror biasing circuit 120 is provided by the output of the first output terminal VEA1 of the error amplifier 1.

[0054] The amplification circuit 110 comprises a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal of the amplification circuit 110 is connected to the output terminal of the current mirror biasing circuit 120, the second input terminal of the amplification circuit 110 is connected to the first output terminal of the error amplifier 1, the third input terminal of the amplification circuit 110 is connected to a power supply, and the output terminal of the amplification circuit 110 is connected to the gate of the power tube 2, i.e. the output terminal of the amplification circuit 110 is connected to the gate of the power tube 2 as the output terminal of the enhancement circuit 100.

[0055] In the embodiment, the specific structure of the enhancement circuit 100 is described, which comprises the amplification circuit 110 and the current mirror biasing circuit 120. The structure of the enhancement circuit 100 is simple and easy to implement. Moreover, the second input terminal of the current mirror biasing circuit 120 is connected to a power supply, and the input terminal of the amplification circuit 110 is also connected to the power supply. The current mirror biasing circuit 120 is used to ensure that the current inputted to the current mirror biasing circuit 120 by the power supply is the same as the current inputted to the amplification circuit 110 by the power supply, so as to ensure the normal operation of the amplification circuit 110.

[0056] Please continue to see Figure 4 In one embodiment, the current mirror biasing circuit 120 comprises a first field effect tube 121 and a second field effect tube 122.

[0057] The gate of the first field effect transistor 121 is connected with the first output terminal VEA1 of the error amplifier 1, the drain of the first field effect transistor 121 is connected with the drain of the second field effect transistor 122, and the source of the first field effect transistor 121 is grounded. The source of the second field effect transistor 122 is connected with the power supply, the gate of the second field effect transistor 122 is connected with the drain of the second field effect transistor 122, and the gate of the second field effect transistor 122 is connected with the input terminal of the amplifying circuit 110.

[0058] The gate of the first field effect transistor 121 is connected with the first output terminal VEA1 of the error amplifier 1 as the first input terminal of the current mirror bias circuit 120. The first field effect transistor 121 and the second field effect transistor 122 are common-drain. The source of the second field effect transistor 122 is connected with the power supply as the second input terminal of the current mirror bias circuit 120, and the gate of the second field effect transistor 122 is connected with the input terminal of the amplifying circuit 110 as the output terminal of the current mirror bias circuit 120.

[0059] In an optional embodiment, as shown in Figure 4 the first field effect transistor 121 is an N-channel field effect transistor, and the second field effect transistor 122 is a P-channel field effect transistor.

[0060] In the embodiment, the current mirror bias circuit 120 composed of the first field effect transistor 121 and the second field effect transistor 122 has a simple structure, and the field effect transistors are easy to obtain and have a low cost.

[0061] In an embodiment, as shown in Figure 5 the amplifying circuit 110 includes at least one common-source amplifying sub-circuit 101. The input terminals of the common-source amplifying sub-circuit 101 are respectively connected with the output terminal of the current mirror bias circuit 120, the power supply and the first output terminal VEA1 of the error amplifier 1, and the output terminal of the common-source amplifying sub-circuit 101 is connected with the gate of the power transistor 2.

[0062] The amplifying circuit 110 can include one common-source amplifying sub-circuit 101 or multiple common-source amplifying sub-circuits 101. The embodiment does not limit the number of the common-source amplifying sub-circuits 101 included in the amplifying circuit 110, and the user can select according to the actual application scenario.

[0063] The common-source amplifier sub-circuit 101 includes a first input terminal, a second input terminal, and a third input terminal. When the amplifier circuit 110 includes multiple common-source amplifier sub-circuits 101, the multiple common-source amplifier sub-circuits 101 are connected in parallel. That is, the first input terminal of each common-source amplifier sub-circuit 101 is connected to the output terminal of the current mirror bias circuit 120 as the first input terminal of the amplifier circuit 110, the second input terminal of each common-source amplifier sub-circuit 101 is connected to the first output terminal VEA1 of the error amplifier 1, the third input terminal of each common-source amplifier sub-circuit 101 is connected to the current as the third input terminal of the amplifier circuit 110, and the output terminal of each common-source amplifier sub-circuit 101 is connected to the gate of the power transistor 2 as the output terminal of the amplifier circuit 110.

[0064] In this embodiment, the amplifier circuit 110 includes one or more common source amplifier sub-circuits 101. The user can determine the number of common source amplifier sub-circuits 101 according to the voltage of the power supply in the actual application scenario, which can improve the practicality of the enhancement circuit 100.

[0065] In one embodiment, such as Figure 5 As shown, the common-source amplifier sub-circuit 101 includes a third field-effect transistor 111 and a fourth field-effect transistor 112.

[0066] The gate of the third field-effect transistor 111 is connected to the output terminal of the current mirror bias circuit 120, the source of the third field-effect transistor 111 is connected to the power supply, and the drain of the third field-effect transistor 111 is connected to the drain of the fourth field-effect transistor 112. The gate of the fourth field-effect transistor 112 is connected to the first output terminal VEA1 of the error amplifier 1, the source of the fourth field-effect transistor 112 is grounded, and the drain of the fourth field-effect transistor 112 is connected to the power transistor 2.

[0067] For each common-source amplifier sub-circuit 101, the common-source amplifier sub-circuit 101 includes a third field-effect transistor 111 and a fourth field-effect transistor 112. The gate of the third field-effect transistor 111 is connected to the output terminal of the current mirror bias circuit 120 as the first input terminal of the common-source amplifier sub-circuit 101, and the source of the third field-effect transistor 111 is connected to the power supply as the third input terminal of the common-source amplifier sub-circuit 101.

[0068] The gate of the fourth field-effect transistor 112 is connected to the first output terminal VEA1 of the error amplifier 1, serving as the second input terminal of the common-source amplifier sub-circuit 101. The source of the fourth field-effect transistor 112 is grounded. The third field-effect transistor 111 and the fourth field-effect transistor 112 share a common drain, that is, the drain of the third field-effect transistor 111 is connected to the drain of the fourth field-effect transistor 112. The drain of the fourth field-effect transistor 112 and the drain of the third field-effect transistor 111 also jointly serve as the output terminal of the common-source amplifier sub-circuit 101, connected to the gate of the power transistor 2.

[0069] In the embodiment, the common-source amplification sub-circuit 101 comprises the third field effect tube 111 and the fourth field effect tube 112, so that the common-source amplification sub-circuit 101 has a simple structure and the field effect tubes are easy to obtain and have a low cost.

[0070] In a specific embodiment, as shown in the figure, the third field effect tube 111 is a P-channel field effect tube and the fourth field effect tube 112 is an N-channel field effect tube. Figure 5

[0071] Please refer to Figure 6 In an embodiment, the common-source amplification sub-circuit 101 further comprises a switch circuit 113 connected with the third field effect tube 111 and the fourth field effect tube 112. The switch circuit 113 is used to control the conduction state of the third field effect tube 111 and the fourth field effect tube 112.

[0072] The switch circuit 113 is connected with the third field effect tube 111 and the fourth field effect tube 112, and controls the conduction state of the third field effect tube 111 and the fourth field effect tube 112 to control whether the common-source amplification sub-circuit 101 to which the third field effect tube 111 and the fourth field effect tube 112 belong or the common-source amplification sub-circuit 101 to which the switch circuit 113 belongs is connected to the enhancement circuit 100. The specific structure of the switch circuit 113 is not limited in the embodiment, as long as it can realize its function.

[0073] In the embodiment, the switch circuit 113 is arranged in the common-source amplification sub-circuit 101, so that whether the common-source amplification sub-circuit 101 is connected to the enhancement circuit 100 can be controlled. When a plurality of common-source amplification sub-circuits 101 are included in the amplification circuit 110, the user can control any one or more of the plurality of common-source amplification sub-circuits 101 to be connected to the enhancement circuit 100 according to the range of the power supply voltage in the actual application scenario, so that the practicability of the enhancement circuit 100 can be improved.

[0074] In an optional embodiment, under different power supply voltage domains, the range of the power supply voltage is detected, a control code is output by the corresponding switch circuit 113 to control the conduction state of the common-source amplification sub-circuit 101 to which the switch circuit 113 belongs, so that the conduction of the corresponding common-source amplification sub-circuit 101 under different voltage ranges can be realized, and then the ripple noise transmitted to the gate of the power tube 2 is better matched with the ripple noise from the source to the drain of the power tube 2 to be offset, so that the ripple noise output by the power tube 2 is suppressed to a greater extent, and the improvement of the power supply rejection ratio under different voltage domains is realized.

[0075] Please continue to refer to Figure 6 ​In one embodiment, the switch circuit 113 comprises a first switch tube 114 and a second switch tube 115. The first switch tube 114 is connected between the drain of the third field effect tube 111 and the drain of the fourth field effect tube 112; the second switch tube 115 is connected between the source of the fourth field effect tube 112 and the ground.

[0076] The first switch tube 114 is connected between the drain of the third field effect tube 111 and the drain of the fourth field effect tube 112, for controlling the on-off state of the third field effect tube 111. The second switch tube 115 is connected between the source of the fourth field effect tube 112 and the ground, for controlling the on-off state of the fourth field effect tube 112. The first switch tube 114 and the second switch tube 115 can have the same structure or different structures. The present embodiment does not limit the specific structure of the first switch tube 114 and the second switch tube 115, as long as the functions thereof can be realized.

[0077] In the present embodiment, the on-off states of the third field effect tube 111 and the fourth field effect tube 112 are controlled by setting the switch tubes for the third field effect tube 111 and the fourth field effect tube 112 respectively, which is simple in structure and easy to realize.

[0078] In an alternative embodiment, the first switch tube 114 comprises a fifth field effect tube 116 and a sixth field effect tube 117, and the fifth field effect tube 116 and the sixth field effect tube 117 have different structures. If the fifth field effect tube 116 is an N-channel field effect tube, then the sixth field effect tube 117 is a P-channel field effect tube; if the fifth field effect tube 116 is a P-channel field effect tube, then the sixth field effect tube 117 is an N-channel field effect tube. The source of the P-channel field effect tube is connected with the drain of the third field effect tube 111, and the drain of the P-channel field effect tube is connected with the drain of the fourth field effect tube 112. The drain of the N-channel field effect tube is connected with the drain of the third field effect tube 111, and the source of the N-channel field effect tube is connected with the drain of the fourth field effect tube 112. The gate of the P-channel field effect tube and the gate of the N-channel field effect tube are both control terminals, for receiving control codes.

[0079] The first switch tube 114 and the second switch tube 115 can have the same structure. The second switch tube 115 includes a seventh field effect tube 118 and an eighth field effect tube 119. If the seventh field effect tube 118 is an N-channel field effect tube, the eighth field effect tube 119 is a P-channel field effect tube; if the seventh field effect tube 118 is a P-channel field effect tube, the eighth field effect tube 119 is an N-channel field effect tube. The source of the P-channel field effect tube is connected with the drain of the fourth field effect tube 112, and the drain of the N-channel field effect tube is connected with the drain of the fourth field effect tube 112. The drain of the P-channel field effect tube and the source of the N-channel field effect tube are both grounded. The gates of the P-channel field effect tube and the N-channel field effect tube are both control ends, which are used to receive control codes.

[0080] Please refer to Figure 7 In an embodiment, the enhancement circuit 100 further includes a filter circuit 130. The filter circuit 130 is connected between the current mirror bias circuit 120 and the amplification circuit 110. The filter circuit 130 is used to filter out the ripple noise in the voltage transmitted from the current mirror bias circuit 120 to the amplification circuit 110.

[0081] The filter circuit 130 includes a first end and a second end. The first end of the filter circuit 130 is connected with the output end (the gate of the second field effect tube 122) of the current mirror bias circuit 120, and the second end of the filter circuit 130 is connected with the first input end of the amplification circuit 110. The filter circuit 130 can be an active filter circuit or a passive filter circuit. The embodiment does not limit the structure of the filter circuit 130 as long as it can achieve its function.

[0082] The filter circuit 130 is connected between the current mirror bias circuit 120 and the amplification circuit 110, and can filter out the ripple noise in the voltage transmitted from the current mirror bias circuit 120 to the amplification circuit 110.

[0083] In the embodiment, by setting the filter circuit 130 between the current mirror bias circuit 120 and the amplification circuit 110, the ripple noise in the voltage transmitted from the current mirror bias circuit 120 to the amplification circuit 110 can be filtered out, so that the voltage received by the amplification circuit 110 is more accurate.

[0084] Please continue to refer to Figure 7 In an embodiment, the filter circuit 130 includes a resistor 131 and a capacitor 132. The first end of the resistor 131 is connected with the output end of the current mirror bias circuit 120, and the second end of the resistor 131 is connected with the input end of the amplification circuit 110; the first end of the capacitor 132 is connected with the second end of the resistor 131, and the second end of the capacitor 132 is grounded.

[0085] The resistor 131 comprises a first end and a second end, and the capacitor 132 also comprises a first end and a second end. The first end of the resistor 131 is connected to the output end of the current mirror bias circuit 120 as the first end of the filter circuit 130, and the second end of the resistor 131 is connected to the first end of the capacitor 132 and the first input end of the amplification circuit 110 respectively.

[0086] In the embodiment, the filter circuit 130 composed of the resistor 131 and the capacitor 132 has a simple structure, and the resistor 131 and the capacitor 132 are common electronic components, which are easy to obtain and have low cost.

[0087] One embodiment of the present application provides a voltage stabilizer, which comprises an error amplifier 1, a power tube 2 and the enhanced circuit provided in the above embodiment.

[0088] The voltage stabilizer provided in the embodiment comprises the enhanced circuit provided in the above embodiment, and has all the beneficial effects of the enhanced circuit, which will not be described herein.

[0089] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described herein, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0090] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, however, it should not be understood as the limitation of the patent scope of the present application. It should be pointed out that, for the ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An enhancement circuit, characterized by, The application is applied to a voltage stabilizer, the voltage stabilizer comprises an error amplifier (1) and a power tube (2), the input end of an enhancement circuit (100) is connected with a power supply and the first output end of the error amplifier (1) respectively, the output end of the enhancement circuit (100) is connected with the gate of the power tube (2), the second output end of the error amplifier (1) is connected with the gate of the power tube (2); the first input end of the error amplifier (1) is connected with a basic voltage source, the second input end of the error amplifier (1) is connected with the drain of the power tube (2), and the source of the power tube (2) is connected with the power supply; The enhancement circuit (100) is used for increasing the ripple noise input to the gate of the power tube (2); The enhancement circuit (100) comprises an amplification circuit (110) and a current mirror bias circuit (120); The input end of the current mirror bias circuit (120) is connected with the power supply and the first output end of the error amplifier (1) respectively; The input end of the amplification circuit (110) is connected with the output end of the current mirror bias circuit (120), the power supply and the first output end of the error amplifier (1) respectively, and the output end of the amplification circuit (110) is connected with the gate of the power tube (2); The current mirror bias circuit (120) comprises a first field effect tube (121) and a second field effect tube (122); the gate of the first field effect tube (121) is connected with the first output end of the error amplifier (1), the drain of the first field effect tube (121) is connected with the drain of the second field effect tube (122), and the source of the first field effect tube (121) is grounded; the source of the second field effect tube (122) is connected with the power supply, the gate of the second field effect tube (122) is connected with the drain of the second field effect tube (122), and the gate of the second field effect tube (122) is connected with the input end of the amplification circuit (110); The amplification circuit (110) comprises at least one common-source amplification sub-circuit (101), the input end of the common-source amplification sub-circuit (101) is connected with the output end of the current mirror bias circuit (120), the power supply and the first output end of the error amplifier (1) respectively, and the output end of the common-source amplification sub-circuit (101) is connected with the gate of the power tube (2).

2. The enhanced circuit of claim 1, wherein, The first field effect tube (121) is an N-channel field effect tube, and the second field effect tube (122) is a P-channel field effect tube.

3. The enhanced circuit of claim 1, wherein, The common-source amplification sub-circuit (101) comprises a third field effect tube (111) and a fourth field effect tube (112); The gate of the third field effect tube (111) is connected with the output end of the current mirror bias circuit (120), the source of the third field effect tube (111) is connected with the power supply, and the drain of the third field effect tube (111) is connected with the drain of the fourth field effect tube (112); The gate of the fourth field-effect transistor (112) is connected to the first output terminal of the error amplifier (1), the source of the fourth field-effect transistor (112) is grounded, and the drain of the fourth field-effect transistor (112) is connected to the gate of the power transistor (2).

4. The enhanced circuit of claim 3, wherein, The common-source amplifier sub-circuit (101) further includes a switching circuit (113), which is connected to the third field-effect transistor (111) and the fourth field-effect transistor (112) respectively; The switching circuit (113) is used to control the conduction state of the third field-effect transistor (111) and the fourth field-effect transistor (112).

5. The enhanced circuit of claim 4, wherein, Under different power supply voltage domains, by detecting the range of the power supply voltage, the corresponding switching circuit (113) outputs a control code to control the conduction state of the common source amplifier sub-circuit (101) to which the switching circuit (113) belongs.

6. The enhanced circuit of claim 4, wherein, The switching circuit (113) includes a first switching transistor (114) and a second switching transistor (115); The first switching transistor (114) is connected between the drain of the third field-effect transistor (111) and the drain of the fourth field-effect transistor (112); The second switch (115) is connected between the source of the fourth field-effect transistor (112) and ground.

7. The enhanced circuit of claim 6, wherein, The first switching transistor (114) includes a fifth field-effect transistor (116) and a sixth field-effect transistor (117). If the fifth field-effect transistor (116) is an N-channel field-effect transistor, then the sixth field-effect transistor (117) is a P-channel field-effect transistor; the source of the sixth field-effect transistor (117) is connected to the drain of the third field-effect transistor (111), the drain of the sixth field-effect transistor (117) is connected to the drain of the fourth field-effect transistor (112), the drain of the fifth field-effect transistor (116) is connected to the drain of the third field-effect transistor (111), and the source of the fifth field-effect transistor (116) is connected to the drain of the fourth field-effect transistor (112); the gate of the fifth field-effect transistor (116) and the gate of the sixth field-effect transistor (117) are control terminals used to receive control codes.

8. The boost circuit according to any one of claims 2 to 7, wherein The enhancement circuit (100) further includes a filter circuit (130) connected between the current mirror bias circuit (120) and the amplification circuit (110); The filter circuit (130) is used to filter out ripple noise in the voltage transmitted from the current mirror bias circuit (120) to the amplifier circuit (110).

9. The enhanced circuit of claim 8, wherein, The filter circuit (130) includes a resistor (131) and a capacitor (132). The first end of the resistor (131) is connected to the output end of the current mirror bias circuit (120), and the second end of the resistor (131) is connected to the input end of the amplifier circuit (110). The first end of the capacitor (132) is connected to the second end of the resistor (131), and the second end of the capacitor (132) is grounded.

10. A voltage regulator characterized by comprising: The voltage regulator includes an error amplifier (1), a power transistor (2), and an enhancement circuit (100) as described in any one of claims 1-9.

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