Electronic device

Abstract

The present disclosure provides an electronic device, including a substrate, a driving element, a conductive layer, and an electronic element. The driving element is disposed on the substrate. The conductive layer is disposed on the substrate, wherein a first distance (B) is between the driving element and an edge of the conductive layer. The electronic element is disposed on the conductive layer and electrically connected to the driving element, wherein a second distance (A) is between the electronic element and the edge of the conductive layer, and the first distance (B) is greater than the second distance (A).

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] To enable electronic components in electronic devices to achieve various functions such as rapid heat dissipation or reduced electromagnetic interference, a large-area conductive layer is typically formed within the device. However, the presence of this conductive layer increases the capacitive load of electronic components and / or the impedance of signal lines, or creates topographical differences among components, potentially leading to signal line breaks or stripping. Therefore, improving the reliability of electronic devices by reducing the likelihood of these problems has become a key area of ​​technological development in recent years. Summary of the Invention

[0003] This disclosure provides an electronic device to address the problems encountered by existing electronic devices, thereby improving the reliability of the electronic device.

[0004] According to embodiments disclosed herein, an electronic device includes a substrate, a driving element, a conductive layer, and electronic components. The driving element is disposed on the substrate. The conductive layer is disposed on the substrate, wherein a first distance (B) exists between the driving element and the edge of the conductive layer. The electronic components are disposed on the conductive layer and electrically connected to the driving element, wherein a second distance (A) exists between the electronic components and the edge of the conductive layer, and the first distance (B) is greater than the second distance (A).

[0005] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the present disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0007] Figure 1 This is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2A Based on Figure 1 An enlarged schematic diagram of an embodiment of region R1;

[0009] Figure 2B Based on Figure 1 An enlarged schematic diagram of another embodiment of region R1;

[0010] Figure 2C Based on Figure 1 An enlarged schematic diagram of another embodiment of region R1;

[0011] Figure 3A Based on Figure 1 An enlarged schematic diagram of one embodiment;

[0012] Figure 3B Based on Figure 3A A partial cross-sectional schematic diagram of an embodiment with section lines A1-A1';

[0013] Figure 3C Based on Figure 3A A partial cross-sectional schematic diagram of an embodiment with section line B1-B1';

[0014] Figure 3D Based on Figure 3A A partial cross-sectional schematic diagram of an embodiment with section line C1-C1';

[0015] Figure 4A Based on Figure 1 An enlarged schematic diagram of another embodiment;

[0016] Figure 4B Based on Figure 4A A partial cross-sectional schematic diagram of an embodiment with section line C2-C2';

[0017] Figure 5A This is a partial top view schematic diagram of the arrangement relationship between conductive layers in an electronic device according to an embodiment of the present disclosure;

[0018] Figure 5B Based on Figure 5A A partial cross-sectional schematic diagram of an embodiment with section line D1-D1';

[0019] Figure 5C Based on Figure 5A A partial cross-sectional schematic diagram of an embodiment of section line D2-D2';

[0020] Figure 6 This is a partial top view schematic diagram showing the arrangement relationship between conductive layers of an electronic device according to another embodiment of the present disclosure;

[0021] Figure 7A This is a partial top view schematic diagram illustrating the arrangement relationship between conductive layers of an electronic device according to yet another embodiment of this disclosure;

[0022] Figure 7B Based on Figure 7A A partial cross-sectional schematic diagram of an embodiment with section lines E1-E1';

[0023] Figure 7C Based on Figure 7A A partial cross-sectional schematic diagram of an embodiment of the section line E2-E2'. Detailed Implementation

[0024] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0025] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0026] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0027] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there may be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0028] The terms “approximately,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0029] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0030] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0031] The electrical connections described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of two circuit components are directly connected or connected to each other by a conductor segment.

[0032] In this disclosure, the thickness, length, and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image using an electron microscope, but these methods are not limited to these. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0033] The electronic devices disclosed herein may include display devices, antenna devices, sensing devices, splicing devices, touch devices, or combinations thereof. For example, the electronic devices disclosed herein may include active components, passive components, or combinations thereof, which may include diodes, transistors, capacitors, inductors, resistors, or combinations thereof, but this disclosure is not limited thereto. The electronic devices include, but are not limited to, rollable, bendable, or flexible electronic devices. The electronic devices may include, for example, liquid crystals, light-emitting diodes (LEDs), variable capacitors, quantum dots (QDs), fluorescence, phosphorescence, other suitable materials, or combinations thereof. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), micro-LEDs, mini-LEDs, or quantum dot light-emitting diodes (QLEDs, QDLEDs), but are not limited thereto. The display devices may be self-emissive display devices. The antenna device can be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device can be a sensing device that senses capacitance, light, heat energy, or ultrasound, but is not limited thereto. The sensing device may include fingerprint sensing devices, visible light sensing devices, infrared light sensing devices, X-ray sensing devices, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any arrangement and combination of the foregoing, but is not limited thereto. Furthermore, the shape of the electronic device can be rectangular, circular, polygonal, with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a processing system, a driving system, a control system, a light source system, and a shelving system to support the display device or splicing device. It should be noted that the electronic device can be any arrangement and combination of the foregoing, but is not limited thereto. The following description uses display devices or splicing devices as examples of electronic devices to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0034] The following examples illustrate exemplary embodiments of this disclosure, and the same element symbols are used in the drawings and description to denote the same or similar parts.

[0035] Figure 1 This is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 2A Based on Figure 1 An enlarged schematic diagram of an embodiment of region R1, Figure 2B Based on Figure 1 An enlarged schematic diagram of another embodiment of region R1, Figure 2C Based on Figure 1 An enlarged schematic diagram of another embodiment of region R1, and Figure 3ABased on Figure 1 An enlarged schematic diagram of one embodiment. It is worth noting that, for clarity and ease of explanation, the drawings are provided. Figure 1 and Figure 3A Several components are omitted.

[0036] Please refer to the following at the same time Figure 1 , Figure 2A , Figure 2B and Figure 2C The electronic device 10 of this embodiment includes an active region AA and a peripheral region PA. In some embodiments, the peripheral region PA is located on at least one side of the active region AA. In this embodiment, the peripheral region PA surrounds the active region AA, but this disclosure is not limited thereto. The electronic device 10 of this application may be, for example, a display device, an antenna device, a sensing device, or a splicing device. In this embodiment, the electronic device 10 includes a substrate 100, a driving element 200, a conductive layer M1, and electronic components 300.

[0037] The substrate 100 may be made of, for example, glass, plastic, or a combination thereof. For example, the substrate 100 may be made of quartz, sapphire, polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or combinations thereof, and this disclosure is not limited thereto.

[0038] The driving element 200 is disposed, for example, on the substrate 100, and, for example, in the peripheral region PA of the electronic device 10. In some embodiments, the driving element 200 is disposed on the surface of the substrate 100 in a chip-on-glass (COG) manner, but this disclosure is not limited thereto. That is, in other embodiments, the driving element 200 may be disposed on the surface of the substrate 100 in a chip-on-plastic (COP) manner. Alternatively, in still other embodiments, the driving element 200 includes a driving circuit and is directly disposed on the surface of the substrate 100 (gate-on-panel (GOP)). It is worth noting that... Figure 1Although only one driving element 200 is shown, this disclosure is not limited thereto. In other embodiments, the electronic device 10 may include two or more driving elements 200 disposed on the surface of the substrate 100. The driving element 200 may include, for example, a driving chip, a circuit board, or a combination thereof. In some embodiments, the driving chip may include driving units such as a timing control unit, a data driving unit, and a power driving unit, and the circuit board may include a flexible printed circuit board (FPC), but this disclosure is not limited thereto.

[0039] A conductive layer M1 is disposed, for example, on a substrate 100, and, for example, in an active region AA of an electronic device 10. In some embodiments, the conductive layer M1 extends into a peripheral region PA in addition to being disposed in the active region AA, serving as a heat dissipation layer, an electrostatic discharge protection layer, an electromagnetic interference shielding layer, etc., for the electronic device 10, but this disclosure is not limited to these uses. The material of the conductive layer M1 may include, for example, low-impedance materials such as silver, copper, gold, aluminum, tin, nickel, or combinations thereof. However, the material of the conductive layer M1 may also be, for example, other suitable materials or combinations of the above materials, and this disclosure is not limited thereto. In this embodiment, the conductive layer M1 has an edge M1E adjacent to the driving element 200. The edge M1E of the conductive layer M1 extends substantially along a first direction d1, for example, but this disclosure is not limited thereto. In addition, the conductive layer M1 may have a quadrilateral shape, for example, but this disclosure is not limited thereto. That is, in other embodiments, the conductive layer M1 may not be rectangular. In this disclosure, "A adjacent to B" means that there is no A or B between A and B, but other elements may be disposed there.

[0040] Electronic components 300 are disposed, for example, on the conductive layer M1. In some embodiments, the electronic components 300 are spaced apart on the conductive layer M1. For example, such as Figure 1 As shown, multiple electronic components 300 are arranged in an array on the conductive layer M1, but this disclosure is not limited thereto. In other embodiments, the multiple electronic components 300 may be arranged in an alternating manner (e.g., in a pentile manner) or other ways on the conductive layer M1. The electronic components 300 may include, for example, electronic components such as variable capacitors, light-emitting diodes, or solar cells, and this disclosure is not limited thereto.

[0041] In this embodiment, an electronic component 300 adjacent to the edge M1E of the conductive layer M1 is electrically connected to a driving element 200 via a first wire CL1, so as to be driven by the driving element 200. A first distance B exists between the driving element 200 adjacent to the edge M1E of the conductive layer M1 and the edge M1E of the conductive layer M1, and a second distance A exists between the electronic component 300 and the edge M1E of the conductive layer M1. Specifically, the first distance B exists between the driving element 200 and the edge M1E of the conductive layer M1 in the extending direction of the first wire CL1 (e.g., the second direction d2), and the second distance A exists between the electronic component 300 and the edge M1E of the conductive layer M1 in the extending direction of the first wire CL1 (e.g., the second direction d2), wherein the second direction d2 is different from the first direction d1, for example, orthogonal. In some embodiments, the first distance B is greater than the second distance A. Alternatively, the first distance B and the second distance A satisfy the following relationship: B > A. When the first distance B and the second distance A satisfy the above relationship, the overlapping area of ​​the conductive layer M1 and the first wire CL1 can be reduced, thereby reducing the capacitive load of the electronic device 10 and improving the signal transmission quality of the electronic device 10. In other embodiments, the first distance B and the second distance A can satisfy the following relationship: B / (A+B)≥50%. It is worth noting that when the first distance B and the second distance A satisfy the above relationship, the above effect can be achieved at any position on the electronic device 10.

[0042] Please refer to the following at the same time Figure 1 and Figure 3AIn this embodiment, the electronic device 10 further includes an electrical element 400. In some embodiments, the electrical element 400 at least partially overlaps with the electronic element 300 in a third direction d3 (the normal direction of the substrate 100, orthogonal to the second direction d2 and the first direction d1), but this disclosure is not limited thereto. The electrical element 400 may, for example, include a thin-film transistor (TFT) and a storage capacitor Cst electrically connected to each other, but this disclosure is not limited thereto. In some embodiments, the thin-film transistor (TFT) is electrically connected to the electronic element 300 to serve as a switching element for driving the electronic element 300. The thin-film transistor (TFT) may, for example, include a plurality of electrodes and a semiconductor layer SE. For example, in this embodiment, the electrodes include a gate G, a source S, and a drain D, but this disclosure is not limited thereto. In some embodiments, the material of the semiconductor layer SE includes low-temperature polysilicon (LTPS), low-temperature polysilicon oxide (LTPO), or amorphous silicon (a-Si), but this disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include, but is not limited to, amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (e.g., gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy), or combinations thereof. The material of the semiconductor layer SE may also include, but is not limited to, metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or organic semiconductors containing polycyclic aromatic compounds, or combinations thereof. The gate G overlaps at least partially with the semiconductor layer SE on a third-direction d3 of the substrate 100. The source S and drain D are, for example, separated from each other and cover at least a portion of the semiconductor layer SE and are electrically connected to the semiconductor layer SE, wherein the drain D may be electrically connected, for example, to the storage capacitor Cst. Alternatively, the source S and drain D can be electrically connected to each other through vias in the insulating layer between them and the semiconductor layer SE. The thin-film transistor (TFT) is, for example, any bottom-gate type thin-film transistor known to those skilled in the art. However, while this embodiment uses a bottom-gate type thin-film transistor as an example, this disclosure is not limited thereto.

[0043] In this embodiment, the electronic device 10 further includes a test pad 500. The test pad 500 is disposed, for example, in the peripheral region PA of the electronic device 10, and on a different side from the driving element 200 in the active region AA, but this disclosure is not limited thereto. In some embodiments, the test pad 500 may overlap with the conductive layer M1, but this disclosure is not limited thereto. In other embodiments, the test pad 500 may not overlap with the conductive layer M1. In some embodiments, multiple test pads 500 are provided, and the multiple test pads 500 are arranged along the second direction d2, but this disclosure is not limited thereto. In this embodiment, the test pad 500 and the electronic component 300 are electrically connected to each other via a test connection line TL. Therefore, the test pad 500 can be used to test whether multiple electronic components 300 are damaged during the process of forming the electronic device 10. If a damaged electronic component 300 is detected, the damaged electronic component 300 can be repaired or replaced with a new electronic component during the process of forming the electronic device 10. The aforementioned test method may be, for example, by setting up a test device (not shown) electrically connected to the test pad 500 to apply a bias voltage to the electronic component 300, and by observing the electrical characteristics of the electronic component 300 to determine whether the electronic component 300 is damaged; or by using a thermal imager to detect the thermal characteristics of the electronic component 300 to determine whether the electronic component 300 is damaged, but it should be noted that this disclosure is not limited thereto.

[0044] In this embodiment, the electronic device 10 further includes a first conductive line CL1. The first conductive line CL1 is electrically connected, for example, to the driving element 200 and the electronic element 300, for transmitting signals from the driving element 200 to a corresponding electrical element 400 (e.g., a thin-film transistor TFT) to drive the electronic element 300, but this disclosure is not limited thereto. In other embodiments, the driving element 200 may also transmit signals directly to the electronic element 300 via other conductive lines. Based on this, the first conductive line CL1 extends, for example, from the driving element 200 disposed in the peripheral region PA to the electrical element 400 disposed in the active region PA, such that the first conductive line CL1 includes both the portion outside the conductive layer M1 that does not overlap with the conductive layer M1 and the portion that overlaps with the conductive layer M1 (bounded by the edge M1E of the conductive layer M1). To reduce the problem of the first conductor CL1 breaking or peeling at the edge M1E of the conductive layer M1 due to terrain differences when it extends to the edge M1E of the conductive layer M1, this embodiment includes a relatively large width portion of the first conductor CL1 at the edge M1E of the conductive layer M1. Specifically, as... Figure 2AAs shown, the first conductor CL1 has a first width w1 in the first direction d1 outside the conductive layer M1 (i.e., the first conductor CL1 that does not overlap with the conductive layer M1), and the first conductor CL1 has a second width w2 in the first direction d1 on the edge M1E of the conductive layer M1, wherein the first width w1 is smaller than the second width w2. In some embodiments, the first width w1 and the second width w2 satisfy the following relationship: w2 ≥ w1 * 1.1. Based on this, by making the first width w1 smaller than the second width w2, this embodiment can reduce the chance of the above-mentioned problems occurring and improve the reliability of the electronic device 10. In this embodiment, the electronic device 10 also includes a first conductor CL1'. The first conductor CL1' extends from the driving element 200 to the conductive layer M1, so that the driving element 200 is electrically connected to the conductive layer M1, but this disclosure is not limited thereto.

[0045] From another perspective, the first conductor CL1 includes a portion CL1_P1 having a first width w1 and a portion CL1_P2 having a second width w2, wherein the portion CL1_P2 of the first conductor CL1 extends from outside the conductive layer M1 to the conductive layer M1. In some embodiments, the edge of the portion CL1_P2 of the first conductor CL1 is arc-shaped, which can reduce the chance of static electricity accumulating at this edge, thereby providing electrostatic protection. The portion CL1_P2 of the first conductor CL1, for example, partially overlaps the edge M1E of the conductive layer M1, wherein the portion CL1_P2 not overlapping with the conductive layer M1 has a length h1 extending in the second direction d2, and the portion CL1_P2 overlapping with the conductive layer 300 has a length h2 extending in the second direction d2, and the lengths h1 and h2 are, for example, from 1 micrometer to 50 micrometers, but this disclosure is not limited thereto. The lengths h1 and h2 may be, for example, the same or different; for example, the length h1 may be greater than the length h2, but this disclosure is not limited thereto. In some embodiments, the first conductor CL1 further includes a portion CL1_P3 extending from the portion CL1_P2 to the electronic component 300. The width of the portion CL1_P3 of the first conductor CL1 may be substantially the same as the width of the portion CL1_P1; or substantially the same as the width of the portion CL1_P2; or greater than the width of the portion CL1_P2, and this disclosure is not limited thereto.

[0046] In other embodiments, such as Figure 2BAs shown, a portion CL1_P2 of the first conductor CL1 has multiple openings CL1_OP arranged relative to each other along a first direction d1, such that a portion CL1_P2 of the first conductor CL1 has multiple branches CL1_P2B. The branches CL1_P2B of the first conductor CL1 also extend from outside the conductive layer M1 to the conductive layer M1. Through this design, when some branches CL1_P2B of the portion CL1_P2 of the first conductor CL1 experience problems such as wire breakage, the electronic device 10 can still transmit signals through the unbroken branches CL1_P2B of the first conductor CL1, thereby improving the reliability of the electronic device 10.

[0047] In some other embodiments, such as Figure 2C As shown, the edge M1E of the conductive layer M1 includes a non-linear portion M1Z, and the first conductor CL1 is located on the non-linear portion M1Z. In some embodiments, the non-linear portion M1Z of the first conductor CL1 may include a serrated shape (e.g., Figure 2C As shown, the shape can be wavy, arc-shaped, or a combination thereof, but this disclosure is not limited thereto. This design increases the overlap length between the first conductor CL1 and the edge M1E of the conductive layer M1, thereby reducing the possibility of the first conductor CL1 breaking or peeling at the edge M1E of the conductive layer M1, and thus improving the reliability of the electronic device 10.

[0048] In this embodiment, as Figures 3A to 3D As shown, the electronic device 10 also includes an insulating layer IL1, an insulating layer IL2, a conductive layer M2, an insulating layer IL3, a conductive layer M3, an insulating layer IL4, a conductive layer M4, and an insulating layer IL5, wherein... Figures 3A to 3D The illustrated embodiment corresponds to the area where a thin-film transistor (TFT) is provided.

[0049] An insulating layer IL1 is disposed on the substrate 100, for example. In this embodiment, the insulating layer IL1 is disposed between the substrate 100 and the conductive layer M1. The material of the insulating layer IL1 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but this disclosure is not limited thereto.

[0050] An insulating layer IL2 is disposed, for example, on an insulating layer IL1. In this embodiment, the insulating layer IL2 covers the conductive layer M1. The material of the insulating layer IL2 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), but this disclosure is not limited thereto. The material of the insulating layer IL2 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but this disclosure is not limited thereto.

[0051] The conductive layer M2 is disposed, for example, on the insulating layer IL2. In this embodiment, the conductive layer M2 has the aforementioned gate G and gate line GL, wherein the gate G may be electrically connected to the corresponding gate line GL to receive the corresponding gate signal, but this disclosure is not limited thereto. The conductive layer M2 may be made of the same or different material as the aforementioned conductive layer M1, and this disclosure is not limited thereto.

[0052] An insulating layer IL3 is disposed, for example, on an insulating layer IL2. In this embodiment, the insulating layer IL3 partially covers the conductive layer M2. That is, the insulating layer IL3 has a via TH1 that exposes a portion of the conductive layer M2, but this disclosure is not limited thereto. From another perspective, the insulating layer IL3 is disposed between the gate G and the semiconductor layer SE to serve as a gate insulating layer. The material of the insulating layer IL3 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), but this disclosure is not limited thereto. The material of the insulating layer IL3 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but this disclosure is not limited thereto.

[0053] Conductive layer M3 is disposed on insulating layer IL3, for example, and partially covers semiconductor layer SE, which is also disposed on insulating layer IL3. In this embodiment, conductive layer M3 is formed with the aforementioned source S, drain D, and data line DL, wherein source S can be electrically connected to the corresponding data line DL to receive the corresponding data signal, but this disclosure is not limited thereto. Conductive layer M3 may, for example, be made of the same or different material as the aforementioned conductive layer M1, and this disclosure is not limited thereto.

[0054] An insulating layer IL4 is disposed, for example, on an insulating layer IL3. In this embodiment, the insulating layer IL4 partially covers the conductive layer M3. That is, the insulating layer IL4 has a via TH22 that exposes a portion of the conductive layer M3, but this disclosure is not limited thereto. In addition, the insulating layer IL4 also includes a via TH21 that exposes a portion of the conductive layer M2. Specifically, in this embodiment, via TH21 overlaps with via TH1, such that the insulating layer IL4 and the insulating layer IL3 together expose a portion of the conductive layer M2. In some embodiments, the insulating layer IL4 exposes the gate line GL of the conductive layer M2 and the data line DL of the conductive layer M3. The material of the insulating layer IL4 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), but this disclosure is not limited thereto. The material of the insulating layer IL4 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but this disclosure is not limited thereto.

[0055] Conductive layer M4 is disposed, for example, on insulating layer IL4. In this embodiment, conductive layer M4 has conductors M4_CL1 and M4_CL2, wherein conductor M4_CL1 is electrically connected to the corresponding gate line GL, and conductor M4_CL2 is electrically connected to the corresponding data line DL. Specifically, conductor M4_CL1 is electrically connected to the gate line GL in conductive layer M2 through interconnected vias TH21 and TH1, and M4_CL2 is electrically connected to the data line DL in conductive layer M3 through via TH22, such that conductors M4_CL1 and M4_CL2 each serve as adapters for gate line GL and data line DL. Based on this, since conductive layer M4 is disposed further away from conductive layer M1 than conductive layer M2 (or conductive layer M3), by electrically connecting the gate line GL and data line DL used for signal transmission to conductive layer M4, the distance between them and conductive layer M1 can be increased, thereby reducing the impedance values ​​of gate line GL and data line DL. In detail, in the normal direction (third direction d3) of the substrate 100, the distance d41 between conductive layer M4 and conductive layer M1 is, for example, greater than the distance d31 between conductive layer M3 and conductive layer M1, and the distance d41 between conductive layer M4 and conductive layer M1 is also, for example, greater than the distance d21 between conductive layer M2 and conductive layer M1. From another perspective, in the normal direction (third direction d3) of the substrate 100, the distance d41 between wire M4_CL2 and conductive layer M1 is, for example, greater than the distance d31 between source electrode S and conductive layer M1, and the distance d41 between wire M4_CL1 and conductive layer M1 is also, for example, greater than the distance d21 between conductive layer M2 (e.g., gate G or gate line GL) and conductive layer M1.

[0056] Figure 4A Based on Figure 1 An enlarged schematic diagram of another embodiment, and Figure 4B Based on Figure 4A A partial cross-sectional view of one embodiment along section line C2-C2'. It should be noted that... Figure 4A and Figure 4B Each of the embodiments can be used independently. Figure 3A and Figure 3D The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0057] Please refer to the following at the same time Figure 4A and Figure 4B The main difference between this embodiment and the previous one is that it further includes a conductive layer M5, which replaces the conductive wire M4_CL1 formed by the conductive layer M4 and is electrically connected to the corresponding gate line GL.

[0058] In detail, the conductive layer M5 is also disposed on the insulating layer IL4, for example, through a different process than that used to form the conductive layer M4, but this disclosure is not limited thereto. In this embodiment, the conductor M5 is formed with a conductor M5_CL, which is electrically connected to the gate line GL in the conductive layer M2 through interconnected vias TH21 and TH1. Therefore, since the conductive layer M5 is disposed further away from the conductive layer M1 than the conductive layer M2, by electrically connecting the gate line GL, which is used to transmit signals, to the conductive layer M5, the distance between it and the conductive layer M1 can be increased, thereby reducing the impedance value of the gate line GL. In detail, in the normal direction (third direction d3) of the substrate 100, the distance d51 between the conductive layer M5 and the conductive layer M1 is, for example, greater than the distance d21 between the conductive layer M2 and the conductive layer M1. From another perspective, in the normal direction (third direction d3) of the substrate 100, the distance d51 between the conductor M5_CL and the conductive layer M1 is, for example, greater than the distance d21 between the conductive layer M2 (e.g., the gate G or the gate line GL) and the conductive layer M1.

[0059] It is worth noting that although conductive layer M5 and conductive layer M4 are located on the same horizontal plane in this embodiment, this disclosure is not limited to this. In some other embodiments, the electronic device 10 may also include an insulating layer (not shown) covering conductive layer M4, and conductive layer M5 is disposed on this insulating layer, such that conductive layer M5 and conductive layer M4 belong to different layers. From another perspective, wire M5_CL and wire M4_CL1 belong to different layers. This insulating layer also includes a portion of conductive layer M2 exposed by a via (not shown) connected to via TH21 and via TH1, and wire M5_CL in conductive layer M5 is electrically connected to gate line GL in conductive layer M2 through this via. Since conductive layer M5 and conductive layer M4 are at different heights in this case, the adverse effects caused by signal coupling between gate line GL and data line DL can be reduced, thereby improving the signal transmission quality of electronic device 10.

[0060] Figure 5A This is a partial top view schematic diagram showing the arrangement relationship between the conductive layers of an electronic device according to an embodiment of this disclosure. Figure 5B Based on Figure 5A A partial cross-sectional schematic diagram of an embodiment with section lines D1-D1', and Figure 5C Based on Figure 5A A partial cross-sectional view of one embodiment along section line D2-D2'. It should be noted that, for clarity and ease of explanation, the drawings are provided. Figures 5A to 5C Several components are omitted from the diagram. It should be noted that... Figures 5A to 5C The embodiments can be used Figures 3A to 3D The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0061] In some embodiments, conductive layer M1 of electronic device 10 has a conductor M1_CL formed thereon, conductive layer M2 has a conductor M2_CL formed thereon, and insulating layer IL2 has a via TH3, wherein the via TH3 exposes a portion of the conductor M1_CL. Conductor M1_CL is disposed, for example, on substrate 100, and conductor M2_CL overlaps with conductor M1_CL, wherein conductor M2_CL extends, for example, in the same direction as conductor M1_CL. For example, conductor M2_CL and conductor M1_CL may extend in a second direction d2, but this disclosure is not limited thereto. In this embodiment, conductor M2_CL is electrically connected to conductor M1_CL through the via TH3 of insulating layer IL2. By stacking conductor M2_CL and conductor M1_CL in parallel, the impedance value of conductor M2_CL can be reduced, thereby improving the signal transmission quality of electronic device 10. Furthermore, in this embodiment, the area of ​​conductor M2_CL in the third direction d3 is larger than the area of ​​conductor M1_CL in the third direction d3, but this disclosure is not limited thereto. For example, the width wL2 of conductor M2_CL in the first direction d1 may be greater than the width wL1 of conductor M1_CL in the first direction d1, such that the area of ​​conductor M2_CL in the third direction d3 is greater than the area of ​​conductor M1_CL in the third direction d3, but this disclosure is not limited thereto.

[0062] Figure 6 This is a partial top view schematic diagram showing the arrangement relationship between the conductive layers of an electronic device according to another embodiment of this disclosure. It should be noted that... Figure 6 The embodiments can be used Figure 5A The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0063] Please refer to Figure 6 This embodiment and Figure 5A The main difference in the illustrated embodiment is that the insulating layer IL2 has an opening OP extending along the extension direction of the conductor, wherein the opening OP exposes a portion of the conductor M1_CL, and the conductor opening OP extends, for example, in the same direction as the conductors M2_CL and M1_CL. For example, the opening OP may extend in a second direction d2 along with the conductors M2_CL and M1_CL, but this disclosure is not limited thereto. In some embodiments, the width wOP of the opening OP in the first direction d1 may be smaller than the width wL1 of the conductor M1_CL in the first direction d1. In this embodiment, the conductor M2_CL can also be electrically connected to the conductor M1_CL through the opening OP of the insulating layer IL2.

[0064] Figure 7A This is a partial top view schematic diagram showing the arrangement relationship between the conductive layers of an electronic device according to another embodiment of this disclosure. Figure 7BBased on Figure 7A A partial cross-sectional schematic diagram of an embodiment with section lines E1-E1'. Figure 7C Based on Figure 7A A partial cross-sectional view of an embodiment along section line E2-E2'. It should be noted that... Figures 7A to 7C The embodiments can be used Figures 5A to 5C The component references and partial contents of the embodiments are as follows, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted.

[0065] Please refer to the following at the same time Figures 7A to 7C This embodiment and Figures 5A to 5C The main difference in the illustrated embodiment is that the area of ​​conductor M2_CL in the third direction d3 is smaller than the area of ​​conductor M1_CL in the third direction d3. For example, the width wL2 of conductor M2_CL in the first direction d1 may be smaller than the width wL1 of conductor M1_CL in the first direction d1, such that the area of ​​conductor M2_CL in the third direction d3 is smaller than the area of ​​conductor M1_CL in the third direction d3, but this disclosure is not limited thereto. In this embodiment, conductor M2_CL can also be electrically connected to conductor M1_CL through the through-hole TH3 of insulating layer IL2.

[0066] Based on the above, in some embodiments of the electronic device disclosed herein, the driving element has a first distance from the edge of the conductive layer, and the electronic element has a second distance from the edge of the conductive layer. By making the first distance smaller than the second distance, the area of ​​overlap between the conductive layer and the first conductor can be reduced, thereby reducing the capacitive load of the electronic device. Furthermore, in some embodiments of the electronic device disclosed herein, the first conductor has a first width outside the conductive layer and a second width at the edge of the conductive layer. By making the first width smaller than the second width, the problem of breakage or stripping of the first conductor at the edge of the conductive layer due to terrain differences can be reduced. In addition, some embodiments of the electronic device disclosed herein include an adapter cable for signal lines, and this adapter cable is separated from the signal lines by at least one insulating layer. Therefore, the distance between the adapter cable and the conductive layer can be increased, thereby reducing the impedance value of the signal lines. Moreover, some embodiments of the electronic device disclosed herein reduce the impedance value of the signal lines by stacking and connecting the signal lines in parallel with the conductors in the conductive layer. In summary, the electronic device disclosed herein has improved reliability.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein. Features between the embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

Claims

1. An electronic device, characterized in that, include: substrate; A driving element is disposed on the substrate; A conductive layer is disposed on the substrate, wherein the driving element has a first distance (B) between it and the edge of the conductive layer. An electronic component is disposed on the conductive layer and electrically connected to the driving element, wherein the electronic component has a second distance (A) between it and the edge of the conductive layer. as well as A first conductive wire electrically connects the driving element and the electronic element. The first conductive wire has a first width outside the conductive layer and a second width at the edge of the conductive layer, wherein the first width is smaller than the second width. Wherein, the first distance (B) is greater than the second distance (A).

2. The electronic device according to claim 1, characterized in that, It includes a plurality of said electronic components, which are spaced apart on the conductive layer.

3. The electronic device according to claim 1, characterized in that, The first distance (B) and the second distance (A) satisfy the following relationship: B / (A+B)≥50%.

4. The electronic device according to claim 1, characterized in that, The first conductor has a branch portion that extends from outside the conductive layer to onto the conductive layer.

5. The electronic device according to claim 1, characterized in that, The edge of the conductive layer includes a non-linear portion, and the first wire is located on the non-linear portion.

6. The electronic device according to claim 1, characterized in that, It also includes a thin-film transistor and a second conductive wire. The thin-film transistor is disposed on the substrate and includes a first electrode. The second conductive wire is electrically connected to the first electrode through a first via. In the normal direction of the substrate, the distance between the second conductive wire and the conductive layer is greater than the distance between the first electrode and the conductive layer.

7. The electronic device according to claim 6, characterized in that, It also includes a third conductive line, wherein the thin-film transistor includes a second electrode, the third conductive line is electrically connected to the second electrode through a second via, and in the normal direction of the substrate, the distance between the third conductive line and the conductive layer is greater than the distance between the second electrode and the conductive layer.

8. The electronic device according to claim 7, characterized in that, The second conductor and the third conductor belong to different layers.

9. The electronic device according to claim 1, characterized in that, Also includes: A fourth conductive line is disposed on the substrate; as well as The fifth conductor overlaps with the fourth conductor and is electrically connected to the fourth conductor through a through-hole. The fifth conductor extends in the same direction as the fourth conductor.

Images