Monolithic integrated circuit of nitride surface acoustic wave device and field effect transistor and manufacturing method thereof

Abstract

The present invention discloses a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, which mainly solves the problem of difficult epitaxial integration of the nitride surface acoustic wave device and the field effect transistor. It includes a substrate, a nucleation layer, a channel layer, an insertion layer, a barrier layer, and a piezoelectric ferroelectric layer from bottom to top. The barrier layer is made of scandium indium aluminum gallium nitride material, and the piezoelectric ferroelectric layer is a continuous epitaxial single crystal scandium aluminum nitride material. Etching grooves are formed in the channel layer to the piezoelectric ferroelectric layer to form a partition area, and a passivation layer is filled; the piezoelectric ferroelectric layer on one side of the partition area and the interdigital electrodes thereon form a surface acoustic wave device; an ohmic contact area and source and drain electrodes are provided on the other side, and together with the channel layer to the piezoelectric ferroelectric layer, the passivation layer, and the gate electrode, a field effect transistor is formed. The present invention prepares a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor on an epitaxial single crystal material, improves the circuit performance and the matching performance of the frequency band and bandwidth, and can be used in the signal processing system of the communication radio frequency front end.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a monolithic integrated circuit that can be used in a front-end signal processing system in the field of radio frequency communications. Background Art

[0002] In the microwave radio frequency field, surface acoustic wave devices are commonly integrated with analog and radio frequency electronic devices due to their small size, low insertion loss, and fast filtering response. They play an important role in radio frequency front-end signal processing circuits and are widely used in communications, the Internet of Things, sensors, and autonomous driving. Due to the high electromechanical coupling coefficient, low dielectric loss, and compatibility with CMOS processes of AlN materials, the piezoelectric materials of surface acoustic wave filters are currently mainly prepared by physical vapor transport deposition methods such as magnetron sputtering to prepare polycrystalline AlN materials. Gallium nitride-based high electron mobility transistors (GaN HEMTs) are widely used as one of the solid-state electronic devices for microwave power amplifiers due to their excellent power and frequency characteristics, and they play an important role in the fields of 5G communications and information perception. Improving the performance of GaN HEMT devices can be achieved by changing the barrier layer structure, evolving from conventional AlGaN barriers to (Sc)AlN barriers.

[0003] To improve the analog signal processing capabilities of RF front-end circuits, monolithic epitaxial integration of polycrystalline nitride filter devices with single-crystal nitride RF devices is a key approach to reducing circuit size and improving circuit performance. In recent years, with the increasing maturity of GaN technology, efforts have been made to integrate polycrystalline AlN surface acoustic wave devices with single-crystal GaN HEMT RF devices to achieve higher-performance monolithic integrated filter-microwave amplifiers to meet the requirements of future communication systems.

[0004] The structure of surface acoustic wave devices made of existing polycrystalline AlN materials is as follows: Figure 1 As shown in FIG, it includes a substrate and a polycrystalline AlN piezoelectric layer from bottom to top, and an interdigital electrode is provided on the polycrystalline AlN piezoelectric layer as a transducer. The existing single crystal material GaN HEMT device structure is as follows: Figure 2 As shown, it includes a substrate, a nucleation layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top. A gate electrode is provided on the AlGaN barrier layer, and source and drain electrodes are provided on the source-drain ohmic contacts.

[0005] The GaN HEMT device is mainly grown by metal organic chemical vapor deposition or molecular beam epitaxy, and the AlN piezoelectric layer of the surface acoustic wave device is mainly grown by magnetron sputtering. The inconsistency of the growth method leads to a large difference in their crystal quality, making it difficult to achieve continuous growth and epitaxial monolithic integration of polycrystalline AlN surface acoustic wave devices and single crystal GaN HEMT RF devices. Therefore, the current method of integrating these two devices is as followsFigure 3 The discrete packaging technology shown, that is, after the nitride surface acoustic wave device and the high electron mobility transistor are fabricated, they are respectively soldered on the printed circuit board, and the two devices are interconnected through external leads to form an integrated circuit. This integrated circuit has the following disadvantages:

[0006] 1. Since its circuit integration is carried out by means of external lead interconnection, it will increase the process complexity and introduce parasitic parameters, resulting in a serious decline in work efficiency and severely restricting the performance and miniaturization of the RF front-end system.

[0007] 2. Since the filter prepared with polycrystalline AlN material has low electromechanical coupling coefficient, piezoelectric coefficient, sound velocity, power handling ability and its quality factor, there will be problems of mismatched working frequency band and bandwidth when it is directly interconnected with the GaN microwave RF device through external leads, making the monolithic integrated circuit unable to work effectively;

[0008] 3. Due to the inconsistent crystal quality caused by the different growth modes of polycrystalline AlN material and single-crystal GaN material, there are large differences in the reliability between the AlN surface acoustic wave device and the GaN microwave RF device, resulting in large deviations in local areas of the integrated circuit, and its stability and consistency are significantly reduced, restricting the frequency band range of application of this integrated circuit.

[0009] 4. Since the gate control ability of the HEMT device in this integrated circuit is weak, the subthreshold swing is large, and a negative voltage needs to be applied to the gate to deplete the two-dimensional electron gas in the channel under the gate to turn off the device, which will undoubtedly increase the complexity of the integrated circuit design and restrict its application in RF circuits. Summary of the Invention

[0010] The object of the present invention is to propose a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor and a manufacturing method in view of the disadvantages of the above-mentioned existing technologies, so as to improve the work efficiency and stability of the integrated circuit of the nitride surface acoustic wave device and the field effect transistor, achieve the matching of the frequency band and bandwidth of the circuit, and simplify the complexity of the circuit design.

[0011] The technical solution for achieving the object of the present invention is as follows:

[0012] 1. A monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, from bottom to top, includes a substrate, a nucleation layer, a channel layer, an insertion layer and a barrier layer, and is characterized in that:

[0013] A piezoelectric ferroelectric layer is added on the barrier layer, and interdigital electrodes and gate electrodes are arranged on the upper part of the piezoelectric ferroelectric layer;

[0014] Etching grooves in the channel layer, the insertion layer, the barrier layer and the piezoelectric ferroelectric layer form a partition area, which is filled with a passivation layer;

[0015] The piezoelectric and ferroelectric layer on one side of the separation region and the interdigital electrodes on its upper part form a nitride surface acoustic wave device. On the other side of the separation region, an ohmic contact region, a source electrode and a drain electrode are provided, and together with the channel layer, the insertion layer, the barrier layer, the piezoelectric and ferroelectric layer, the passivation layer, and the gate electrode, they form a nitride field effect transistor.

[0016] The nitride surface acoustic wave device and the nitride field effect transistor share the piezoelectric and ferroelectric layer and are isolated by the separation region, and do not interfere with each other during operation.

[0017] Further, the piezoelectric and ferroelectric layer is made of continuously epitaxial single crystal Sc m Al n N material, where the component 0 < m < 0.35, and m + n = 1, and the thickness is 500 nm - 1500 nm;

[0018] Further, for the barrier layer, Sc x In y Al z Ga w N material is used, where the components are 0 ≤ x ≤ 0.3, 0 ≤ y ≤ 0.3, 0 ≤ z < 1, 0 ≤ w < 1 and x + y + z + w = 1, and the thickness is 6 nm - 30 nm.

[0019] Further, for the channel layer, GaN material is used, and the thickness is 500 nm - 4000 nm;

[0020] Further, for the nucleation layer, AlN material is used, and the thickness is 3 nm - 1000 nm;

[0021] Further, for the insertion layer, AlN material is used, and the thickness is 1 nm - 2 nm.

[0022] Further, for the substrate, any one of sapphire material, silicon material, silicon carbide material, diamond material, gallium nitride material, aluminum nitride material, and boron nitride material is used.

[0023] Further, for the passivation layer, any one of SiN material, Al2O3 material, and HfO2 material is used.

[0024] 2. A manufacturing method for a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, characterized by including the following steps:

[0025] 1) Using metal organic chemical vapor deposition technology or molecular beam epitaxy technology, grow a 3 nm - 1000 nm AlN nucleation layer on the substrate wafer;

[0026] 2) Using metal-organic chemical vapor deposition method or molecular beam epitaxy technique, grow a GaN channel layer with a thickness of 500 nm - 4000 nm on the AlN nucleation layer;

[0027] 3) Using metal-organic chemical vapor deposition method or molecular beam epitaxy technique, grow an AlN insertion layer with a thickness of 1 nm - 2 nm on the GaN channel layer;

[0028] 4) Using metal-organic chemical vapor deposition method or molecular beam epitaxy technique, grow a barrier layer with a thickness of 6 nm - 30 nm on the AlN insertion layer;

[0029] 5) Using metal-organic chemical vapor deposition method or molecular beam epitaxy technique, grow a piezoelectric ferroelectric layer with a thickness of 500 nm - 1500 nm on the barrier layer;

[0030] 6) Using a photoresist as a mask on the piezoelectric ferroelectric layer, select the field-effect transistor manufacturing area, and use a dry etching process to partially thin the piezoelectric ferroelectric layer to 30 nm - 80 nm;

[0031] 7) Using a photoresist as a mask on the thinned piezoelectric ferroelectric layer, select the source-drain ohmic contact area of the field-effect transistor, and use a dry etching method to etch the thinned piezoelectric ferroelectric layer until the upper part of the channel layer, forming a source-drain ohmic contact area groove;

[0032] 8) Using metal-organic chemical vapor deposition method or molecular beam epitaxy method to grow an Si-doped n-type GaN layer in the source-drain ohmic contact area groove, with the Si dose of (0.5 - 5)×10 20 cm -3 , forming an ohmic contact area;

[0033] 9) Using a photoresist as a mask, adopt an electron beam evaporation process to first deposit an ohmic contact metal Ti / Al / Ni / Au in the ohmic contact area, and then anneal it in a nitrogen atmosphere at 830 °C to form a source electrode and a drain electrode;

[0034] 10) Using a photoresist as a mask, select the surface acoustic wave device manufacturing area, and adopt an electron beam evaporation process to deposit a metal Ti / Au on the unthinned piezoelectric ferroelectric layer to form interdigital electrodes of the surface acoustic wave device;

[0035] 11) Using a photoresist as a mask, set the gate electrode area on the thinned piezoelectric ferroelectric layer in the field-effect transistor area, and adopt an electron beam evaporation process to deposit a metal Ni / Au in this area to form a gate electrode;

[0036] 12) Using the gate electrode metal as a mask, an inductively coupled plasma etching method is adopted, and a BCl3 / Cl2 gas source is used to completely etch the piezoelectric ferroelectric layer outside the gate electrode in the field effect transistor manufacturing area to form a groove;

[0037] 13) Using photoresist as a mask, a dry etching process is used to etch the piezoelectric ferroelectric layer to the bottom of the GaN channel layer to form a separation area;

[0038] 14) A plasma enhanced chemical vapor deposition method or an atomic layer deposition process is adopted to deposit a passivation layer with a thickness of 50 nm - 200 nm in the surface acoustic wave device manufacturing area, the field effect transistor manufacturing area, and the separation area;

[0039] 15) Using photoresist as a mask, a reactive ion etching method is adopted, and an SF6 gas source is used to etch the passivation layer to form gate electrode vias, source electrode vias, drain electrode vias, and interdigital electrode vias;

[0040] 16) A traditional optical lithography process is adopted to form an interdigital electrode Pad pattern in the surface acoustic wave device manufacturing area, and gate electrode, source electrode, and drain electrode Pad patterns in the field effect transistor manufacturing area. Then, using photoresist as a mask, an electron beam evaporation process is used to evaporate an Au metal layer on each electrode Pad pattern to form metal leads between each electrode Pad pattern and each electrode, completing the preparation of the monolithic integrated circuit.

[0041] The present invention has the following advantages compared with the prior art:

[0042] 1. Since a separation area is designed in the integrated circuit structure of the present invention to achieve isolation between the nitride surface acoustic wave device and the nitride field effect transistor, the process complexity increased by external lead interconnection and the influence of parasitic parameters can be avoided, further improving the performance and space utilization rate of the front-end system;

[0043] 2. Since a piezoelectric ferroelectric layer with a higher piezoelectric coefficient, sound velocity, electromechanical coupling coefficient, and strong ferroelectric characteristics is added to the integrated circuit of the present invention, not only the operating frequency, quality factor, and power handling capacity of the surface acoustic wave device are improved, enabling the integrated circuit to operate in a high-performance system; but also it can be used as a ferroelectric control layer of the field effect transistor, increasing the gate control ability of the transistor, reducing the subthreshold swing, and thus reducing the power consumption of the integrated circuit; it can also deplete the channel of the field effect transistor, realizing a positive shift of the threshold voltage of the device and reducing the design difficulty of the integrated circuit;

[0044] 3. When fabricating the integrated circuit of the present invention, the problem that it is difficult to monolithically epitaxially integrate the surface acoustic wave device made of polycrystalline material and the field effect transistor made of single crystal material is solved by metal organic chemical vapor deposition technology or molecular beam epitaxy technology, so as to achieve the consistency of the material processes of these two devices and the matching of the working frequency band and bandwidth, making the integrated circuit have a stable frequency band and high reliability.

[0045] 4. In the present invention, a single crystal epitaxial process is used to fabricate the ScAlN piezoelectric ferroelectric layer. Compared with the traditional magnetron sputtering, this method can grow a stable and consistent single crystal material, which is beneficial to reducing the working loss and clutter influence of the integrated circuit. Brief Description of the Drawings

[0046] Figure 1 is the structural diagram of a traditional polycrystalline AlN surface acoustic wave device;

[0047] Figure 2 is the structural diagram of a traditional GaN field effect transistor;

[0048] Figure 3 is the existing surface acoustic wave device and field effect transistor monolithic integrated circuit;

[0049] Figure 4 is the structural diagram of the nitride surface acoustic wave device and field effect transistor monolithic integrated circuit of the present invention;

[0050] Figure 5 is the fabrication of the present invention Figure 4 Schematic flow diagram of the integrated circuit. Detailed Description of the Embodiment

[0051] The embodiments of the present invention will be further described in detail with reference to the accompanying drawings.

[0052] Referring to Figure 4 , the nitride surface acoustic wave device and field effect transistor monolithic integrated circuit of this example includes a substrate 1, a nucleation layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5, a ferroelectric piezoelectric layer 6, and a passivation layer 7, where:

[0053] The substrate 1 is made of any one of sapphire material, silicon material, silicon carbide material, diamond material, gallium nitride material, aluminum nitride material, and boron nitride material;

[0054] The nucleation layer 2 is located on the substrate 1, made of AlN material, and has a thickness of 3 nm - 1000 nm;

[0055] The channel layer 3 is located on the nucleation layer 2, made of GaN material, and has a thickness of 500 nm - 4000 nm;

[0056] The insertion layer 4, located above the channel layer 3, is made of AlN material with a thickness of 1 nm - 2 nm;

[0057] The barrier layer 5, located above the insertion layer 4, is made of ScInAlGaN material with components 0 ≤ x ≤ 0.3, 0 ≤ y ≤ 0.3, 0 ≤ z < 1, 0 ≤ w < 1 and x + y + z + w = 1, and a thickness of 6 nm to 30 nm; x In y Al z Ga w N material;

[0058] The piezoelectric ferroelectric layer 6, located above the barrier layer 5, is made of continuous epitaxial single crystal ScAlN material with components 0 < m < 0.35 and m + n = 1, and a thickness of 500 nm - 1500 nm; m Al n N material;

[0059] The grooves in the channel layer 3, insertion layer 4, barrier layer 5 and piezoelectric ferroelectric layer 6 are filled with a passivation layer 7 to form a separation region;

[0060] The passivation layer 7 is made of any one of SiN material, Al2O3 material, and HfO2 material;

[0061] The piezoelectric ferroelectric layer 6 on one side of the separation region and the interdigital electrode above it form a nitride surface acoustic wave device, and a gate electrode is fabricated on the piezoelectric ferroelectric layer 6 on the other side of the separation region. The gate electrode, channel layer 3, insertion layer 4, barrier layer 5, piezoelectric ferroelectric layer 6, and passivation layer 7 form a nitride field effect transistor.

[0062] Refer to Figure 5 , and the present invention provides the following three embodiments for fabricating a nitride surface acoustic wave device and a field effect transistor monolithic integrated circuit.

[0063] Embodiment 1: Using molecular beam epitaxy technology, an InAlN barrier layer and a ScAlN piezoelectric ferroelectric layer of a nitride surface acoustic wave device and a field effect transistor monolithic integrated circuit are fabricated on a silicon carbide substrate. 0.17 Al 0.83 N barrier layer, Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer.

[0064] Step 1: Epitaxially grow an AlN nucleation layer, as Figure 5 (a).

[0065] Using molecular beam epitaxy technology, an AlN nucleation layer with a thickness of 200 nm is epitaxially grown on a silicon carbide substrate.

[0066] The process conditions for molecular beam epitaxy are: temperature is 750 °C, nitrogen gas flow rate is 3.0 sccm, and the equilibrium vapor pressure of the aluminum beam current is 3.2×10-7 Torr, and the radio frequency source power of nitrogen is 350 W.

[0067] Step 2: Epitaxially grow a GaN channel layer, as Figure 5 (b).

[0068] Use molecular beam epitaxy technology to epitaxially grow a GaN channel layer with a thickness of 2000 nm on the AlN nucleation layer.

[0069] The process conditions of molecular beam epitaxy are: the temperature is 750 °C, the nitrogen flow rate is 3.0 sccm, the equilibrium vapor pressure of the gallium beam current is 9.5×10 -7 Torr, and the radio frequency source power of nitrogen is 350 W.

[0070] Step 3: Deposit an AlN insertion layer, as Figure 5 (c)

[0071] Use molecular beam epitaxy technology to deposit an AlN insertion layer with a thickness of 1.5 nm on the GaN channel layer.

[0072] The process conditions of molecular beam epitaxy are: the temperature is 750 °C, the nitrogen flow rate is 3.0 sccm, the equilibrium vapor pressure of the aluminum beam current is 3.2×10 -7 Torr, and the radio frequency source power of nitrogen is 350 W.

[0073] Step 4: Deposit In 0.17 Al 0.83 N barrier layer, as Figure 5 (d).

[0074] Use molecular beam epitaxy technology to epitaxially grow an In 0.17 Al 0.83 N barrier layer with a thickness of 15 nm on the AlN insertion layer.

[0075] The process conditions of molecular beam epitaxy are: the temperature is 600 °C, the nitrogen flow rate is 3.0 sccm, the equilibrium vapor pressure of the indium beam current is 2.1×10 -7 Torr, the equilibrium vapor pressure of the aluminum beam current is 1.2×10 -7 Torr, and the radio frequency source power of nitrogen is 350 W.

[0076] Step 5: Deposit Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer, as Figure 5 (e).

[0077] Use molecular beam epitaxy technology to epitaxially grow an Sc 0.17 Al 0.83 N piezoelectric ferroelectric layer with a thickness of 1000 nm on the In 0.1 Al 0.9 N barrier layer.

[0078] The process conditions of molecular beam epitaxy are: temperature of 680℃, nitrogen flow rate of 3.0sccm, scandium beam equilibrium vapor pressure of 0.5×10 -7 Torr, the equilibrium vapor pressure of aluminum beam is 3.2×10 -7 Torr, and the nitrogen RF source power is 350W.

[0079] Step 6: Thinning part Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer, such as Figure 5 (f).

[0080] In Sc 0.1 Al 0.9 Using photoresist as a mask on the N piezoelectric ferroelectric layer, the field effect transistor fabrication area is selected, and the piezoelectric ferroelectric layer is partially thinned to 30nm using a dry etching process.

[0081] The process conditions used for etching are: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0082] Step 7: dry etching to form source and drain ohmic contact grooves, such as Figure 5 (g).

[0083] In the thinned Sc 0.1 Al 0.9 A mask is made on the N piezoelectric ferroelectric layer, and the source and drain ohmic contact areas of the field effect transistor are selected using a photoresist as a mask. The thinned Sc layers in the source and drain ohmic contact areas are removed by dry etching. 0.1 Al 0.9 N piezoelectric ferroelectric layer, In 0.17 Al 0.83 The N barrier layer, the AlN insertion layer and a portion of the GaN channel layer form source and drain ohmic contact region grooves.

[0084] The process conditions used for etching are: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0085] Step eight, depositing Si-doped n-type GaN layer to form an ohmic contact region, such as Figure 5 (h).

[0086] Molecular beam epitaxy was used to deposit a 50 nm thick Si-doped n-type GaN layer in the source-drain ohmic contact region. The Si doping concentration was 1.0×10 20 cm -3 .

[0087] The process conditions for molecular beam epitaxy are as follows: the temperature is 750 °C, the nitrogen flow rate is 3.0 sccm, the equilibrium vapor pressure of the gallium beam current is 9.5×10 -7 Torr, the equilibrium vapor pressure of the silicon beam current is 2.8×10 -8 Torr, and the power of the nitrogen radio frequency source is 350 W.

[0088] Step Nine: Fabricate the source electrode, drain electrode, and interdigital electrodes, as shown in Figure 5 (i).

[0089] 9.1) Fabricate a mask on the partially thinned Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer. Use electron beam evaporation technology to deposit the Ti / Al / Ni / Au metal combination on the source-drain ohmic contact regions respectively, with the metal thicknesses being 0.02 μm / 0.05 μm / 0.04 μm / 0.04 μm; then perform rapid thermal annealing in a nitrogen atmosphere at 830 °C to fabricate the source electrode and drain electrode;

[0090] 9.2) Fabricate a mask on the unthinned Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer. Select the surface acoustic wave device fabrication area. Use electron beam evaporation technology to deposit the metals Ti / Au on the unthinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, with the metal thicknesses being 0.02 μm / 0.04 μm, to form the interdigital electrodes.

[0091] The process conditions for metal deposition are as follows: the vacuum degree is less than 1.5×10 -3 Pa, the power range is 500 - 800 W, and the evaporation rate is The process conditions for rapid thermal annealing are as follows: the temperature is 830 °C and the time is 30 s.

[0092] Step Ten: Fabricate the gate electrode, as shown in Figure 5 (j).

[0093] Fabricate a mask on the thinned Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer in the field effect transistor area. Select the gate electrode fabrication area. Use electron beam evaporation technology to deposit metals on the thinned Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer to fabricate the gate electrode, where the deposited metals are the Ni / Au metal combination with the metal thicknesses being 0.02 μm / 0.3 μm.

[0094] The process conditions for metal deposition are as follows: the vacuum degree is less than 1.4×10 -3 Pa, the power range is 400 - 800 W, and the evaporation rate is

[0095] Step Eleven, etch the gate-source conduction region and the gate-drain conduction region, as shown in Figure 5 (k).

[0096] Using the gate electrode metal as a mask, use inductively coupled plasma etching to remove the thinned Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer in the gate-source conduction region and the gate-drain conduction region respectively, to form a gate-source conduction region groove and a gate-drain conduction region groove.

[0097] The process conditions for etching are: the flow rate of Cl2 gas is 10 sccm, the flow rate of BCl3 gas is 25 sccm, and the etching time is 150 s.

[0098] Step Twelve, etch the piezoelectric ferroelectric layer in the two device fabrication regions to the bottom of the channel layer to form a partition region, as shown in Figure 5 (l).

[0099] Using photoresist as a mask, use dry etching process to etch the piezoelectric ferroelectric layer in the surface acoustic wave device fabrication region and the field effect transistor fabrication region to the bottom of the GaN channel layer to form a partition region between the two device fabrication regions.

[0100] The process conditions for etching are: the flow rate of Cl2 is 15 sccm, the pressure in the reaction chamber is 11 mTorr, and the electrode power is 180 W.

[0101] Step Thirteen, deposit a SiN passivation layer, as shown in Figure 5 (m).

[0102] Adopt plasma enhanced chemical vapor deposition method to deposit a SiN passivation layer with a thickness of 200 nm in the surface acoustic wave device fabrication region, the field effect transistor fabrication region and the partition region.

[0103] The process conditions for the plasma enhanced chemical vapor deposition method are: the time is 60 s, the pressure is 2200 mTorr, the temperature is 350 °C, the flow rate of SiH4 is 13.5 sccm, the flow rate of NH3 is 10 sccm, and the flow rate of N2 is 1000 sccm.

[0104] Step Fourteen, prepare gate electrode vias, source electrode vias, drain electrode vias and interdigital electrode vias on the SiN passivation layer, as shown in Figure 5 (n).

[0105] Using photoresist as a mask, adopt reactive ion etching method to etch the SiN passivation layer to the surface of the gate electrode, source electrode, drain electrode and interdigital electrode metal to form gate electrode vias, source electrode vias, drain electrode vias and interdigital electrode vias.

[0106] The process conditions adopted by the reactive ion etching method are as follows: the pressure is 1500 mTorr, the power is 200 W, the SF6 flow rate is 8 sccm, the CHF3 is 10 sccm, and the He flow rate is 150 sccm.

[0107] Step 15, lead out each electrode Pad on each electrode through-hole, such as Figure 5 (o).

[0108] Adopt the traditional optical lithography process to lithographically form the gate electrode, source electrode, drain electrode, and interdigital electrode metal Pad patterns on each electrode through-hole; use the electron beam evaporation method, and evaporate Au metal with a thickness of 80 nm on each electrode Pad at a rate of , and then soak it in acetone to respectively form the gate electrode Pad, source electrode Pad, drain electrode Pad, and interdigital electrode Pad interconnected with the gate electrode, source electrode, drain electrode, and interdigital electrode, thus completing the production of the monolithic integrated circuit.

[0109] Example 2, use the molecular beam epitaxy technology to fabricate Sc 0.18 Al 0.82 N barrier layer, nitride surface acoustic wave device and field effect transistor monolithic integrated circuit with Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer.

[0110] Step 1, use the molecular beam epitaxy technology to epitaxially grow the AlN nucleation layer, such as Figure 5 (a).

[0111] Set the temperature to 600 °C, the nitrogen flow rate to 0.6 sccm, the aluminum beam current equilibrium vapor pressure to 0.6×10 -7 Torr, and the nitrogen radio frequency source power to 350 W. Use the molecular beam epitaxy technology to epitaxially grow an AlN nucleation layer with a thickness of 3 nm on the gallium nitride substrate.

[0112] Step 2, use the molecular beam epitaxy technology to epitaxially grow the GaN channel layer, such as Figure 5 (b).

[0113] Set the temperature to 600 °C, the nitrogen flow rate to 0.6 sccm, the gallium beam current equilibrium vapor pressure to 3.5×10 -7 Torr, and the nitrogen radio frequency source power to 350 W. Use the molecular beam epitaxy technology to epitaxially grow a GaN channel layer with a thickness of 500 nm on the AlN nucleation layer.

[0114] Step 3, use the molecular beam epitaxy technology to epitaxially grow the AlN insertion layer, such as Figure 5 (c)

[0115] Set the temperature to 600 °C, the nitrogen flow rate to 0.6 sccm, the equilibrium vapor pressure of the aluminum beam current to 0.6×10 -7 Torr, and the power of the nitrogen radio frequency source to 350 W. Using molecular beam epitaxy technology, an AlN insertion layer with a thickness of 1 nm is epitaxially grown on the GaN channel layer.

[0116] Step 4, use molecular beam epitaxy technology to epitaxially grow Sc 0.18 Al 0.82 N barrier layer, as shown in Figure 5 (d).

[0117] Set the temperature to 650 °C, the nitrogen flow rate to 0.6 sccm, the equilibrium vapor pressure of the scandium beam current to 0.5×10 -7 Torr, the equilibrium vapor pressure of the aluminum beam current to 0.6×10 -7 Torr, and the power of the nitrogen radio frequency source to 350 W. Using molecular beam epitaxy technology, a 6-nm Sc 0.18 Al 0.82 N barrier layer is epitaxially grown on the AlN insertion layer.

[0118] Step 5, use molecular beam epitaxy technology to epitaxially grow Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, as shown in Figure 5 (e).

[0119] Set the temperature to 650 °C, the nitrogen flow rate to 0.6 sccm, the equilibrium vapor pressure of the scandium beam current to 0.5×10 -7 Torr, the equilibrium vapor pressure of the aluminum beam current to 0.6×10 -7 Torr, and the power of the nitrogen radio frequency source to 350 W. Using molecular beam epitaxy technology, a 500-nm Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer is epitaxially grown on the Sc 0.18 Al 0.82 N barrier layer.

[0120] Step 6, use dry etching technology to thin part of the Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, as shown in Figure 5 (f).

[0121] Using photoresist as a mask on the Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, select the area for fabricating the field effect transistor, set the Cl2 flow rate to 20 sccm, the pressure in the reaction chamber to 15 mTorr, and the electrode power to 220 W. Thin part of the Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer to 50 nm.

[0122] Step 7: Use dry etching technology to etch the selected layers, such as Figure 5 (g).

[0123] Fabricate a mask on the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, set the process conditions of Cl2 flow rate of 20 sccm, reaction chamber pressure of 15 mTorr, and electrode power of 220 W, and remove the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, Sc 0.18 Al 0.82 N barrier layer, AlN insertion layer, and part of the GaN channel layer to form a source-drain ohmic contact region groove.

[0124] Step 8: Use molecular beam epitaxy technology to epitaxially grow an Si-doped n-type GaN layer to form an ohmic contact region, such as Figure 5 (h).

[0125] Set the temperature to 600 °C, nitrogen flow rate to 0.6 sccm, gallium beam flux equilibrium vapor pressure to 3.5×10 -7 Torr, silicon beam flux equilibrium vapor pressure to 1.6×10 -8 Torr, and nitrogen radio frequency source power to 350 W. Deposit an n-type GaN layer with a thickness of 60 nm and an Si doping concentration of 0.5×10 20 cm -3 in the source-drain ohmic contact region groove.

[0126] Step 9: Use electron beam evaporation technology to fabricate source electrodes, drain electrodes, and interdigital electrodes, such as Figure 5 (i).

[0127] 9.1) Fabricate a mask on part of the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric, set the vacuum degree to less than 1.4×10 - 3 Pa, the power range to 400 - 800 W, and the evaporation rate to Under the process conditions, deposit the Ti / Al / Ni / Au metal combination on the source-drain ohmic contact regions respectively, with the metal thicknesses of 0.05 μm / 0.12 μm / 0.08 μm / 0.08 μm; then perform a 30 s rapid thermal annealing in a nitrogen atmosphere at 830 °C to fabricate the source and drain electrodes;

[0128] 9.2) Fabricate a mask on the unthinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, select the surface acoustic wave device fabrication area, set the vacuum degree to less than 1.4×10-3 Pa, with a power range of 400 - 800 W and an evaporation rate of Under the process conditions, on the unthinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer, deposit a Ti / Au metal combination with a metal thickness of 0.05 μm / 0.08 μm.

[0129] Step 10, fabricate the gate electrode using electron beam evaporation technology, as shown in Figure 5 (j).

[0130] On the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer in the field effect transistor fabrication area, fabricate a mask, select the gate electrode fabrication area, and set the vacuum degree to be less than 1.4×10 -3 Pa, with a power range of 400 - 800 W and an evaporation rate of Under the process conditions, deposit a Ni / Au metal combination with a metal thickness of 0.04 μm / 0.5 μm on the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer to complete the fabrication of the gate electrode.

[0131] Step 11, use the inductively coupled plasma process to fabricate the conduction region grooves, as shown in Figure 5 (k).

[0132] Using the gate electrode metal as a mask, adopt the inductively coupled plasma process, set the Cl2 gas flow rate to 10 sccm, the BCl3 gas flow rate to 25 sccm, and the etching time to 50 s. Remove the thinned Sc 0.18 Al 0.82 N piezoelectric ferroelectric layer outside the gate electrode in the field effect transistor fabrication area to form the gate-source conduction region grooves and the gate-drain conduction region grooves.

[0133] Step 12, use the dry etching process to form the separation area between the two device fabrication areas, as shown in Figure 5 (l).

[0134] Using photoresist as a mask, set the Cl2 flow rate to 20 sccm, the reaction chamber pressure to 15 mTorr, and the electrode power to 220 W. Etch the piezoelectric ferroelectric layer in the surface acoustic wave device fabrication area and the field effect transistor fabrication area to the bottom of the GaN channel to form the separation area.

[0135] Step 13, deposit the Al2O3 passivation layer using atomic layer deposition technology, as shown in Figure 5 (m).

[0136] Set the process conditions with the time being 40 s, the pressure being 2000 mTorr, the temperature being 300 °C, the flow rate of Al(CH3)3 being 850 sccm, the flow rate of H2O being 350 sccm, and the flow rate of N2 being 1000 sccm. Use the atomic layer deposition process to deposit a 50-nm-thick Al2O3 passivation layer on the surface acoustic wave device fabrication area, the field effect transistor fabrication area, and the separation area.

[0137] Step 14, Prepare gate electrode vias, source electrode vias, drain electrode vias, and interdigital electrode vias on the Al2O3 passivation layer, as Figure 5 (n).

[0138] Using photoresist as a mask, adopt the reactive ion etching method, set the process conditions with the pressure being 1500 mTorr, the power being 200 W, the flow rate of SF6 being 8 sccm, CHF3 being 10 sccm, and the flow rate of He being 150 sccm, and etch the Al2O3 passivation layer to the surface of each electrode metal to respectively form gate electrode vias, source electrode vias, drain electrode vias, and interdigital electrode vias.

[0139] Step 15, Use optical lithography and electron beam evaporation methods to lead out each electrode Pad on each electrode via to complete the fabrication of the monolithic integrated circuit, as Figure 5 (o).

[0140] First, use the traditional optical lithography process to respectively form the patterns of each electrode Pad on each electrode via; then set the process conditions, use the electron beam to evaporate 80-nm-thick Au metal on the patterns of each electrode Pad, and then soak it in acetone to respectively form the gate electrode Pad, source electrode Pad, drain electrode Pad, and interdigital electrode Pad interconnected with the gate electrode, source electrode, drain electrode, and interdigital electrode to complete the fabrication of the monolithic integrated circuit.

[0141] Example 3, Use metal organic chemical vapor deposition technology to fabricate an Al 0.25 Ga 0.75 N barrier layer and an Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer nitride surface acoustic wave device and field effect transistor monolithic integrated circuit.

[0142] Step A, Deposit an AlN nucleation layer, as Figure (a).

[0143] Using metalorganic chemical vapor deposition technology, under the process conditions of an epitaxial temperature of 1200 °C, a pressure of 45 Torr, an aluminum source flow rate of 18.0 sccm, an ammonia flow rate of 3500 sccm, and a hydrogen flow rate of 2500 sccm, an AlN nucleation layer with a thickness of 1000 nm was epitaxially grown on an aluminum nitride substrate.

[0144] Step B, deposit a GaN channel layer, as ​ (b).

[0145] Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1200 °C, a pressure of 45 Torr, an ammonia flow rate of 3500 sccm, a gallium source flow rate of 180 sccm, and a hydrogen flow rate of 2500 sccm, a GaN channel layer with a thickness of 4000 nm was deposited on the AlN nucleation layer.

[0146] Step C, deposit an AlN insertion layer, as ​ (c)

[0147] Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1200 °C, a pressure of 45 Torr, an aluminum source flow rate of 18 sccm, an ammonia flow rate of 3500 sccm, and a hydrogen flow rate of 2500 sccm, an AlN insertion layer with a thickness of 2 nm was deposited on the GaN channel layer.

[0148] Step D, deposit Al 0.25 Ga 0.75 N barrier layer, as ​ (d).

[0149] Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1200 °C, a pressure of 45 Torr, an aluminum source flow rate of 10 sccm, a gallium source flow rate of 80 sccm, an ammonia flow rate of 3500 sccm, and a hydrogen flow rate of 2500 sccm, an Al 0.25 Ga 0.75 N barrier layer was deposited.

[0150] Step E, deposit Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer, as ​ (e).

[0151] Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 1200 °C, a pressure of 80 Torr, an aluminum source flow rate of 10 sccm, a scandium source flow rate of 3000 sccm, an ammonia flow rate of 3500 sccm, and a hydrogen flow rate of 2500 sccm, on Al 0.25 Ga 0.75Deposit Sc with a thickness of 1500 nm on the N barrier layer 0.3 Al 0.7 N piezoelectric ferroelectric layer.

[0152] Step F, dry etching, thinning part of the Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer, as shown in ​ (f).

[0153] On the Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer, using photoresist as a mask, select the field effect transistor manufacturing area, use dry etching technology, with a Cl2 flow rate of 18 sccm, a reaction chamber pressure of 12 mTorr, and an electrode power of 160 W, thin part of the Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer to 80 nm.

[0154] Step G, dry etching, forming source-drain ohmic contact area grooves, as shown in ​ (g).

[0155] On the thinned Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer, make a mask, using photoresist as a mask, select the source-drain ohmic contact area of the field effect transistor, use dry etching technology, with a Cl2 flow rate of 18 sccm, a reaction chamber pressure of 12 mTorr, and an electrode power of 160 W, respectively remove the Sc 0.3 Al 0.7 on the N piezoelectric ferroelectric layer, Al 0.25 Ga 0.75 N barrier layer, AlN insertion layer and part of the GaN channel layer, forming source-drain ohmic contact area grooves.

[0156] Step H, deposit Si-doped n-type GaN layer, forming ohmic contact area, as shown in ​ (h).

[0157] Under the process conditions of a temperature of 1200 °C, a pressure of 45 Torr, a gallium source flow rate of 60 sccm, a silicon source flow rate of 800 sccm, an ammonia flow rate of 3500 sccm, and a hydrogen flow rate of 2500 sccm, deposit an n-type GaN layer with a thickness of 120 nm and a Si doping concentration of 5×10 20 cm -3 in the source-drain ohmic contact area grooves.

[0158] Step I, fabricate source electrode, drain electrode and interdigital electrodes, as shown in ​ (i).

[0159] I.1) On the thinned Sc0.3 Al 0.7 A mask is fabricated on the Sc -3 Al 0.3 N piezoelectric ferroelectric layer. Using electron beam evaporation technology, metal is deposited on the source-drain ohmic contact regions under the process conditions of a vacuum degree less than 1.6×10 -3 Pa, a power range of 600 - 900 W, and an evaporation rate of . Among them, the deposited metal uses a Ti / Al / Ni / Au metal combination, and the metal thickness is 0.02μm / 0.2μm / 0.05μm / 0.05μm.

[0160] I.2) A mask is fabricated on the unthinned Sc -3 Al 0.3 N piezoelectric ferroelectric layer. The surface acoustic wave device fabrication area is selected. Under the process conditions of a vacuum degree less than 1.6×10 0.3 Al 0.7 Pa, a power range of 600 - 900 W, and an evaporation rate of -3 , using electron beam evaporation technology, a Ti / Au metal combination is deposited on the unthinned Sc -3 Al 0.3 N piezoelectric ferroelectric layer, and the metal thickness is 0.02μm / 0.05μm. 0.3 0.7 Al 0.7 N piezoelectric ferroelectric layer.

[0161] Step J, fabricate the gate electrode, as shown in ​ (j).

[0162] A mask is fabricated on the thinned Sc -3 Al 0.3 N piezoelectric ferroelectric layer. The gate electrode fabrication area is selected. Using electron beam evaporation technology, on the Sc -3 Al 0.3 N piezoelectric ferroelectric layer, under the process conditions of a vacuum degree less than 1.5×10 0.3 Al 0.7 Pa, a power range of 300 - 800 W, and an evaporation rate of 0.3 Al 0.7 N piezoelectric ferroelectric layer, fabricate the gate electrode. Among them, the deposited metal is a Ni / Au metal combination, and the metal thickness is 0.03μm / 0.4μm. -3 Pa, a power range of 300 - 800 W, and an evaporation rate of

[0163] Step K, etch the gate-source conduction region and the gate-drain conduction region, as shown in ​ (k).

[0164] Using the gate electrode metal as a mask, adopting inductively coupled plasma etching process, under the process conditions of a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 200 s, remove the thinned Sc -3 Al 0.3 N piezoelectric ferroelectric layer on the gate-source conduction region and the gate-drain conduction region, and respectively form a gate-source conduction region groove and a gate-drain conduction region groove. 0.3 Al 0.7 N piezoelectric ferroelectric layer.

[0165] Step L, isolate the surface acoustic wave device fabrication area from the field effect transistor fabrication area, as shown in ​ (l).

[0166] Using photoresist as a mask, and with a dry etching technique, etch the piezoelectric ferroelectric layer of both devices to the bottom of the GaN channel under the process conditions of a Cl2 flow rate of 18 sccm, a reaction chamber pressure of 12 mTorr, and an electrode power of 160 W to form a separation region.

[0167] Step M, deposit a HfO2 passivation layer, as shown in ​ (m).

[0168] Using atomic layer deposition process, deposit a 100 - nm - thick HfO2 passivation layer in the surface acoustic wave device fabrication area, the field effect transistor fabrication area, and the separation region under the process conditions of a time of 70 s, a temperature of 280 °C, an ethylmethylamino hafnium flow rate of 1200 sccm, an H2O flow rate of 110 sccm, and an N2 flow rate of 1000 sccm.

[0169] Step N, etch through - holes for the gate electrode, source electrode, drain electrode, and interdigital electrode on the HfO2 passivation layer, as shown in ​ (n).

[0170] Using photoresist as a mask, and with a reactive ion etching method, etch the HfO2 passivation layer to the metal surfaces of the gate electrode, source electrode, drain electrode, and interdigital electrode under the process conditions of a pressure of 1500 mTorr, a power of 200 W, an SF6 flow rate of 8 sccm, a CHF3 of 10 sccm, and an He flow rate of 150 sccm to form through - holes for the gate electrode, source electrode, drain electrode, and interdigital electrode respectively.

[0171] Step O, lead out each electrode Pad on each electrode through - hole, as shown in ​ (o).

[0172] Adopt the traditional optical lithography process to lithographically form the patterns of the gate electrode, source electrode, and drain electrode metal Pads; on each electrode Pad pattern, use electron beam evaporation technology to evaporate Au metal with a thickness of 80 nm at a certain speed, and then soak it in acetone to respectively form the gate electrode Pad, source electrode Pad, drain electrode Pad, and interdigital electrode Pad interconnected with the gate electrode, source electrode, drain electrode, and interdigital electrode, thus completing the fabrication of the monolithic integrated circuit.

[0173] The above description is only three specific examples of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the used silicon carbide material, gallium nitride material, and aluminum nitride material for the substrate, sapphire material, silicon material, diamond material, or any one of boron nitride materials may also be used; for the barrier layer, in addition to the used In 0.17 Al 0.83 N, Sc 0.18 Al 0.82 N, Al 0.25 Ga 0.75 N, Sc x In y Al z Ga w N material with components 0 ≤ x ≤ 0.3, 0 ≤ y ≤ 0.3, 0 ≤ z < 1, 0 ≤ w < 1 and x + y + z + w = 1 and a thickness of 6 nm to 30 nm can also be used; for the piezoelectric ferroelectric layer, in addition to the used Sc 0.1 Al 0.9 N, Sc 0.18 Al 0.82 N, Sc 0.3 Al 0.7 N, single crystal Sc m Al[[ID=3,5]] n N material with components 0 < m < 0.35 and m + n = and a thickness of 500 nm - 1500 nm for continuous epitaxy can also be used; however, these modifications and changes based on the idea of the present invention are still within the scope of the claims of the present invention.

Claims

1. A manufacturing method of a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, characterized in that, Including the following steps: 1) Use metal organic chemical vapor deposition technology or molecular beam epitaxy technology to grow an AlN nucleation layer (2) with a thickness of 3 nm - 1000 nm on a substrate (1) wafer; 2) Use metal organic chemical vapor deposition method or molecular beam epitaxy technology to grow a GaN channel layer (3) with a thickness of 500 nm - 4000 nm on the AlN nucleation layer (2); 3) Use metal organic chemical vapor deposition method or molecular beam epitaxy technology to grow an AlN insertion layer (4) with a thickness of 1 nm - 2 nm on the GaN channel layer (3); 4) Use metal organic chemical vapor deposition method or molecular beam epitaxy technology to grow a barrier layer (5) with a thickness of 6 nm - 30 nm on the AlN insertion layer (4); 5) Use metal organic chemical vapor deposition method or molecular beam epitaxy technology to grow a piezoelectric ferroelectric layer (6) with a thickness of 500 nm - 1500 nm on the barrier layer (5); 6) Using photoresist as a mask on the piezoelectric ferroelectric layer (6), select the field effect transistor manufacturing area, and use dry etching process to partially thin the piezoelectric ferroelectric layer (6) to 30 nm - 80 nm; 7) Using photoresist as a mask on the thinned piezoelectric ferroelectric layer (6), select the source-drain ohmic contact area of the field effect transistor, and use dry etching method to etch the thinned piezoelectric ferroelectric layer (6) until the upper part of the channel layer (3) to form a source-drain ohmic contact area groove; 8) Use metalorganic chemical vapor deposition method or molecular beam epitaxy method to grow an Si-doped n-type GaN layer in the source-drain ohmic contact region groove, and the dose of Si is (0.5-5)×10 20 cm -3 , to form an ohmic contact region; 9) Using photoresist as a mask, adopting the electron beam evaporation process, first deposit the ohmic contact metal Ti / Al / Ni / Au in the ohmic contact region, and then anneal in an 830 o C nitrogen atmosphere to form the source electrode and the drain electrode; 10) Using photoresist as a mask, select the surface acoustic wave device manufacturing area, and use electron beam evaporation process to deposit metal Ti / Au on the unthinned piezoelectric ferroelectric layer (6) to form the interdigital electrodes of the surface acoustic wave device; 11) Using photoresist as a mask, set the gate electrode area on the thinned piezoelectric ferroelectric layer (6) in the field effect transistor area, and use electron beam evaporation process to deposit metal Ni / Au in this area to form the gate electrode; 12) Using the gate electrode metal as a mask, use inductively coupled plasma etching method, using BCl3 / Cl2 gas source, to completely etch the piezoelectric ferroelectric layer (6) outside the gate electrode in the field effect transistor manufacturing area to form a groove; 13) Using photoresist as a mask, use dry etching process to etch the piezoelectric ferroelectric layer (6) to the bottom of the GaN channel layer (3) to form a partition area; 14) Adopt plasma enhanced chemical vapor deposition method or atomic layer deposition process to deposit a passivation layer with a thickness of 50 nm - 200 nm in the surface acoustic wave device manufacturing area, field effect transistor manufacturing area and partition area; 15) Using photoresist as a mask, adopt reactive ion etching method, using SF6 gas source, to etch the passivation layer to form gate electrode vias, source electrode vias, drain electrode vias and interdigital electrode vias; 16) Using the traditional optical lithography process, an interdigital electrode Pad pattern is formed in the surface acoustic wave device fabrication area, and gate electrode, source electrode, and drain electrode Pad patterns are formed in the field effect transistor fabrication area. Then, using photoresist as a mask, an Au metal layer is evaporated on each electrode Pad pattern by the electron beam evaporation process to form metal leads between each electrode Pad pattern and each electrode, completing the preparation of the monolithic integrated circuit.

2. The manufacturing method according to claim 1, wherein: The metal organic chemical vapor deposition process conditions in the steps 1)-3) are as follows: The temperature is 950 o °C - 1250 o °C; The pressure is 40 Torr - 50 Torr; The flow rate of the aluminum source is 3 sccm - 20 sccm; The flow rate of the gallium source is 60 sccm - 200 sccm; The flow rate of ammonia is 3500 sccm; The flow rate of hydrogen is 2500 sccm.

3. The manufacturing method according to claim 1, wherein: The molecular beam epitaxy process conditions in the steps 1)-3) are as follows: The temperature is 600 o °C - 750 o °C; The flow rate of nitrogen is 0.6 sccm - 3.0 sccm; The equilibrium vapor pressure of the aluminum beam is 0.6×10 -7 Torr - 3.2×10 -7 Torr; The equilibrium vapor pressure of the gallium beam is 3.5×10 -7 Torr - 9.5×10 -7 Torr; The power of the nitrogen radio frequency source is 350 W.

4. The manufacturing method according to claim 1, wherein: The metal organic chemical vapor deposition process conditions in the step 4) are: The temperature is 950 o °C - 1250 o °C; The pressure is 40 Torr - 100 Torr; The flow rate of the scandium source is 2000 sccm - 5000 sccm; The flow rate of the aluminum source is 3 sccm - 20 sccm; The flow rate of the gallium source is 60 sccm - 200 sccm; The flow rate of the indium source is 50 sccm - 120 sccm; The flow rate of ammonia is 3500 sccm; The flow rate of hydrogen is 2500 sccm.

5. The manufacturing method according to claim 1, wherein: For the metal organic chemical vapor deposition method in the step 5), the process conditions are: The temperature is 950 o °C - 1250 o °C; The pressure is 40 Torr - 100 Torr; The flow rate of the scandium source is 2000 sccm - 5000 sccm; The flow rate of the aluminum source is 3 sccm - 20 sccm; The flow rate of ammonia is 3500 sccm; The flow rate of hydrogen is 2500 sccm.

6. The manufacturing method according to claim 1, wherein: For the molecular beam epitaxy method in the steps 4)-5), the process conditions are: The temperature is 600 o °C - 750 °C; The flow rate of nitrogen is 0.6 sccm - 3.0 sccm; The equilibrium vapor pressure of the aluminum beam current is 0.6×10 -7 Torr - 3.2×10 -7 Torr; The equilibrium vapor pressure of the gallium beam is 3.5×10 -7 Torr - 9.5×10 -7 Torr; The equilibrium vapor pressure of the scandium beam is 0.2×10 -7 Torr - 0.5×10 -7 Torr; The equilibrium vapor pressure of indium beam is 0.8×10 -7 Torr - 2.1×10 -7 Torr; The power of the nitrogen radio frequency source is 350 W.

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