An output circuit

Abstract

An output circuit, wherein a source of the first PMOS transistor is connected to a power supply voltage, a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and an output terminal of the output circuit, and a source of the first NMOS transistor is connected to ground. When the adjustment circuit comprises a second NMOS transistor, the first input terminal is connected to a gate of the first PMOS transistor, the second input terminal is connected to a drain of the second NMOS transistor, a gate of the second NMOS transistor is connected to the power supply voltage, and a source of the second NMOS transistor is connected to a gate of the first NMOS transistor. When the adjustment circuit comprises a second PMOS transistor, the first input terminal is connected to a source of the second PMOS transistor, a gate of the second PMOS transistor is connected to ground, a drain of the second PMOS transistor is connected to a gate of the first PMOS transistor, and the second input terminal is connected to a gate of the first NMOS transistor.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more particularly to an output circuit. Background Technology

[0002] like Figure 1 As shown, the main body of the typical output circuit is an inverter composed of an NMOS transistor N11 and a PMOS transistor P11. The gate of the PMOS transistor P11 is connected to the first input terminal Input-P, the source of the PMOS transistor P11 is connected to the power supply voltage VDDH, and the drain of the PMOS transistor P11 is connected to the drain of the NMOS transistor N11 and the output terminal Output of the output circuit. The gate of the NMOS transistor N11 is connected to the second input terminal Input-N, and the source of the NMOS transistor N11 is grounded to GND.

[0003] As the usable range of power supply voltage becomes wider, such as 1.8V-5V and 1.62V-5.5V, the ratio of the driving capability of NMOS transistor N11 to PMOS transistor P11 tends to vary significantly and monotonically within this range. The driving capability refers to the magnitude of the driving current.

[0004] Figure 2 This shows the relationship between the size ratio P / N of NMOS and PMOS transistors under the same drive capability under different processes and the power supply voltage VDDH.

[0005] from Figure 2 It can be seen that in the first process, under low voltage (e.g., 1.8V), only the NMOS transistor N11 has a strong driving capability. This leads to a large deviation in the driving capability of NMOS transistor N11 and PMOS transistor P11 under different power supply voltages. The size ratio of NMOS transistor N11 and PMOS transistor P11 under the same driving capability is difficult to control, thus affecting the output characteristics. For example, the rising and falling edges of the output signal are mismatched, and the duty cycle deviation is large, making it difficult to control at around 50% at high speed (50m). Summary of the Invention

[0006] The problem solved by this invention is that the output characteristics of some existing process output circuits are poor.

[0007] To address the aforementioned problems, the present invention provides an output circuit. The output circuit includes: a first input terminal, a second input terminal, a first PMOS transistor, a first NMOS transistor, and an adjustment circuit, wherein the adjustment circuit includes: a second NMOS transistor or a second PMOS transistor.

[0008] The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the output terminal of the output circuit, and the source of the first NMOS transistor is grounded.

[0009] When the adjustment circuit includes a second NMOS transistor, the first input terminal is connected to the gate of the first PMOS transistor, the second input terminal is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the power supply voltage, and the source of the second NMOS transistor is connected to the gate of the first NMOS transistor.

[0010] When the adjustment circuit includes a second PMOS transistor, the first input terminal is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is grounded, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the second input terminal is connected to the gate of the first NMOS transistor.

[0011] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0012] By changing the gate voltage of the first NMOS transistor or the first PMOS transistor using the second NMOS transistor or the second PMOS transistor, the drive current of the first NMOS transistor or the first PMOS transistor is adjusted, thereby balancing the output characteristics of the output circuit.

[0013] Furthermore, the present invention can further adjust the output drive current by adjusting the size ratio of the first NMOS to the third NMOS or the size ratio of the first PMOS to the third PMOS, so as to make the output characteristics of the output circuit better. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the existing output circuit.

[0015] Figure 2 It is the relationship between the size ratio P / N of NMOS and PMOS transistors under the same driving capability under different processes and the power supply voltage;

[0016] Figure 3 This is a schematic diagram of the output circuit according to an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the output circuit of another embodiment of the present invention;

[0018] Figure 5 The prior art and the present invention are in Figure 2 A comparison of the size ratio P / N and the power supply voltage when NMOS and PMOS transistors have the same driving capability under the first process. Detailed Implementation

[0019] To solve the above-mentioned technical problems, the present invention provides an output circuit, including: a first input terminal, a second input terminal, a first PMOS transistor, a first NMOS transistor, and an adjustment circuit, wherein the adjustment circuit includes: a second NMOS transistor or a second PMOS transistor.

[0020] The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the output terminal of the output circuit.

[0021] When the adjustment circuit includes a second NMOS transistor, the first input terminal is connected to the gate of the first PMOS transistor, the second input terminal is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the power supply voltage, and the source of the second NMOS transistor is connected to the gate of the first NMOS transistor.

[0022] When the adjustment circuit includes a second PMOS transistor, the first input terminal is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is grounded, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the second input terminal is connected to the gate of the first NMOS transistor.

[0023] To clearly describe the case where the adjustment circuit includes a second NMOS transistor or a second PMOS transistor, two specific embodiments are described below.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Please refer to Figure 3 In one embodiment, the output circuit includes: a first input terminal Input-P1, a second input terminal Input-N1, a first PMOS transistor P21, a first NMOS transistor N21, and an adjustment circuit. The adjustment circuit includes: a second NMOS transistor N22.

[0026] The source of the first PMOS transistor P21 is connected to the power supply voltage VDDH, and the drain of the first PMOS transistor P21 is connected to the drain of the first NMOS transistor N21 and the output terminal Output of the output circuit. The source of the first NMOS transistor N21 is grounded to GND.

[0027] The first input terminal Input-P1 is connected to the gate of the first PMOS transistor P21, the second input terminal Input-N1 is connected to the drain of the second NMOS transistor N22, the gate of the second NMOS transistor N22 is connected to the power supply voltage VDDH, and the source of the second NMOS transistor N22 is connected to the gate of the first NMOS transistor N21.

[0028] In this embodiment, a second NMOS transistor N22 is added before the gate of the first NMOS transistor N21. This reduces the overdrive voltage of the first NMOS transistor N21 by the threshold voltage of one NMOS transistor, thereby reducing the drive current (drive capability). The reduced threshold voltage has a significant impact at low voltages, while its impact is smaller at high voltages, which is consistent with the overall output characteristics.

[0029] The adjustment circuit may further include a third NMOS transistor N23. The gate of the third NMOS transistor N23 is connected to the second input terminal Input-N1, the drain of the third NMOS transistor N23 is connected to the output terminal Output1 of the output circuit, and the source of the third NMOS transistor N23 is grounded to GND.

[0030] The third NMOS transistor N23 increases the drive capability of Output1, which, combined with the reduced drive capability of the first NMOS transistor N21 due to the second NMOS transistor N22, achieves a balance that meets design requirements. Specifically, since the drive capability of a MOS transistor is affected by its size and gate voltage, the drive capability of Output1 can be adjusted by changing the dimensions of the first NMOS transistor N21 and the third NMOS transistor N23. Therefore, the size ratio of the first NMOS transistor N21 to the third NMOS transistor N23 is related to the drive current of Output1.

[0031] Please refer to Figure 4 In another embodiment, the output circuit includes: a first input terminal Input-P2, a second input terminal Input-N2, a first PMOS transistor P31, a first NMOS transistor N31, and an adjustment circuit. The adjustment circuit includes: a second PMOS transistor P32.

[0032] The source of the first PMOS transistor P31 is connected to the power supply voltage VDDH, and the drain of the first PMOS transistor P31 is connected to the drain of the first NMOS transistor N31 and the output terminal Output of the output circuit. The source of the first NMOS transistor N31 is grounded to GND.

[0033] The first input terminal Input-P2 is connected to the source of the second PMOS transistor P32, the gate of the second PMOS transistor P32 is grounded to GND, the drain of the second PMOS transistor P32 is connected to the gate of the first PMOS transistor P31, and the second input terminal Input-N2 is connected to the gate of the first NMOS transistor N31.

[0034] In this embodiment, a second PMOS transistor P32 is added before the gate of the first PMOS transistor P31. This reduces the overdrive voltage of the first PMOS transistor P31 by the threshold voltage of one PMOS transistor, thereby reducing the drive current (drive capability). The reduced threshold voltage has a significant impact at low voltages, while its impact is smaller at high voltages, which is consistent with the overall output characteristics.

[0035] The adjustment circuit may further include a third PMOS transistor, P33.

[0036] The gate of the third PMOS transistor P33 is connected to the first input terminal Input-P2, the drain of the third PMOS transistor P33 is connected to the output terminal Output2 of the output circuit, and the source of the third PMOS transistor P33 is connected to the power supply voltage VDDH.

[0037] The third PMOS transistor, P33, increases the drive capability of Output1. This, combined with the reduced drive capability of the first PMOS transistor, N31, by the second PMOS transistor, P32, achieves a balance that meets design requirements. Specifically, since the drive capability of a MOS transistor is affected by its size and gate voltage, the drive capability of Output2 can be adjusted by changing the dimensions of the first PMOS transistor, P31, and the third PMOS transistor, P33. Therefore, the size ratio of the first PMOS transistor, P31, and the third PMOS transistor, P33 is related to the drive current of Output2.

[0038] Figure 3 The illustrated embodiment is more suitable for: under the same driving capability, Figure 1 When the size ratio of PMOS transistor P11 to NMOS transistor N11 in the circuit becomes significantly higher under low voltage, the following applies: Figure 3 Replace the existing output circuit Figure 1 The output circuit exhibits a small deviation in the size ratio of PMOS and NMOS transistors under different voltages, thus improving output characteristics.

[0039] Figure 4 The illustrated embodiment is more suitable for: under the same driving capability, Figure 1 When the size ratio of PMOS transistor P11 to NMOS transistor N11 decreases significantly under low voltage, the following should be considered: Figure 4 Replace the existing output circuit Figure 1 The output circuit is improved to enhance output characteristics.

[0040] In light of the above, technicians can first... Figure 1The driving capability of the NMOS transistor N11 and PMOS transistor P11 in the existing output circuit shown was tested. With a PMOS to NMOS size ratio of approximately 2:1, and considering the same driving capability, when the size ratio of PMOS transistor P11 to NMOS transistor N11 significantly increases at low voltage, the driving capability is... Figure 3 The circuit shown replaces the output circuit, improving its output characteristics. When the drive capability is the same, but the size ratio of PMOS transistor P11 to NMOS transistor N11 decreases significantly under low voltage, the circuit used... Figure 4 The circuit shown replaces the output circuit, improving its output characteristics.

[0041] like Figure 5 As shown, by comparing the size ratio P / N of NMOS and PMOS transistors under the same process and driving capability in the prior art and the present invention with the relationship between the power supply voltage, it can be seen that using the technical solution of the present invention, a stable P / N size ratio can be obtained, thereby improving the output characteristics.

[0042] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An output circuit, characterized in that, include: The system comprises a first input terminal, a second input terminal, a first PMOS transistor, a first NMOS transistor, and an adjustment circuit, wherein the adjustment circuit includes a second NMOS transistor or a second PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the output terminal of the output circuit, and the source of the first NMOS transistor is grounded. When the adjustment circuit includes a second NMOS transistor, the first input terminal is connected to the gate of the first PMOS transistor, the second input terminal is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the power supply voltage, and the source of the second NMOS transistor is connected to the gate of the first NMOS transistor. When the adjustment circuit includes a second PMOS transistor, the first input terminal is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is grounded, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the second input terminal is connected to the gate of the first NMOS transistor. When the adjustment circuit includes a second NMOS transistor, the adjustment circuit further includes a third NMOS transistor; the gate of the third NMOS transistor is connected to the second input terminal, the drain of the third NMOS transistor is connected to the output terminal of the output circuit, and the source of the third NMOS transistor is grounded; When the adjustment circuit includes a second PMOS transistor, the adjustment circuit further includes a third PMOS transistor; the gate of the third PMOS transistor is connected to the first input terminal, the drain of the third PMOS transistor is connected to the output terminal of the output circuit, and the source of the third PMOS transistor is connected to the power supply voltage.

2. The output circuit as described in claim 1, characterized in that, The size ratio of the first NMOS transistor to the third NMOS transistor is related to the drive current at the output terminal of the output circuit.

3. The output circuit as described in claim 1, characterized in that, The size ratio of the first PMOS transistor to the third PMOS transistor is related to the drive current at the output terminal of the output circuit.

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