A high-speed digital output circuit and device based on isolated power supply

Abstract

This invention discloses a high-speed digital output circuit and device based on an isolated power supply, comprising an isolated power supply, a high-speed isolation device, a MOS driver, and a MOS transistor. The first port of the isolated power supply is connected to the power supply terminal, the third port of the isolated power supply is connected to the power supply terminal, and the fourth port of the isolated power supply is connected to the second power supply terminal (COM). The third and fourth ports of the isolated power supply are respectively connected to the power distribution terminals of the high-speed isolation device. The first input terminal of the high-speed isolation device is connected to the power supply terminal, the second input terminal of the high-speed isolation device is connected to a current-limiting resistor, and the power distribution terminals of the high-speed isolation device are connected to the third and fourth ports of the isolated power supply. The output terminal of the high-speed isolation device is sequentially connected to the input terminal of the MOS driver and the gate of the MOS transistor. The power supply terminal of the MOS driver is connected to the third port of the isolated power supply, and the output terminal of the MOS driver is connected to the gate of the MOS transistor. The drain of the MOS transistor is connected to the equivalent load and the third power supply terminal. This improves the anti-interference capability of the high-speed digital output device.

Description

Technical Field

[0001] This invention relates to the field of industrial automation technology, and in particular to a high-speed digital output circuit and device based on an isolated power supply. Background Technology

[0002] In industrial automation, digital output primarily serves as a device for converting low-voltage (a few volts) control signals (such as those from CPUs and FPGAs) to high-voltage levels. These devices are generally categorized into relay outputs and MOS (Metal-Oxide-Semiconductor) outputs. MOS digital outputs are further divided into source-type and sink-type digital outputs.

[0003] Existing technologies have made numerous attempts to cover digital output methods. For example, utility model patent application number 201920894426.4 discloses a high-speed output interface circuit for a power distribution automation terminal tester, providing a high-speed driving method, but it does not address the protection of high-voltage transistors (such as MOSFETs) during low-voltage to high-voltage transitions in digital output. Utility model patent application number 201520301295.6 discloses a fast discharge circuit for the gate-source parasitic capacitance of a PMOS power transistor device, providing a method for fast turn-off of source-type high-speed digital output, but it also does not address the protection of high-voltage transistors (such as MOSFETs) during low-voltage to high-voltage transitions in digital output.

[0004] Therefore, it is necessary to propose a driving method for high-speed digital output based on isolated power supply, solve the transistor protection problem of high-speed digital output of MOS, and use different high-speed MOS transistor driving methods. Summary of the Invention

[0005] The purpose of this invention is to provide a high-speed digital output circuit and device based on an isolated power supply, which solves the transistor protection problem of high-speed digital output of MOS transistors and can use different high-speed MOS transistor driving methods.

[0006] This invention provides a high-speed digital output circuit based on an isolated power supply.

[0007] This includes: isolated power supplies, high-speed isolation devices, MOS drivers, MOS transistors, and equivalent loads;

[0008] The first port of the isolation power supply is connected to the first power supply terminal, the second port of the isolation power supply is grounded, the third port of the isolation power supply is connected to the second power supply terminal, and the fourth port of the isolation power supply is connected to the second power supply terminal COM. The third and fourth ports of the isolation power supply are respectively connected to the power distribution terminal of the high-speed isolation device for isolating input signals and output signals.

[0009] The first input terminal of the high-speed isolation device is connected to the first power supply terminal, the second input terminal of the high-speed isolation device is connected to the current limiting resistor, the power distribution terminal of the high-speed isolation device is connected to the third and fourth ports of the isolation power supply respectively, and the output terminal of the high-speed isolation device is connected to the input terminal of the MOS driver and the gate of the MOS transistor in sequence.

[0010] The power supply terminal of the MOS driver is connected to the third port of the isolation power supply, the ground terminal of the MOS driver is connected to the fourth port of the isolation power supply, and the output terminal of the MOS driver is connected to the gate of the MOS transistor to trigger the rapid charging and discharging of the MOS transistor.

[0011] The source of the MOS transistor is connected to the second power supply terminal or the first ground terminal, and the drain of the MOS transistor is connected to the equivalent load and the second power supply terminal or the second ground terminal, for triggering the on state and the off state.

[0012] Preferably, in the isolated power supply, the input portion formed by the first input terminal and the second input terminal is isolated from and independently set up with the output portion formed by the third input terminal and the fourth input terminal.

[0013] Preferably, when outputting source-type digital signals, the MOS transistor is a PMOS transistor; when outputting sink-type digital signals, the MOS transistor is an MMOS transistor.

[0014] Preferably, the MOS transistor includes a parasitic capacitor, one end of which is connected to the gate of the MOS transistor, and the other end of which is connected to the source of the MOS transistor.

[0015] Preferably, the circuit is isolated, with one side of the circuit having a first power supply terminal and a first ground terminal GND, and the other side of the circuit having a second power supply terminal and a second ground terminal COM.

[0016] The first power supply is the VDD port, and the second power supply is the L+ port.

[0017] Preferably, the isolated power supply and the external power supply for digital output are connected to a common ground or power source, and changes in the external power supply will not affect the operating voltage conditions of the circuit using the isolated power supply.

[0018] Preferably, when outputting a source-type digital quantity,

[0019] When the input on one side of the circuit is at a logic high level, the output logic of the high-speed isolation device is low according to the input-output relationship of the high-speed isolation device; and the output logic of the MOS driver is high according to the input and output relationship of the MOS driver.

[0020] The output reference of the isolation power supply is L+, and the output level of the MOS driver is 0 relative to the reference L+.

[0021] When the voltage difference between the gate and source of the PMOS transistor is 0, that is, when the control voltage of the PMOS transistor is 0, the PMOS transistor is in the off state and there is no output voltage on the equivalent load.

[0022] When the input on one side of the circuit is logic low, the output logic of the high-speed isolation device is high, the output logic of the MOS driver is low, and according to the output reference of the isolation power supply as L+, the output of the MOS driver is negative.

[0023] When the voltage difference between the gate and source of the PMOS transistor is -V1, that is, when the control voltage of the PMOS transistor is negative, the PMOS is in the turned-on state, and there is an output voltage on the equivalent load.

[0024] In this circuit, the circuit on the other side is isolated with L+ as the reference, and the circuit on the other side is isolated with GND as the reference. The output voltage of the isolation power supply is V1, then the negative output of the isolation power supply is -V1, and the positive output of the isolation power supply is 0.

[0025] Preferably, in the case of leaky digital output,

[0026] When the input on one side of the circuit is at a logic high level, the output logic of the high-speed isolation device is low according to the input-output relationship of the high-speed isolation device; and the output logic of the MOS driver is high according to the input and output relationship of the MOS driver.

[0027] The output reference of the isolation power supply is COM, and the output level of the MOS driver is 0 relative to the reference COM.

[0028] When the voltage difference between the gate and source of the NMOS transistor is 0, that is, when the control voltage of the NMOS transistor is 0, the NMOS transistor is in the off state and there is no output voltage on the equivalent load.

[0029] When the input on one side of the circuit is logic low, the output logic of the high-speed isolation device is high, and the output logic of the MOS driver is low. Since the output reference of the isolation power supply is COM, the output of the MOS driver is the output voltage of the isolation power supply.

[0030] When the voltage difference between the gate and source of the NMOS transistor is V1, that is, when the control voltage of the NMOS transistor is positive, the NMOS transistor is in the turned-on state, and there is an output voltage on the equivalent load.

[0031] The circuit on the other side of the isolation is referenced to COM, while the circuit on the other side of the isolation is referenced to GND.

[0032] Preferably, the isolated power supply is a DC / DC isolated power supply assembly.

[0033] The present invention also provides a high-speed digital output device based on an isolated power supply, the device comprising the high-speed digital output circuit based on an isolated power supply as described in the embodiments of the present invention.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] This invention provides a method for using MOSFETs to perform high-speed digital output in the field of industrial control. The method uses an isolated power supply as its core, which solves the problems of isolation and protection on the high-speed digital output side and improves the anti-interference capability of high-speed digital output modules or systems.

[0036] This invention employs an isolated power supply, which can be connected to the external power supply for digital output via a common ground or a power supply. Changes in the external power supply will not affect the operating voltage conditions of the circuit using the isolated power supply.

[0037] This invention uses isolated power supplies and isolators connected to the circuit to achieve isolation of digital output.

[0038] This invention uses a MOS driver to reduce the impact of the gate and source parasitic capacitances of the MOS transistor on digital output using MOS, thereby increasing the frequency of digital output using MOS. Attached Figure Description

[0039] Figure 1 This is a source-type digital output circuit diagram in an embodiment of the present invention;

[0040] Figure 2 This is a diagram of a leaky digital output circuit in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1

[0043] like Figure 1 , 2 As shown, the present invention provides a high-speed digital output circuit based on an isolated power supply, including: an isolated power supply B1, a high-speed isolation device B2, a MOS driver B3, a MOS transistor, and an equivalent load RL;

[0044] The first port of the isolation power supply B1 is connected to the first power supply terminal VDD, the second port of the isolation power supply B1 is grounded GND, the third port of the isolation power supply B1 is connected to the second power supply terminal L+, the fourth port of the isolation power supply B1 is connected to the second power supply terminal COM, and the third and fourth ports of the power supply B1 are connected to the power distribution terminal of the high-speed isolation device B2 for isolating input signals and output signals.

[0045] The first input terminal of the high-speed isolation device B2 is connected to the first power supply terminal VDD, the second input terminal of the high-speed isolation device B2 is connected to the current limiting resistor R1, the power distribution terminal of the high-speed isolation device B2 is connected to the third and fourth ports of the isolation power supply B1, and the output terminal of the high-speed isolation device B2 is sequentially connected to the input terminal IN of the MOS driver and the gate G of the MOS transistor; that is, the upper and lower power distribution terminals of the high-speed isolation device B2 are respectively connected to the third and fourth ports of the isolation power supply B1.

[0046] The power supply terminal of the MOS driver B3 is connected to the third port of the isolation power supply B1, the ground terminal of the MOS driver B3 is connected to the fourth port of the isolation power supply B1, and the output terminal OUT of the MOS driver B3 is connected to the gate G of the MOS transistor to trigger the fast charging and discharging of the MOS transistor.

[0047] The source S of the MOSFET is connected to the second power supply terminal L+ or COM, and the drain D of the MOSFET is connected to the equivalent load RL and the second power supply terminal L+ or COM, for triggering the on and off states.

[0048] In one embodiment, when outputting a source-type digital signal, the MOS transistor is a PMOS transistor.

[0049] In one embodiment, the MOS transistor used in the sink-type digital output is an MMOS transistor.

[0050] The present invention is implemented as follows: Figure 1 and 2 As shown, function block B1 is the isolated power supply section, function block B2 is the high-speed isolated input device, function block B3 is the MOS driver, R1 is the input current limiting resistor, and RL is the equivalent load. In-source digital output. Figure 1 Q1 is a PMOS transistor used in sink-type digital output. Figure 2 Q1 is an MMOS transistor.

[0051] Specifically, the circuit adopts an isolation method. The power supply on one side of the circuit includes a first power supply terminal VDD and a first ground terminal GND, and the power supply on the other side of the circuit includes a second power supply terminal L+ and a second ground terminal COM.

[0052] The first power supply is the VDD port, and the second power supply is the L+ port.

[0053] like Figure 1 and 2 As shown, the circuit system uses isolation. The power supply on the left consists of VDD and GND, while the power supply on the right consists of L+ and COM. This can be understood as L+ being the positive terminal of the output voltage and COM being the negative terminal.

[0054] In the source type digital quantity output, such as Figure 1 As shown.

[0055] 1) Assuming the circuit on the right side of the isolation block is referenced to L+, and the output voltage of the isolation power supply is V1, then the negative terminal of function block B1, i.e., the output of the fourth port, is -V1, and the positive terminal of function block B1, i.e., the output of the third port, is 0. The circuit on the left side of function block B1 is referenced to GND.

[0056] 2) Assume that the input and output logic of function block B2 is as follows: input logic high level, output logic low level; input logic low level, output logic high level.

[0057] 3) Assume that the input IN and output OUT logic of function block B3 are as follows: input logic high level, output logic high level; input logic low level, output logic low level.

[0058] like Figure 1As shown, when the input on the left is logic high, according to the input-output relationship of function block B2 above, the output logic of B2 is low; according to the input and output relationship of B3 above, the output logic of B3 is high; the output reference of module B1 is L+, therefore the output level of B3 is 0 relative to the reference L+. The gate G of Q1 is labeled Vg, and the source S of Q1 is labeled Vs. Therefore, the voltage difference between the gate and source of Q1 is Vg-Vs=0-0=Vgs=0. Because the control voltage Vgs of PMOS is 0, PMOS is in the off state, and there is no output voltage on the load RL; conversely, when the control input on the left is logic low, the output of function block B2 is high, and the output of function block B3 is low. According to the above assumption, if the output reference of module B1 is L+, then the output of B3 is -V1. The gate (G) of Q1 is labeled with voltage Vg, and the source (S) of Q1 is labeled with voltage Vs. Therefore, the voltage difference between the gate and source of Q1 is Vg-Vs=-V1-0=Vgs=-V1. Since the control voltage Vgs of the PMOS is negative, the PMOS transistor is in the on state, and there is an output voltage on the load RL.

[0059] Specifically, the PMOS transistor includes a parasitic capacitance Cgs, one end of which is connected to the gate G of the PMOS transistor, and the other end of which is connected to the source S of the PMOS transistor.

[0060] Based on the switching characteristics of PMOS transistors, parasitic capacitance Cgs exists between the gate (G) and source (S) of a PMOS transistor. Turning a PMOS transistor on or off essentially involves charging and discharging this parasitic capacitance Cgs. At low speeds, the switching frequency is low, and the effect of parasitic capacitance Cgs on the turn-on or turn-off of the PMOS transistor can be ignored. However, at high speeds, a fast charging and discharging path is needed for the parasitic capacitance Cgs, and the MOS driver B3 provides a path for charging and discharging the parasitic capacitance Cgs of the PMOS transistor.

[0061] Based on the characteristics of PMOS transistors, the voltage difference between the gate (G) and source (S) is limited. Overvoltage will damage the PMOS transistor. Therefore, using an isolated power supply is necessary. Figure 1 As shown in Figure B1, the output voltage is constant when... Figure 1When the power supply voltage on the right side, namely L+ and COM, increases, L+ will increase relative to COM. The third port of B1 is connected to the power supply L+, while the fourth port of B1 is unrelated to COM. Since the B1 functional block is a DC / DC module, its output voltage is constant. Therefore, the negative terminal of B1, namely the fourth port, will also increase relative to COM. The voltage difference between the third and fourth ports of B1 remains unchanged. Thus, the output of the B3 functional block will be limited, that is, the drive voltage Vgs of the PMOS transistor will be limited, thereby protecting the PMOS transistor from damage due to excessive Vgs voltage.

[0062] Similar to source-type digital output, in sink-type digital output... Figure 2 As shown,

[0063] 1) Assuming the circuit on the right side of the isolation is referenced to COM, and the output voltage of the isolation power supply B1 is V1, then the negative terminal of B1, i.e., the fourth port, outputs 0, and the positive terminal of B1, i.e., the third port, outputs V1. The circuit on the left side of the isolation is referenced to GND.

[0064] 2) Assume that the input and output logic of function block B2 is as follows: input logic high level, output logic low level; input logic low level, output logic high level.

[0065] 3) Assume that the input IN and output OUT logic of function block B3 are as follows: input logic high level, output logic high level; input logic low level, output logic low level.

[0066] like Figure 2 As shown, when the input on the left is logic high, according to the input-output relationship of function block B2 above, the output logic of B2 is low; according to the input and output relationship of B3 above, the output logic of B3 is high; the output reference of module B1 is COM, therefore the output level of B3 is 0 relative to the reference COM. The gate G of Q1 is labeled Vg, and the source S of Q1 is labeled Vs. Therefore, the voltage difference between the gate and source of Q1 is Vg-Vs=0-0=Vgs. Since the control voltage Vgs of NMOS is 0, NMOS is in the off state, and there is no output voltage on the load RL; conversely, when the control input on the left is logic low, the output of function block B2 is high, and the output of function block B3 is low. According to the above assumption, if the output reference of module B1 is COM, then the output of B3 is V1. The gate (G) of Q1 is labeled with voltage Vg, and the source (S) of Q1 is labeled with voltage Vs. Therefore, the voltage difference between the gate and source of Q1 is Vg-Vs=V1-0=Vgs=V1. Since the control voltage Vgs of the NMOS is positive, the NMOS is in the on state, and there is an output voltage on the load RL.

[0067] Based on the switching characteristics of NMOS transistors, parasitic capacitance Cgs exists at the gate (G) and source (S) of an NMOS transistor. Turning an NMOS transistor on or off essentially involves charging and discharging this parasitic capacitance Cgs. At low speeds, the switching frequency is low, and the effect of parasitic capacitance Cgs on the turn-on or turn-off of the NMOS transistor can be ignored. However, at high speeds, a fast charging and discharging path is needed for the parasitic capacitance Cgs. Therefore, the MOS driver provides a path for charging and discharging the parasitic capacitance Cgs of the NMOS transistor.

[0068] Based on the characteristics of MOSFETs, the voltage difference between the gate (G) and source (S) of a MOSFET is limited. Overvoltage will damage the MOSFET. Therefore, using an isolated power supply is necessary. Figure 2 As shown in Figure B1, the output voltage is constant and only related to... Figure 2 When the COM of the power supply is connected on the right, and the L+ voltage rises relative to the COM, the isolation power supply B1 is independent of L+. B1 will maintain a constant voltage, thereby limiting the NMOS drive voltage Vgs, thus protecting the NMOS transistor from damage due to excessive Vgs voltage.

[0069] Specifically, in the isolated power supply B1, the input portion formed by the first input terminal and the second input terminal is isolated from and independently set up with the output portion formed by the third input terminal and the fourth input terminal.

[0070] Specifically, the isolation power supply B1 is connected to the external power supply for digital output via a common ground or power supply. Changes in the external power supply will not affect the operating voltage conditions of the circuit using the isolation power supply.

[0071] The high-speed isolation device B2 used in this embodiment can also be a high-speed optocoupler, magnetic isolation device, or capacitive isolation device with the same function.

[0072] Example 2

[0073] Based on the same concept, the present invention also provides a high-speed digital output device / system / module based on isolated power supply, wherein the device / system / module includes a high-speed digital output circuit based on isolated power supply as described in the embodiments of the present invention, such as an output device like a circuit board.

[0074] This invention also provides a high-speed digital output device based on an isolated power supply, the device comprising the high-speed digital output circuit based on an isolated power supply as described in the embodiments of this invention. Its functional principles are as described in Embodiment 1 of this invention, and will not be repeated here.

[0075] This invention provides a method for using MOSFETs to perform high-speed digital output in the field of industrial control. The method uses an isolated power supply as its core, which solves the problems of isolation and protection on the high-speed digital output side and improves the anti-interference capability of high-speed digital output modules or systems.

[0076] For the preferred embodiments detailed in the above figures, there are alternative structures that are not limited. These are other embodiments obtained based on the implementation principles of the present invention and all fall within the protection scope of the present invention. The optocouplers, isolation power supplies, MOS drivers, and resistors in the figures of the present invention can be replaced by other circuits with the same function, without prejudice to the claims of the present invention.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed digital output circuit based on an isolated power supply, characterized in that, include: Isolated power supply, high-speed isolation device, MOS driver, MOSFET and equivalent load; The first port of the isolation power supply is connected to the first power supply terminal, the second port of the isolation power supply is grounded, the third port of the isolation power supply is connected to the second power supply terminal, and the fourth port of the isolation power supply is connected to the second power supply terminal COM. The third and fourth ports of the isolation power supply are respectively connected to the power distribution terminal of the high-speed isolation device for isolating input signals and output signals. The first input terminal of the high-speed isolation device is connected to the first power supply terminal, the second input terminal of the high-speed isolation device is connected to the current limiting resistor, the power distribution terminal of the high-speed isolation device is connected to the third and fourth ports of the isolation power supply respectively, and the output terminal of the high-speed isolation device is connected to the input terminal of the MOS driver and the gate of the MOS transistor in sequence. The power supply terminal of the MOS driver is connected to the third port of the isolation power supply, the ground terminal of the MOS driver is connected to the fourth port of the isolation power supply, and the output terminal of the MOS driver is connected to the gate of the MOS transistor to trigger the rapid charging and discharging of the MOS transistor. The source of the MOS transistor is connected to the second power supply terminal or the first ground terminal, and the drain of the MOS transistor is connected to the equivalent load and the second power supply terminal or the second ground terminal, for triggering the on state and the off state.

2. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, In the isolated power supply, the input portion formed by the first input terminal and the second input terminal is isolated from and independently set up with the output portion formed by the third input terminal and the fourth input terminal.

3. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, When outputting digital signals in source mode, a PMOS transistor is used; when outputting digital signals in sink mode, an MMOS transistor is used.

4. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, The MOS transistor includes a parasitic capacitor, one end of which is connected to the gate of the MOS transistor, and the other end of which is connected to the source of the MOS transistor.

5. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, The circuit is isolated. One side of the circuit is powered by a first power supply terminal and a first ground terminal GND. The other side of the circuit is powered by a second power supply terminal and a second ground terminal COM. The first power supply is the VDD port, and the second power supply is the L+ port.

6. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, The isolated power supply is connected to the external power supply for digital output via a common ground or power supply. Changes in the external power supply will not affect the operating voltage conditions of the circuit using the isolated power supply.

7. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, When outputting source-type digital values When the input on one side of the circuit is at a logic high level, the output logic of the high-speed isolation device is low according to the input-output relationship of the high-speed isolation device; and the output logic of the MOS driver is high according to the input and output relationship of the MOS driver. The output reference of the isolation power supply is L+, and the output level of the MOS driver is 0 relative to the reference L+. When the voltage difference between the gate and source of the PMOS transistor is 0, that is, when the control voltage of the PMOS transistor is 0, the PMOS transistor is in the off state and there is no output voltage on the equivalent load. When the input on one side of the circuit is logic low, the output logic of the high-speed isolation device is high, the output logic of the MOS driver is low, and according to the output reference of the isolation power supply as L+, the output of the MOS driver is negative. When the voltage difference between the gate and source of the PMOS transistor is -V1, that is, when the control voltage of the PMOS transistor is negative, the PMOS is in the turned-on state, and there is an output voltage on the equivalent load. In this circuit, the circuit on the other side is isolated with L+ as the reference, and the circuit on the other side is isolated with GND as the reference. The output voltage of the isolation power supply is V1, then the negative output of the isolation power supply is -V1, and the positive output of the isolation power supply is 0.

8. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, When outputting leaky digital values When the input on one side of the circuit is at a logic high level, the output logic of the high-speed isolation device is low according to the input-output relationship of the high-speed isolation device; and the output logic of the MOS driver is high according to the input and output relationship of the MOS driver. The output reference of the isolation power supply is COM, and the output level of the MOS driver is 0 relative to the reference COM. When the voltage difference between the gate and source of the NMOS transistor is 0, that is, when the control voltage of the NMOS transistor is 0, the NMOS transistor is in the off state and there is no output voltage on the equivalent load. When the input on one side of the circuit is logic low, the output logic of the high-speed isolation device is high, and the output logic of the MOS driver is low. Since the output reference of the isolation power supply is COM, the output of the MOS driver is the output voltage of the isolation power supply. When the voltage difference between the gate and source of the NMOS transistor is V1, that is, when the control voltage of the NMOS transistor is positive, the NMOS transistor is in the turned-on state, and there is an output voltage on the equivalent load. The circuit on the other side of the isolation is referenced to COM, while the circuit on the other side of the isolation is referenced to GND.

9. The high-speed digital output circuit based on isolated power supply as described in claim 1, characterized in that, The isolated power supply uses a DC / DC isolated power supply component.

10. A high-speed digital output device based on an isolated power supply, characterized in that, The device includes a high-speed digital output circuit based on an isolated power supply as described in any one of claims 1 to 9.

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