A DMA-based data sampling system and sampling method

Abstract

The application discloses a DMA-based data sampling system and a sampling method. In the sampling system, a timer unit sends a sampling trigger signal to each ADC multi-channel sampling unit at a set time interval, and each ADC sends a DMA request signal to a DMA control unit after sampling is completed. If the DMA control unit receives any DMA request signal, the DMA control unit collects the data sampled by all channels of each ADC in turn and transmits the data to a storage unit. For all ADCs, when the number of sampling points reaches a specified first sampling point number, a CPU interrupt is triggered, and when the number of sampling points reaches a specified second sampling point number, an iteration end signal is sent to a CPU unit. The CPU unit determines a new set of sampling data for single protection calculation when the interrupt is triggered, and updates the address of subsequent data storage after receiving the iteration end signal. Protection calculation is also performed based on a single set of sampling data for protection calculation. The application can be used for DTU, FTU and other devices to realize multi-channel synchronous high-speed data sampling, and the data acquisition efficiency and reliability can be improved.

Description

Technical Field

[0001] This invention relates to the field of power distribution network terminal equipment technology, and in particular to a data sampling system and method based on DMA (Direct Memory Access), which can be used in DTU, FTU and other equipment to achieve high-speed sampling. Background Technology

[0002] Smart distribution networks are a key component of smart grids, and automated monitoring terminal equipment is an important part of smart distribution networks. Feeder terminal units (FTUs) and switchgear terminal units (DTUs) are responsible for sampling and transmitting critical power system parameters. Higher sampling accuracy and more sampling points mean higher equipment performance and reliability. Improving the performance, reliability, and intelligence level of these terminal devices is an urgent problem to be solved in the intelligentization of distribution networks.

[0003] Existing DTUs and FTUs use ADCs for sampling, which requires the terminal device's CPU I / O ports as interrupt ports. However, as the sampling rate increases, the number of CPU interrupts also increases, and the CPU load rate rises rapidly. Experiments have shown that when there are many ADC chips and the sampling time is too short, the terminal device's CPU will experience performance degradation due to high occupancy. Specifically, the CPU's ability to handle other tasks, including interrupt handling, is weakened. This is detrimental to further improving device performance and to expanding the CPU's ability to perform other intelligent functions. The intelligentization and high performance of power distribution terminals require efficient, low-occupancy, and higher-speed sampling systems. Summary of the Invention

[0004] The purpose of this invention is to provide a DMA-based data sampling system and method, which can be used in devices such as DTUs and FTUs to achieve high-speed data sampling with multi-channel synchronization. The technical solution adopted by this invention is as follows.

[0005] On one hand, the present invention provides a DMA-based data sampling system, including a DMA control unit, a storage unit, a CPU unit, a timer unit, and multiple ADC multi-channel sampling units;

[0006] The timer unit is configured to send a sampling trigger signal to each ADC multi-channel sampling unit at a set time interval. Each ADC multi-channel sampling unit performs data sampling in response to receiving the sampling trigger signal and sends a DMA request signal to the DMA control unit after sampling is completed.

[0007] The DMA control unit is configured to, upon receiving any DMA request signal, sequentially collect the data sampled by each ADC according to the preset correspondence between source data address and target address, and transmit it to the corresponding target address in the storage unit; when collecting the data sampled by a single ADC, sequentially collect the data of each channel of the ADC to obtain the sampled data of all channels of the single ADC at a single sampling point.

[0008] The DMA control unit is also configured to send an interrupt trigger signal to the CPU unit when the number of sampling points acquired by all ADCs reaches a specified first number of sampling points, and to send an iteration end signal to the CPU unit when the number of sampling points acquired reaches a specified second number of sampling points.

[0009] The CPU unit is configured to: in response to receiving the interrupt trigger signal, determine a new set of sampled data for a single protection calculation; in response to receiving the iteration end signal, update the configuration of the correspondence between the source data address and the target address; and perform protection calculation based on the single set of sampled data for protection calculation.

[0010] Optionally, when the DMA control unit is collecting data from the same sampling point for all ADCs, after all channel data of each ADC has been collected, it increments the number of sampling points corresponding to the ADC that has just finished collecting by 1, and then collects all channel data of the next ADC until all ADCs at the same sampling point have been collected. Then it determines whether the number of sampling points corresponding to all ADCs has reached the specified first sampling point number or second sampling point number.

[0011] Optionally, when the DMA control unit is collecting data from the same sampling point for all ADCs, it will collect data from all channels of the next ADC after all channels of each ADC have been collected, until all ADCs at the same sampling point have been collected. Then, it will record the number of sampling points and increment it by 1. Then, it will determine whether the updated number of sampling points has reached the specified number of first or second sampling points.

[0012] Both of the above implementation methods can ensure that the same specified number of sampling points are obtained for all ADCs before the interrupt is triggered or before the iteration ends, thus ensuring the reliability of the data.

[0013] Optionally, the sampling trigger signal sent by each ADC multi-channel sampling unit of the timer unit is a rising edge signal, and the DMA request signal sent by the ADC multi-channel sampling unit to the DMA control unit is a falling edge signal.

[0014] Optionally, in response to receiving the interrupt trigger signal, the CPU unit performs the following operations during the interrupt: clearing the interrupt flag and updating the preset count of the protected calculation data group by 1 to mark and locate the sampling data group with the latest acquired first set number of sampling points.

[0015] Optionally, during the data acquisition and transmission process of the DMA control unit, the CPU unit synchronously performs protection calculations using the marked and located sampled data groups. That is, the CPU does not perform any protection calculations in the terminal, which can shorten interruption time and ensure that other CPU functions operate normally as much as possible.

[0016] Optionally, at any sampling point, if the DMA control unit fails to acquire sampling data from a certain ADC within a specified time, it will proceed with data acquisition for the next ADC; otherwise, the DMA control unit will perform data acquisition for the next ADC after acquiring a specified length of data from a single ADC. For example, in the case of an 8-channel ADC, if each channel can acquire 2 bytes of data, then for a single ADC, after transmitting 16 bytes of data, the DMA control unit will trigger channel switching and proceed to data acquisition for the next ADC.

[0017] Optionally, the DMA control unit, storage unit, CPU unit and timer unit are integrated into a sampling processor, or a microprocessor chip of model RT1064 is used.

[0018] Optionally, the number of ADC multi-channel sampling units is 5, each including 8 sampling channels; the ADC multi-channel sampling unit uses the AD7606 chip. This chip has 8 sampling channels, supports a maximum sampling frequency of 200Ksps, and has an input range of ±5V or ±10V.

[0019] The ADC multi-channel sampling unit can also use the AD7616 to enable free selection and configuration of sampling channels, meeting different working conditions and user needs.

[0020] Optionally, the set time interval is 125µs, the number of the first sampling points is 80, and the number of the second sampling points is 240. A sampling interval of 125µs corresponds to 160 sampling points per cycle. When all the ADC sampling data collected and transported reaches 240 points, the sampling data storage for one half-cycle is completed. At this time, the CPU unit resets the target address, and the data is no longer saved. The subsequent ADC data will overwrite the data of the previous half-cycle to avoid occupying too much internal CPU storage space.

[0021] Secondly, the present invention provides a DMA-based data sampling method, executed by a sampling processor, for data acquisition and transmission from multiple ADC multi-channel sampling units; the method includes:

[0022] A sampling trigger signal is sent to each ADC multi-channel sampling unit at a set time interval, and each ADC multi-channel sampling unit performs data sampling in response to receiving the sampling trigger signal;

[0023] The system receives DMA request signals sent by the ADC multi-channel sampling unit after sampling is completed. If any DMA request signal is received, the system sequentially collects the data sampled by each ADC according to the preset correspondence between the source data address and the target address, and transmits it to the corresponding target address in memory. When collecting the data sampled by a single ADC, the system sequentially collects the data of each channel of the ADC to obtain all channel sampled data of a single ADC at a single sampling point.

[0024] For all ADCs, when the number of sampling points acquired reaches the specified first sampling point number, an interrupt is triggered, and a new set of sampling data for a single protection calculation is determined; when the number of sampling points acquired reaches the specified second sampling point number, the correspondence between the source data address and the target address is configured and updated.

[0025] During the data acquisition and transmission process of each ADC multi-channel sampling unit, protection calculations are performed synchronously based on a single set of sampling data used for protection calculations.

[0026] Beneficial effects

[0027] This invention relates to a DMA-based data sampling system. By combining cyclic sampling of multiple channels in a single ADC chip with cyclic sampling of multiple ADC chips, a CPU interrupt is triggered when the obtained data reaches the required level for protection calculations. During the CPU interrupt, only the newly obtained data set is located. Protection calculations are performed outside the interrupt and during ADC acquisition. This system enables high-speed, high-precision acquisition and transmission of data from multiple ADCs simultaneously sampled. It is applicable to high-speed sampling systems for DTUs and FTUs, meeting the data transmission requirements of at least five ADCs simultaneously sampling at high speed. Furthermore, it allows for the expansion of multiple ADC modules without affecting CPU performance, while significantly reducing the number of CPU interrupts and alleviating CPU load. Attached Figure Description

[0028] Figure 1 The figure shows a schematic diagram of the system architecture of the DMA-based data sampling system of the present invention;

[0029] Figure 2 The diagram shown illustrates the working principle of DMA acquisition and transmission in the data sampling system of this invention.

[0030] Figure 3 The diagram shows the DMA data acquisition process. Detailed Implementation

[0031] The following description, in conjunction with the accompanying drawings and specific embodiments, provides further details.

[0032] Example 1

[0033] This embodiment describes a DMA-based data sampling system, referencing... Figure 1 As shown, the system includes a DMA control unit, a storage unit, a CPU unit, a timer unit, and multiple ADC multi-channel sampling units;

[0034] The timer unit is configured to send a sampling trigger signal to each ADC multi-channel sampling unit at a set time interval. Each ADC multi-channel sampling unit performs data sampling in response to receiving the sampling trigger signal and sends a DMA request signal to the DMA control unit after sampling is completed.

[0035] The DMA control unit is configured to, upon receiving any DMA request signal, sequentially acquire the data sampled by each ADC according to the preset correspondence between source data address and target address, and transmit it to the corresponding target address in the storage unit; when acquiring the data sampled by a single ADC, the data of each channel of the ADC is acquired sequentially to obtain the sampled data of all channels of a single ADC at a single sampling point.

[0036] The DMA control unit is also configured to send an interrupt trigger signal to the CPU unit when the number of sample points acquired by all ADCs reaches a specified first number of sample points, and to send an iteration end signal to the CPU unit when the number of sample points acquired reaches a specified second number of sample points.

[0037] The CPU unit is configured to: in response to receiving the interrupt trigger signal, determine a new set of sampled data for a single protection calculation; in response to receiving the iteration end signal, update the configuration of the correspondence between the source data address and the target address; and perform protection calculation based on the single set of sampled data for protection calculation.

[0038] Figure 1In the illustrated embodiment, the DMA control unit, storage unit, CPU unit, and timer unit are integrated into a sampling processor using the RT1064 microprocessor chip. The ADC multi-channel sampling unit uses the AD7606 chip, with five units, each containing eight sampling channels. The maximum sampling frequency supports 200Ksps, and the input range is ±5V or ±10V. Other models or the AD7616 can also be used for the ADC multi-channel sampling unit to allow for flexible selection and configuration of sampling channels, meeting different operating conditions and user needs.

[0039] In power grids, to meet the requirements of relay protection, real-time sampling and measurement aim to detect faults as soon as possible and enable timely protection actions. Within one cycle of the power grid, the more sampling points and the faster the sampling speed, the better. This embodiment sets 160 sampling points within one cycle and can complete one cycle of sampling within 20ms, performing protection calculations every 80ms, fully meeting the power grid's sampling requirements.

[0040] The system utilizes a DMA module for programming, which allows a large amount of data obtained by the sampling circuit to be transferred from the memory of multiple AD7606 chips to the CPU's internal storage in a timely manner without frequent CPU interrupts, so that the CPU can perform measurement value display and protection calculations in a timely manner.

[0041] In this embodiment, the system first performs system initialization configuration. During this process, the CPU can configure the correspondence between the source and destination addresses for DMA data transfer. After the initialization configuration is completed, the FTM module sends a rising-edge convert signal to each AD7606 sampling circuit every 125µs. Each ADC chip samples eight channels for one sampling point in one cycle of the circuit. The sampled data is stored in the ADC chip's memory. After sampling is completed, the ADC sends a falling-edge busy signal to the XBAR pin of the main control system to request DMA. DMA is triggered as soon as any busy signal is received. At any sampling point, if the DMA control unit fails to acquire sampled data from a certain ADC within a specified time, it proceeds to acquire data from the next ADC; otherwise, the DMA control unit performs data acquisition operation on the next ADC after acquiring a specified length of data from a single ADC. For example, in the case of an 8-channel ADC, if each channel can acquire 2 bytes of data, then for a single ADC, after transmitting 16 bytes of data, the DMA control unit triggers channel switching to enter the data acquisition of the next ADC. This avoids the problem that if one ADC chip malfunctions, all chip data cannot be transmitted.

[0042] After DMA is triggered, the main loop of a certain channel is entered for iteration counting.

[0043] During the main loop of any channel, the DMA transfers the sampled data from the source data address (i.e., the ADC chip's memory) to a specified address in an internal register. The transfer of data between different sampling channels of a single ADC is accomplished through secondary loops. Each completion of a secondary loop transfers data from one sampling channel of the ADC chip, which is 2 bytes of data. After every 8 iterations of the secondary loops (transferring 16 bytes of data), the data transfer for all 8 channels of the ADC chip at that sampling point is complete, triggering a channel transition to the next channel, and incrementing the main loop count for that channel by one.

[0044] For example: if channel 2 needs to iterate 8 times to trigger channel switching, then channel 1 will be entered, and the main loop and secondary loop of channel 1 will begin, transmitting the data of the next 8 channels of the ADC at this sampling point.

[0045] When all ADCs have completed the data transmission of 80 sampling points, the system enters channel 0 and triggers an interrupt. This means that after transmitting data for every 80 sampling points, the CPU performs protection calculations and displays the measured values ​​for those 80 sampling points.

[0046] When all channels have iterated 240 times in the main loop, the CPU will reset the target address for DMA data transfer. This means that the system will only store one and a half cycles, or 240 sample points of data. This avoids the abuse of system memory and ensures that data transfer can be carried out without affecting other CPU performance.

[0047] Regarding the determination of the number of iterations in the main loop of each acquisition and transmission channel, this invention can employ two methods to ensure that the number of iterations in each acquisition and transmission channel reaches the specified number when an interrupt is triggered. One method is as follows: When the DMA control unit acquires data from the same sampling point for all ADCs, after all channel data acquisition for each ADC is completed, it increments the number of sampling points corresponding to the most recently acquired ADC by 1, and then proceeds to acquire data from all channels of the next ADC. This continues until all ADCs at the same sampling point have completed acquisition, at which point it is determined whether the number of sampling points corresponding to all ADCs has reached the specified number of sampling points.

[0048] Secondly, when the DMA control unit is acquiring data from the same sampling point for all ADCs, it proceeds to acquire data from all channels of the next ADC only after all channels of the ADC have been acquired, until all ADCs at the same sampling point have been acquired. Then, it increments the sampling point count by 1 and checks whether the updated sampling point count has reached the specified number of sampling points. In this method, refer to... Figure 2As shown, in the DMA logic, based on the design of acquisition and transmission channels 1-5 for each ADC, an additional acquisition and transmission channel 0 can be added. When the channel is switched to channel 0, no data transfer operation is performed, only the number of sampling points is incremented by 1. Then it can be determined whether the specified number of sampling points has been reached after the sampling point is updated.

[0049] Board-level testing showed that, in actual tests, the sampling system of this embodiment, even with five ADCs simultaneously sampling at a sampling frequency of 125µs, did not affect CPU performance. Compared to the original method of using interrupts for data transmission, CPU usage was significantly reduced. This system allows the CPU to handle other tasks, offering high scalability. Increasing the number of ADC chips or sampling points does not place an additional burden on the CPU. It also facilitates adjustments to sampling accuracy and speed according to customer needs and enables intelligent upgrades to power distribution terminals.

[0050] Example 2

[0051] This embodiment introduces a DMA-based data sampling method, executed by a sampling processor, to acquire and transmit data from multiple ADC multi-channel sampling units; combined with Figure 1 and Figure 3 As shown, taking the RT1064 chip as the sampling processor and the AD7606 chip as the ADC multi-channel sampling unit as an example, the data sampling methods include:

[0052] The sampling processor sends a rising edge convert signal to each ADC at 125µs intervals via the timer FTM module as a sampling trigger signal. In response to receiving the sampling trigger signal, each ADC synchronously samples one sampling point in one cycle of its circuit using eight channels. The sampled data is stored in the memory of the ADC chip. After sampling is completed, the ADC sends a falling edge busy signal to the XBAR pin of the sampling processor as a DMA request.

[0053] The sampling processor receives DMA request signals from the ADC after sampling is complete. If any DMA request signal is received, it triggers... Figure 3 The DMA acquisition and transmission process shown is as follows: the acquisition processor DMA acquires the data sampled by each ADC in sequence according to the preset correspondence between the source data address and the target address, and transmits it to the corresponding target address in memory; when acquiring the data sampled by a single ADC, the data of each channel of the ADC is acquired in sequence to obtain the sampled data of all channels of a single ADC at a single sampling point.

[0054] For all ADCs, when the number of sampling points acquired reaches 80, the DMA will trigger a CPU core interrupt in the acquisition processor. The CPU can clear the interrupt flag in the interrupt and locate the newly acquired set of sampling data for protection calculation by updating the interrupt trigger count. That is, it determines a new set of sampling data for a single protection calculation. When the number of sampling points acquired reaches 240, the CPU updates the configuration of the correspondence between the source data address and the target address used by the DMA to perform data transfer. In subsequent data acquisition, transfer and storage, the new data will overwrite the sampling data of the previous half-cycle stored in the sampling processor's memory, thereby avoiding occupying too much CPU space, greatly reducing the number of interrupts, and not affecting the protection calculation's requirements for data length and retention time.

[0055] During the data acquisition and transmission process of each ADC multi-channel sampling unit, the sampling processor DMA performs protection calculations based on a single set of sampling data used for protection calculations.

[0056] In the above process, the CPU interrupt time triggered by data acquisition and transmission is extremely short, and the number of interrupts is also significantly reduced, which can ensure the normal operation of other CPU functions.

[0057] like Figure 1 In the case where there are 5 ADC chips, in addition to the acquisition and transfer channels 1-5 designed for each ADC, the DMA logic in this embodiment also sets up an acquisition and transfer channel 0, such as... Figure 2 As shown. See also... Figure 3 The flowchart shows that after DMA is triggered, it enters the acquisition and transfer channel 5. The DMA starts the large loop iteration for acquisition in channel 5. During the large loop, a secondary loop iteration is performed. In each iteration, data of one channel of ADC5 at sampling point 1 is transmitted, such as 2 bytes of data. For the case of an 8-channel sampling chip, after 8 secondary loop iterations, the data transmission of the eight channels of ADC5 at sampling point 1 is completed. After DMA detects that 16 bytes of data have been transmitted, it triggers the DMA channel conversion and enters the acquisition and transfer channel 4. At this time, the number of large loop iterations of channel 5 can be incremented by 1.

[0058] After DMA enters channel 4, it performs a large loop iteration of channel 4. During the large loop iteration of channel 4, it performs its corresponding minor loop iteration, which moves the data of one channel of ADC4 at sampling point 1 to the target address. Similarly, the minor loop iteration is performed 8 times. After all channels of ADC4 at sampling point 1 have completed data transmission, it triggers channel conversion to enter channel 3 and records the number of large loop iterations of channel 4 by 1.

[0059] The logic of DMA channels 3, 2, and 1 is the same as that of channels 5 and 4. After one iteration of the large loop of DMA channel 1, it enters channel 0. At this time, all ADCs have completed the data acquisition and transmission at sampling point 1. In channel 0, the number of sampling points is incremented by 1, and no other operations are performed. DMA returns to channel 5 to perform data acquisition and transmission at sampling point 2.

[0060] When the number of sampling points in all channels reaches 80, the DMA enters channel 0 and triggers an interrupt. In the interrupt, the interrupt flag is cleared and the count is incremented by 1. This count plays a positioning role in the protection algorithm program. Subsequently, the CPU core protection algorithm calculates the data of this group of 80 points and performs protection judgment.

[0061] To ensure the normal operation of other CPU functions and to minimize interrupt time, the CPU does not perform any protection calculations during interrupts; all protection procedures are completed synchronously by the CPU during DMA data transfer.

[0062] When each channel's main loop iterates 240 times, the system has already transferred the data from the corresponding ADC of 240 points. The main loop iteration ends, the target address is reset, and at this point, the sampling and data storage of one half-cycle is completed. The data is no longer saved, and the ADC data below will overwrite the data of this half-cycle to avoid occupying too much CPU internal storage space.

[0063] In this embodiment, the determination of the iteration count of the main loop can be set after the DMA enters channel 0 and the sampling point is updated, or it can be recorded by incrementing the corresponding channel large loop iteration count by 1 after each channel large loop iteration. When the channel 5 large loop iterates 240 times, the channel 5 large loop ends. At this time, the channel 4 large loop has not yet ended and needs to be iterated once more. In order to complete the iteration of all channel large loops, an iteration maximum value channel conversion command can be added after each channel. Even if the large loop ends, a channel conversion is still performed to enter the next DMA channel until all channel large loops have iterated 240 times. Then the DMA sends an iteration end signal to the CPU.

[0064] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0065] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0066] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0067] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0068] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A DMA-based data sampling system, characterized by, It includes a DMA control unit, a storage unit, a CPU unit, a timer unit, and multiple ADC multi-channel sampling units; The timer unit is configured to send a sampling trigger signal to each ADC multi-channel sampling unit at a set time interval. Each ADC multi-channel sampling unit performs data sampling in response to receiving the sampling trigger signal and sends a DMA request signal to the DMA control unit after sampling is completed. The DMA control unit is configured to, upon receiving any DMA request signal, sequentially collect the data sampled by each ADC according to the preset correspondence between source data address and target address, and transmit it to the corresponding target address in the storage unit; when collecting the data sampled by a single ADC, sequentially collect the data of each channel of the ADC to obtain the sampled data of all channels of the single ADC at a single sampling point. The DMA control unit is also configured to send an interrupt trigger signal to the CPU unit when the number of sampling points acquired by all ADCs reaches a specified first number of sampling points, and to send an iteration end signal to the CPU unit when the number of sampling points acquired reaches a specified second number of sampling points. The CPU unit is configured to: in response to receiving the interrupt trigger signal, determine a new set of sampled data for a single protection calculation; in response to receiving the iteration end signal, update the configuration of the correspondence between the source data address and the target address; and perform protection calculation based on the single set of sampled data for protection calculation.

2. The DMA-based data sampling system of claim 1, wherein, When the DMA control unit collects data from the same sampling point for all ADCs, it increments the number of sampling points corresponding to the ADC that has just finished collecting data by 1 after all channels of each ADC have been collected. Then it collects data from all channels of the next ADC until all ADCs at the same sampling point have been collected. Finally, it determines whether the number of sampling points corresponding to all ADCs has reached the specified number of first or second sampling points.

3. The DMA-based data sampling system of claim 1, wherein, When the DMA control unit collects data from the same sampling point for all ADCs, it proceeds to collect data from all channels of the next ADC after all channels of each ADC have been collected. This continues until all ADCs at the same sampling point have been collected. Then, it increments the number of sampling points by 1 and determines whether the updated number of sampling points has reached the specified number of the first or second sampling points.

4. The DMA-based data sampling system of claim 1, wherein, The sampling trigger signal sent by each ADC multi-channel sampling unit of the timer unit is a rising edge signal, and the DMA request signal sent by the ADC multi-channel sampling unit to the DMA control unit is a falling edge signal.

5. The DMA-based data sampling system of claim 1, wherein, In response to receiving the interrupt trigger signal, the CPU unit performs the following operations during the interrupt: clearing the interrupt flag and updating the preset count of the protected calculation data group by 1 to mark and locate the latest acquired first set number of sampling data groups.

6. The DMA-based data sampling system of claim 5, wherein, During the data acquisition and transmission process of the DMA control unit, the CPU unit simultaneously performs protection calculation operations using the marked and located sampled data groups.

7. The DMA-based data sampling system of claim 1, wherein If the DMA control unit fails to acquire sampling data from a certain ADC within a specified time at any sampling point, it will acquire data from the next ADC; otherwise, the DMA control unit will acquire data from the next ADC after acquiring a specified length of data from a single ADC.

8. The DMA-based data sampling system of claim 1, wherein, The DMA control unit, storage unit, CPU unit and timer unit are integrated into a sampling processor, or a microprocessor chip of model RT1064 is used; The ADC multi-channel sampling unit consists of 5 units, each with 8 sampling channels; the ADC multi-channel sampling unit uses the AD7606 chip.

9. The DMA-based data sampling system of claim 1, wherein, The set time interval is 125µs, the number of the first sampling points is 80, and the number of the second sampling points is 240.

10. A DMA-based data sampling method, executed by a sampling processor, for data acquisition and transmission from multiple ADC multi-channel sampling units; characterized in that the method... include: A sampling trigger signal is sent to each ADC multi-channel sampling unit at a set time interval, and each ADC multi-channel sampling unit performs data sampling in response to receiving the sampling trigger signal; The system receives DMA request signals sent by the ADC multi-channel sampling unit after sampling is completed. If any DMA request signal is received, the system sequentially collects the data sampled by each ADC according to the preset correspondence between the source data address and the target address, and transmits it to the corresponding target address in memory. When collecting the data sampled by a single ADC, the system sequentially collects the data of each channel of the ADC to obtain all channel sampled data of a single ADC at a single sampling point. For all ADCs, when the number of sampling points acquired reaches the specified first sampling point number, an interrupt is triggered, and a new set of sampling data for a single protection calculation is determined; when the number of sampling points acquired reaches the specified second sampling point number, the correspondence between the source data address and the target address is configured and updated. During the data acquisition and transmission process of each ADC multi-channel sampling unit, protection calculations are performed synchronously based on a single set of sampling data used for protection calculations.

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