Multilayer integrated circuit with enhanced heat dissipation using back-end metal layers

Abstract

In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistive element (MRE) disposed above the first conductive layer and coupled to the first conductive layer through a first via. The MRE is magnetized to produce a first magnetic orientation. The first conductive layer is disposed above a second conductive layer in the circuit and coupled to the second conductive layer through a second via. The circuit also includes a metal fill disposed in a vicinity of the MRE. The metal fill is positioned above the second conductive layer and coupled to the second conductive layer through a third via. The circuit also includes a heat dissipation path resulting from a physical input applied to the first MRE. The heat dissipation path extends through the first via to the third via, the first conductive layer and the second conductive layer, an integrated circuit interconnect, and the metal fill.

Description

BACKGROUND

[0001] Magnetic field sensors are used in a variety of applications including, but not limited to, angle sensors that sense an angle of a direction of a magnetic field, current sensors that sense a magnetic field generated by a current carried by a current-carrying conductor, magnetic switches that sense proximity of a ferromagnetic object, and magnetic field sensors that sense a magnetic field density of a magnetic field.

[0002] Some magnetic field sensors include magnetoresistive (MR) elements, such as giant magnetoresistive (GMR) elements and tunneling magnetoresistive (TMR) elements. In general, GMR elements and TMR elements have a relatively high sensitivity compared to other types of sensing elements, such as Hall effect elements. GMR elements and TMR elements have a moderately good linearity, but within a limited range of magnetic fields. However, even within the limited range of magnetic fields, the linearity of GMR elements or TMR elements can be affected by irregularities caused, for example, by high temperatures during processing of the MR elements (e.g., during manufacturing).

[0003] Reference layers of magnetoresistive arrays can be oriented by heating a lower wafer in the presence of a magnetic field in which the elements in the array are oriented in the same manner. However, in some applications, it is desirable to have different reference orientations on the same die. This can be obtained by locally heating the magnetoresistive elements with a current or a laser pulse. However, the heat generated by this process can degrade the magnetoresistive elements and their interconnects. SUMMARY

[0004] In one aspect, a multilayer integrated circuit includes a first conductive layer, a first magnetoresistive element disposed above a first portion of the first conductive layer and coupled to the first portion by a first via, the first magnetoresistive element magnetized to produce a first magnetic orientation, wherein the first conductive layer is disposed above a second conductive layer in the multilayer integrated circuit, and the first portion of the first conductive layer is coupled to a first portion of the second conductive layer by a second via, a first metal fill disposed proximate to the first portion of the first conductive layer and the first magnetoresistive element, the first metal fill positioned above a second portion of the second conductive layer and coupled to the second portion of the second conductive layer by a third via, and a first heat dissipation path generated by a physical input applied to the first magnetoresistive element, the first heat dissipation path extending through the first via, the first portion of the first conductive layer, the second via, the first integrated circuit interconnect, the first metal fill, the third via, and the second portion of the third conductive layer.

[0005] The integrated circuit can further include one or more of the following features: a second magnetoresistive element disposed above the second portion of the first conductive layer and coupled to the second portion of the first conductive layer by a fourth via, the second magnetoresistive element magnetized to produce a first magnetic orientation; and a first metal jumper interconnect disposed above the first and second magnetoresistive elements, the first metal jumper interconnect coupled to the first magnetoresistive element by a fifth via and to the second magnetoresistive element by a sixth via, wherein the first heat dissipation path further extends through the fifth via, the first metal jumper interconnect, the sixth via, the second magnetoresistive element, the fourth via, and the second portion of the first conductive layer, the first integrated circuit interconnect connecting the first magnetoresistive element to circuitry of the multilayer integrated circuit and the silicon-based substrate, a third magnetoresistive element disposed above the second portion of the first conductive layer and coupled to the second portion of the first conductive layer by a seventh via, the third magnetoresistive element magnetized to produce a second magnetic orientation different from the first magnetic orientation; a second metal filler disposed adjacent to the second portion of the first conductive layer and the third magnetoresistive element, the second metal filler disposed above the second portion of the second conductive layer and coupled to the second portion of the second conductive layer by an eighth via, wherein the second portion of the first conductive layer includes first and second opposing edges, the first metal filler disposed adjacent to the first edge of the second portion of the first conductive layer, and the second metal filler disposed adjacent to the second edge of the second portion of the first conductive layer; and a second heat dissipation path generated by a physical input applied to the third magnetoresistive element, the second heat dissipation path extending through the seventh via, the second portion of the first conductive layer, the second metal filler, the eighth via, and the second portion of the second conductive layer, a fourth magnetoresistive element disposed above a third portion of the first conductive layer and coupled to the third portion of the first conductive layer by a ninth via, the third portion of the first conductive layer disposed above a third portion of the second conductive layer and coupled to the third portion of the second conductive layer by a tenth via; a second metal jumper interconnect disposed above the third and fourth magnetoresistive elements, the second metal jumper interconnect coupled to the third magnetoresistive element by an eleventh via and to the fourth magnetoresistive element by a twelfth via; and a second metal filler disposed between the third and fourth magnetoresistive elements in the first conductive layer.and a third heat dissipation path generated from a physical input applied to the fourth magnetoresistive element, the third heat dissipation path extending through the ninth via, the third portion of the first electrically conductive layer, the tenth via, the second integrated circuit interconnect, the twelfth via, the second metal jumper interconnect, the eleventh via, the third magnetoresistive element, the seventh via, the second portion of the first electrically conductive layer, the second metal filler, the eighth via, and the second portion of the second electrically conductive layer, the second integrated circuit interconnect connecting the fourth magnetoresistive element to a circuit device of the multilayer integrated circuit and a silicon-based substrate, the second portion of the first electrically conductive layer including an interconnect structure interconnecting the second magnetoresistive element to the third magnetoresistive element, the top thermally conductive element coupled to the fourth portion of the first electrically conductive layer, the thermally conductive element disposed above the first metal jumper interconnect; the fourth portion of the first electrically conductive layer disposed above the fourth portion of the second electrically conductive layer and coupled to the fourth portion of the third electrically conductive layer through the thirteenth via, wherein the first heat dissipation path further extends through the second portion of the first electrically conductive layer, the thirteenth via, and the third portion of the second electrically conductive layer, the first heat dissipation path further extending through the top thermally conductive element via the fourth portion of the first electrically conductive layer, the first via includes an intermetallic dielectric, the physical input is one of an electrical current and a laser pulse, the first metal filler includes a thermally conductive element, the first metal filler is one of aluminum and tungsten, the first magnetoresistive element is a tunnel magnetoresistive (TMR) element, the first magnetoresistive element is a giant magnetoresistive (GMR) element, and / or the first heat dissipation path further extends through the circuit layer to the base substrate.

[0006] In another aspect, a method of manufacturing a multilayer integrated circuit includes disposing a first electrically conductive layer; disposing a first magnetoresistive element above a first portion of the first electrically conductive layer and coupling the first magnetoresistive element to the first portion of the first electrically conductive layer through a first via; disposing the first electrically conductive layer above a second electrically conductive layer in the multilayer integrated circuit and coupling the first portion of the first electrically conductive layer to a first portion of the second electrically conductive layer through a second via; disposing a first metal filler in the first electrically conductive layer proximate to the first portion of the first electrically conductive layer and the first magnetoresistive element; coupling the first metal filler to a second portion of the second electrically conductive layer through a third via; and magnetizing the first magnetoresistive element to generate a first magnetic orientation, wherein heat generated from a physical input applied to the first magnetoresistive element is dissipated from the first magnetoresistive element through the first via, the first portion of the first electrically conductive layer, the second via, a first integrated circuit interconnect, the first metal filler, the third via, and the second portion of the second electrically conductive layer.

[0007] A method can further include one or more of the following features: disposing a second magnetoresistive element over the second portion of the first conductive layer and coupling the second magnetoresistive element to the second portion of the first conductive layer through a fourth via; and disposing a first metal cross-over interconnect over the first and second magnetoresistive elements and coupling the first metal cross-over interconnect to the first magnetoresistive element through a fifth via and to the second magnetoresistive element through a sixth via; magnetizing the second magnetoresistive element simultaneously with the first magnetoresistive element, wherein heat generated by a physical input applied to the first magnetoresistive element is further dissipated from the first magnetoresistive element through the fifth via, the first metal cross-over interconnect, the sixth via, the second magnetoresistive element, the fourth via, and the second portion of the first conductive layer, the first integrated circuit interconnect connecting the first magnetoresistive element to the circuitry of the multilayer integrated circuit and the silicon-based substrate, disposing a third magnetoresistive element over the second portion of the first conductive layer and coupling the third magnetoresistive element to the second portion of the first conductive layer through a seventh via; disposing a second metal filler proximate to the second portion of the first conductive layer and the third magnetoresistive element and coupling the second metal filler to the second portion of the second conductive layer through an eighth via; wherein the second portion of the first conductive layer includes first and second opposing edges, the first metal filler is disposed adjacent to the first edge of the second portion of the first conductive layer, and the second metal filler is disposed adjacent to the second edge of the second portion of the first conductive layer; and magnetizing the third magnetoresistive element to produce a second magnetic orientation different from the first magnetic orientation, wherein heat generated by a physical input applied to the third magnetoresistive element is dissipated from the third magnetoresistive element through the seventh via, the second portion of the first conductive layer, the second metal filler, the eighth via, and the second portion of the second conductive layer, disposing a fourth magnetoresistive element over a third portion of the first conductive layer and coupling the fourth magnetoresistive element to the third portion of the first conductive layer through a ninth via; disposing the third portion of the first conductive layer over a third portion of the second conductive layer and coupling the third portion of the first conductive layer to the third portion of the second conductive layer through a tenth via; and disposing a second metal cross-over interconnect over the third and fourth magnetoresistive elements and coupling the second metal cross-over interconnect to the third magnetoresistive element through an eleventh via and to the fourth magnetoresistive element through a twelfth via; wherein the second metal filler is disposed between the third and fourth magnetoresistive elements in the first conductive layer;wherein heat generated by a physical input applied to the fourth magnetoresistive element is dissipated from the fourth magnetoresistive element through the ninth via, the third portion of the first electrically conductive layer, the tenth via, the second integrated circuit interconnect, the twelfth via, the second metal jumper interconnect, the eleventh via, the third magnetoresistive element, the seventh via, the second portion of the first electrically conductive layer, the second metal fill, the eighth via, and the second portion of the second electrically conductive layer, the second integrated circuit interconnect connecting the fourth magnetoresistive element to a circuit device of the multilayer integrated circuit and a silicon-based substrate, the second portion of the first electrically conductive layer comprising an interconnect structure, the method further comprising connecting the second magnetoresistive element to the third magnetoresistive element via the interconnect structure, disposing a top thermally conductive element on the first metal jumper interconnect, and coupling the top thermally conductive element to the fourth portion of the first electrically conductive layer; and disposing the fourth portion of the first electrically conductive layer above the fourth portion of the second electrically conductive layer and coupling the fourth portion of the first electrically conductive layer to the fourth portion of the second electrically conductive layer through the thirteenth via; wherein further heat applied to the first magnetoresistive element and the second magnetoresistive element is dissipated through the fourth portion of the first electrically conductive layer, the thirteenth via, and the fourth portion of the second electrically conductive layer, wherein further the heat applied to the first magnetoresistive element and the second magnetoresistive element is dissipated through the top thermally conductive element via the fourth portion of the first electrically conductive layer, wherein how much heat is dissipated from the first magnetoresistive element depends on a number of electrically conductive layers contained in the multilayer integrated circuit, the number of electrically conductive layers comprising at least the first electrically conductive layer and the second electrically conductive layer, wherein how much heat is dissipated from the first magnetoresistive element depends on: a number and physical location of metal fills, the metal fills comprising the first metal fill; and a number and physical location of integrated circuit interconnects, the integrated circuit interconnects comprising the integrated circuit interconnect, the first via comprising an intermetallic dielectric, the physical input being one of an electrical current and a laser pulse, the first metal fill comprising a thermally conductive element, the first metal fill comprising one of aluminum and tungsten, wherein the first magnetoresistive element is a tunnel magnetoresistive (TMR) element, wherein the first magnetoresistive element is a giant magnetoresistive (GMR) element, and / or the heat generated by the physical input applied to the first magnetoresistive element is further dissipated through the circuit layer to the base substrate. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above-mentioned features can be more fully understood from the following description taken in conjunction with the accompanying drawings. The drawings are helpful in explaining and understanding the disclosed technology. As it is generally impractical or impossible to illustrate every possible embodiment, the drawings provided depict one or more illustrative embodiments. Accordingly, the drawings are not intended to limit the scope of the broad concepts, systems, and technologies described herein. Like numbers in the drawings represent the same elements.

[0009] Figure 1 is a cross-sectional view of a multilayer integrated circuit with enhanced heat dissipation including a magnetoresistive array according to one embodiment;

[0010] Figure 2 is a cross-sectional view of a multilayer integrated circuit including a magnetoresistive array having enhanced heat dissipation according to another embodiment;

[0011] Figure 3 is a perspective view of a multilayer integrated circuit including a magnetoresistive array having enhanced heat dissipation according to another embodiment;

[0012] Figures 4A-4D A process for fabricating a multilayer integrated circuit including a magnetoresistive array having enhanced heat dissipation according to one embodiment is described;

[0013] Figure 5 is a cross-sectional view of a multilayer integrated circuit including a magnetoresistive array having enhanced heat dissipation according to another embodiment; and

[0014] Figure 6 is a cross-sectional view of a multilayer integrated circuit including a magnetoresistive array having enhanced heat dissipation according to yet another embodiment. DETAILED DESCRIPTION

[0015] Techniques to improve heat dissipation characteristics of integrated circuits including magnetoresistive arrays are described herein. Currently, it is challenging to provide a balance between proper magnetization of magnetoresistive elements and effective heat dissipation. Too much heat applied to the circuit, magnetoresistive elements, and surrounding areas can be damaging. On the other hand, too little energy or power applied to the circuit can result in reduced and insufficient magnetization of the magnetoresistive elements. Typical integrated circuits having sensor devices that require magnetization rely on multiple layers of the circuit underneath to provide some heat dissipation. However, not all components of the circuit provide effective heat transfer means. For example, certain circuit layers / components can be formed of non-conductive materials (e.g., silicon dioxide), and the corresponding density of vias connecting these layers together is typically too small to effectively transfer heat away from the heat source.

[0016] In embodiments described herein, heat dissipation characteristics of integrated circuits having sensor elements (e.g., magnetoresistive arrays) employ circuit layers to dissipate heat generated from the magnetization process.

[0017] Reference Figure 1 One embodiment of an integrated circuit 100 generally includes a base substrate 110, a plurality of conductive layers 122, 124, 126, 128, and 129 (collectively referred to herein as "120"), a magnetoresistive array composed of magnetoresistive elements 132A-132D, metal fill 150A and 150B (collectively referred to as "150"), and a variety of interconnects and circuitry devices (not shown) as will be further described herein.

[0018] In various embodiments, the base substrate 110 can be constructed of silicon. Various layers of the integrated circuit are coupled by vias (collectively shown as 170) including interconnects that connect the magnetoresistive array elements to lower circuitry (not shown) of the integrated circuit 100 (e.g., where such circuitry is located in the base substrate 110). In various embodiments, a lower metal layer 129 (e.g., a polysilicon layer) is located directly above the base substrate 110. The polysilicon layer 129 can be connected to the substrate 110 by an interlayer dielectric (ILD) that forms an insulating layer between interconnects in the circuitry.

[0019] In various embodiments, the level of heat dissipation obtained during the magnetization process of the magnetoresistive array depends at least on the number of conductive layers 120 contained in the multilayer integrated circuit, the number and physical location of metal fill (e.g., 150A, 150B), the number and location of interconnect layers 170, the density of vias in the interconnect layers, and other factors, as will now be described.

[0020] As Figure 1 depicted in the depicted embodiment, the multilayer integrated circuit 100 includes a first conductive layer 122 and a first magnetoresistive element 132A disposed above a first portion 122A of the first conductive layer 122 and coupled to the first portion 122A by a first via 140A. In one embodiment, the magnetoresistive element 132A includes a tunneling magnetoresistive (TMR) element.

[0021] The first conductive layer 122 is disposed above a second conductive layer 124 in the multilayer integrated circuit 100, and a first portion 122A of the first conductive layer 122 is coupled to a first portion 124A of the second conductive layer 124 by a second via 140B. In one embodiment, the first portion 124A of the second conductive layer 124 includes a first integrated circuit interconnect that electrically connects the first magnetoresistive element 132A to circuitry located below via layers 122 and 126-129, and in turn to the silicon-based substrate 110 of the multilayer integrated circuit 100. The circuitry can contain a variety of electronic components, such as processors, logic, memory, switches, encoders / decoders, amplifiers, etc.

[0022] In several embodiments, a first metal filler 150A of the first conductive layer 122 is disposed near a first portion 122A of the first conductive layer 122 and a first magnetoresistive element 132A within the first conductive layer 122. The first metal filler may comprise any type of suitable thermally conductive material (e.g., a metal or a composition of different metals). In one embodiment, the metal filler may be disposed on a second conductive layer, close to the magnetoresistive element, and in any available space on the second conductive layer not yet occupied by other components of the circuit 100. The close proximity of the metal filler to the magnetoresistive element provides additional heat sink characteristics.

[0023] like Figure 1 As shown, the first metal filler 150A is located above the second portion 124B of the second conductive layer 124 and is coupled to the second portion 124B through the third via 140C.

[0024] As described above, the magnetoresistive element is magnetized, wherein a physical input is applied to the element to magnetically orient the element in various directions. In one embodiment, the physical input may be either an electric current or a laser pulse.

[0025] Therefore, when the first magnetoresistive element 132A is magnetized to generate a first magnetic orientation, the heat generated by the physical input applied to the first magnetoresistive element 132A is discharged downward from the first magnetoresistive element through the first via 140A, the first portion 122A of the first conductive layer 122, the second via 140B, the first integrated circuit interconnect of the first portion 124A of the second conductive layer 124, the first metal filler 150A, the third via 140C, the second portion 124B of the second conductive layer 124, and the alternating conductive layers 120 and the interconnect layer 170 containing vias to the substrate 110.

[0026] like Figure 1 As shown, the multilayer integrated circuit also includes a second magnetoresistive element 132B, which is disposed above the second portion 122B of the first conductive layer 122 and coupled to the second portion 122B through a fourth via 140D. The second magnetoresistive element may be a tunnel magnetoresistive (TMR) element.

[0027] Figure 1A first metal jumper interconnect 160A is also shown disposed above the first and second magnetoresistive elements 132A and 132B. The first metal jumper interconnect 160A is coupled to the first magnetoresistive element 132A by a fifth via 140E and to the second magnetoresistive element 132B by a sixth via 140F. In one embodiment, the second magnetoresistive element 132B is magnetized simultaneously with the first magnetoresistive element 132A to produce a first magnetic orientation. Thus, the first and second magnetoresistive elements are simultaneously magnetized and oriented in a single direction. However, it will be appreciated that the magnetoresistive elements can be configured to be individually magnetized and oriented in different directions in order to achieve the advantages of the embodiments described herein.

[0028] In one embodiment, heat generated by an input applied to the first magnetoresistive element 132A is further dissipated from the element 132A, for example, through the alternating conductive layer 120 and interconnect layer 170 containing vias, toward the metal jumper interconnect 160A and toward the silicon-based substrate 110. As shown, heat can be dissipated from the first magnetoresistive element 132A through the fifth via 140E, the first metal jumper interconnect 160A, the sixth via 140F, the second magnetoresistive element 132B, the fourth via 140D, and the second portion 122B of the first conductive layer 122. Figure 1

[0029] Figure 1 A third magnetoresistive element 132C is also shown disposed above the second portion 122B of the first conductive layer 122 and coupled to the second portion 122B by a seventh via 140G. Like the first and second magnetoresistive elements, the third magnetoresistive element 132C can be a tunnel magnetoresistive (TMR) element.

[0030] In various embodiments, a second metal filler 150B is disposed proximate the second portion 122B of the first conductive layer 122 and the third magnetoresistive element 132C. The second metal filler includes a thermally conductive element. The second metal filler 150B is disposed above a second portion 124B of the second conductive layer 124 and coupled to the second portion 124B by an eighth via 140H.

[0031] As shown, heat can be dissipated from the third magnetoresistive element 132C through the seventh via 140G, the second portion 124B of the second conductive layer 124, the eighth via 140H, the second metal filler 150B, the second portion 122B of the first conductive layer 122, and the fourth via 140D. Figure 1 ​As shown, the second portion 122B of the first conductive layer 122 includes opposite first and second edges (edges 123A and 123B, respectively). A first metal filler 150A is disposed adjacent the first edge 123A of the second portion 122B of the first conductive layer 122, and a second metal filler 150B is disposed adjacent the second edge 123B of the second portion 122B of the first conductive layer 122. Thus, the close proximity of the first metal filler 150A and the second metal filler 150B provides additional heat dissipation capability with respect to heat evacuation from the magnetoresistive element.

[0032] For example, in Figure 1 In the embodiment shown, heat generated by a physical input applied to the third magnetoresistive element 132C is evacuated from the third magnetoresistive element 132C in a changing direction (e.g., through the seventh via 140G, the second portion 122B of the first conductive layer 122, the second metal filler 150B, the eighth via 140H, the second portion 124B of the second conductive layer 124, down through the alternating conductive layers 120 and via-containing interconnect layer 170 below, toward the silicon-based substrate 110 of the multilayer integrated circuit 100).

[0033] Figure 1 Also shown in the middle is a fourth magnetoresistive element 132D disposed above a third portion 122C of the first conductive layer 122 and coupled to the third portion 122C by a ninth via 140I. The fourth magnetoresistive element can be a tunneling magnetoresistive (TMR) element.

[0034] As shown, the third portion 122C of the first conductive layer 122 is disposed above a third portion 124C of the second conductive layer 124 and coupled to the third portion 124C by a tenth via 140J. The third portion 124C of the second conductive layer 124 includes connecting the fourth magnetoresistive element 132D to the second integrated circuit interconnect of the silicon-based substrate 110 and circuitry of the multilayer integrated circuit 100.

[0035] A second metal jumper interconnect 160B is disposed above the third magnetoresistive element 132C and the fourth magnetoresistive element 132D, respectively, and the second metal jumper interconnect 160B is coupled to the third magnetoresistive element 132B by an eleventh via 140K and to the fourth magnetoresistive element 132D by a twelfth via 140L.

[0036] A second metal filler 150B is disposed between the third magnetoresistive element 132C and the fourth magnetoresistive element 132D in the first conductive layer 122 to provide effective heat dissipation assistance.

[0037] For example, heat generated by physical input applied to the fourth magnetoresistive element 132D is dissipated from the fourth magnetoresistive element 132D (e.g., through the ninth via 1401, the third portion 122C of the first conductive layer 122, the tenth via 140J, the second integrated circuit interconnect of the third portion 124C of the second conductive layer 124, the twelfth via 140L, the second metal cross-over interconnect 160B, the eleventh via 140K, the third magnetoresistive element 132C, the seventh via 140G, the second portion 122B of the first conductive layer 122, the second metal fill 150B, the eighth via 140H, and the second portion 124B of the second conductive layer 124 toward the silicon-based structure 110 of the multilayer integrated circuit.

[0038] Figure 1 Also shown in FIG. 1 is a metal structure 162 and 164 coupled to portions of the layer 122. The metal used for the cross-overs (e.g., 160A) can be a first metal exposed to a heat source and thus can reach a higher temperature than adjacent components in the circuit. However, the metal cross-overs 160A / 160B can be used as electrical cross-overs and thus can not be grounded, which can cause shorting. The two structures 162 and 164 connect the top metal to the substrate to dissipate heat, but do not connect to the magnetoresistive elements (e.g., they can use dummy magnetoresistors or regular via arrays, as shown in Figure 1

[0039] The first conductive layer 122 also includes an interconnect structure interconnecting the second magnetoresistive element 132B and the third magnetoresistive element 132C. As shown in Figure 1 For example, the second portion 122B of the first conductive layer 122 represents an interconnect structure interconnecting the second magnetoresistive element 132B and the third magnetoresistive element 132C, as shown in FIG. 1. As described above, this interconnect structure further enables heat dissipation between circuit elements.

[0040] While Figure 1 the embodiments in FIG. 1 are described as providing two metal fills and four magnetoresistive elements, it will be understood that multiple fills and magnetoresistive elements can be included in the circuit 100. For example, two additional metal fills (shown generally at 150) can also provide the ability to diffuse heat around the circuit elements. The fills and components are shown for purposes of illustration and ease of description only.

[0041] The vias 170 (including vias 140A-140L) can be formed in an intermetal dielectric (IMD) layer (e.g., a material placed between metal layers to isolate them). Non-limiting examples of this material include silicon oxide or silicon nitride.

[0042] ​As noted above, the magnetoresistive element can be a tunnel magnetoresistive element (TMR). The TMR element can include a layer stack (not shown) indicative of, for example, a pillar of a multi-pillar element. Non-limiting examples of these layers can include, for example, a seed layer (e.g., copper nickel (CuN) and the following combination: platinum manganese (PtMn) or iridium manganese (IrMn), cobalt iron (CoFe), magnesium oxide (MgO), and tantalum (Ta), etc.). A cap layer can include, for example, tantalum (Ta). It will be appreciated that the drive current flowing through the TMR element flows through the multiple layers of the stack / pillar, thereby flowing between the seed layer and the cap layer, i.e., perpendicular to the surface of the bottom electrode.

[0043] As Figure 1 shown, two non-connecting elements 190 and 195 are provided to indicate that the addition of this heat spreading structure is compatible with other metal lines located below the magnetoresistive element. These metal lines are configured to route electronic circuits on the die, and thus can be used extensively. It would be very limited for electronic design to avoid this from happening when there is a heat spreading structure. Thus, spaces or holes can be provided in these structures to leave the space needed for these lines to pass. However, they are not electrically connected to avoid short circuits from occurring (e.g., due to the alignment of the non-connecting element 199 with the line 195).

[0044] Turning now to Figure 2 a portion of a multilayer integrated circuit 200 having enhanced heat spreading will now be described according to another embodiment. The circuit 200 can include elements similar to those described above with respect to the circuit 100, and will not be further discussed. Figure 1 described above with respect to the circuit 100.

[0045] The circuit 200 includes a base substrate 210, a plurality of conductive layers 220 (layers 222, 224, 226, 228, and 229), a magnetoresistive array composed of magnetoresistive elements 232A-232C, metal fill 250A and 250B (collectively referred to as "250"), and a variety of interconnects (e.g., integrated circuit interconnects 224B) and circuitry (not shown). In various embodiments, the level of heat spreading achieved depends at least on the number of conductive layers included in the multilayer integrated circuit, the number and physical location of the metal fill, and the number and physical location of the interconnects.

[0046] In addition, the circuit 200 includes a top thermally conductive element 205 extending above and over the circuit 200. The thermally conductive element 205 can include any suitable electrically conductive material, such as a metal. In one embodiment, the element 205 is connected all the way down to the substrate 110.

[0047] It is understood that the width or size of the heat-conducting element 205 is small enough that the laser source providing the magnetization process for the magnetoresistive elements 232A-232C is not obstructed by the placement or position of the heat-conducting element 205.

[0048] The top thermally conductive element 205 is coupled to a first portion 222A of the first conductive layer 222. For example... Figure 2 As shown, the top thermally conductive element 205 is disposed above the first metal jumper interconnect 260A. The first conductive layer 222 can be substantially similar to... Figure 1 The first conductive layer 122.

[0049] A first portion 222A of the first conductive layer 222 is disposed above a first portion 224A of the second conductive layer 224 and coupled to the first portion 224A through a via 240A. The second conductive layer 224 can be substantially similar to Figure 1 The second conductive layer 124.

[0050] A first magnetoresistive element 232A and a second magnetoresistive element 232B are disposed above corresponding second portions 222B and third portions 222C of the first conductive layer 222, and are coupled to these portions 222B and 222C through corresponding vias 240B and 240C. Similarly, the second portion 222B is coupled to the second portion 224B of the second conductive layer 224 through a via 240F. The second portion 224B includes integrated circuit interconnects connecting the magnetoresistive elements to the lower circuitry of the circuit 200 and the substrate. The third portion 222C of the first conductive layer 222 includes interconnects connecting the magnetoresistive elements 232B and 232C.

[0051] The first metal filler 250A in the first conductive layer 222 is coupled to the third portion 224C of the second conductive layer 224 through the via 240D, and the second metal filler 250B in the first conductive layer 222 is coupled to the fourth portion 224D of the second conductive layer 224 through the via 240E.

[0052] When heat is applied to the first magnetoresistive element and the second magnetoresistive element, the heat is discharged to the substrate 210 through vias 240B and 240C, the second portion 222B and the third portion 222C of the first conductive layer 222, via 240F, the second portion 224B of the second conductive layer 224, metal fillers 250A and 250B, vias 240D and 240E, the corresponding third portion 224C and the fourth portion 224D of the second conductive layer 224, and through one or more layers 226, 228, and 229.

[0053] Further, heat can be diffused through the third portion 222C of the first conductive layer, where the third portion 222C, which acts as an interconnect between the magnetoresistive elements 232B and 232C, transfers heat through the third magnetoresistive element 232C (via the via 240G and the metal cross-over interconnect 260B and the via 240H).

[0054] Further, heat can also be diffused through the first portion 224A of the second conductive layer 224, the via 240A, the first portion 222A of the first conductive layer, and the top thermally conductive element 205.

[0055] Turning now to Figure 3 , a perspective view of a multilayer integrated circuit 300 with enhanced heat dissipation is shown. Figure 3 The integrated circuit 300 can have a similar layout as the embodiment shown in Figure 1 . The circuit 300 includes a top thermally conductive element 305, which is further described in Figure 2 (e.g., the thermally conductive element 205), and the placement of the integrated circuit interconnects (e.g., 324 and 325) within the multiple layers of the circuit 300 also differs. Heat diffusion between the components of the circuit 300 can be achieved in a similar manner as described above in Figure 1 and Figure 2 .

[0056] Turning now to Figures 4A-4D , flowcharts 400A-400D for fabricating a multilayer integrated circuit according to any of the embodiments in Figures 1-3 will now be described. The circuit includes a silicon-based substrate and multiple conductive layers that can be disposed on the circuit. In Figure 4A , the process 400A constructs a multilayer integrated circuit having a first magnetoresistive element, a first metal fill, and a first integrated circuit interconnect configured to enhance heat dissipation caused by magnetization of the magnetoresistive element. In block 402, the process 400A includes disposing a first conductive layer for the multilayer integrated circuit. In block 404, the process 400A disposes a first magnetoresistive element over a first portion of the first conductive layer and couples the first magnetoresistive element to the first portion of the first conductive layer through a first via.

[0057] In block 406, the process 400A includes disposing a first conductive layer over a second conductive layer in the multilayer integrated circuit and coupling a first portion of the first conductive layer to a first portion of the second conductive layer through a second via. The first portion of the second conductive layer includes a first integrated circuit interconnect that connects the first magnetoresistive element to a silicon-based substrate of the multilayer integrated circuit and a circuit device.

[0058] In block 408, process 400A includes disposing a first metal filler proximate the first portion of the first conductive layer and the first magnetoresistive element. In block 410, process 400A includes coupling the first metal filler to a second portion of the second conductive layer through a third via.

[0059] In block 412, process 400A includes magnetizing the first magnetoresistive element to produce a first magnetic orientation. In this configuration, heat generated by a physical input applied to the first magnetoresistive element is dissipated from the first magnetoresistive element (e.g., through the first via, the first portion of the first conductive layer, the second via, the first portion of the second conductive layer, the first integrated circuit interconnect, the first metal filler, the third via, and the second portion of the second conductive layer toward the silicon-based substrate of the multilayer integrated circuit).

[0060] In Figure 4B In process 400B, process 400B adds a second magnetoresistive element and a metal jumper wire configured to further enhance heat dissipation caused by magnetization of the magnetoresistive elements. In block 414, process 400B includes disposing a second magnetoresistive element over a second portion of the first conductive layer and coupling the second magnetoresistive element to the second portion of the first conductive layer through a fourth via.

[0061] In block 416, process 400B includes disposing a first metal jumper interconnect over the first magnetoresistive element and the second magnetoresistive element and, in block 418, coupling the first metal jumper interconnect to the first magnetoresistive element through a fifth via and to the second magnetoresistive element through a sixth via.

[0062] In block 420, process 400B includes magnetizing the second magnetoresistive element simultaneously with the first magnetoresistive element.

[0063] In this configuration, heat generated by an input applied to the first magnetoresistive element is further dissipated from the first magnetoresistive element (e.g., through the fifth via, the first metal jumper interconnect, the sixth via, the second magnetoresistive element, the fourth via, and the second portion of the first conductive layer toward the silicon-based substrate of the multilayer integrated circuit).

[0064] In Figure 4C In process 400C, process 400C adds a third magnetoresistive element and a second metal filler to the multilayer integrated circuit to further enhance heat dissipation caused by magnetization of the magnetoresistive elements.

[0065] In block 422, process 400C includes disposing a third magnetoresistive element over the second portion of the first conductive layer and coupling the third magnetoresistive element to the second portion of the first conductive layer through a seventh via.

[0066] In block 424, process 400C includes, in block 426, disposing a second metal fill adjacent to a second portion of the first conductive layer and the third magnetoresistive element, and coupling the second material fill to the second portion of the second conductive layer through an eighth via. The second portion of the first conductive layer includes opposite first and second edges. The first metal fill is disposed adjacent to the first edge of the second portion of the first conductive layer, and the second metal fill is disposed adjacent to the second edge of the second portion of the first conductive layer.

[0067] In block 428, process 400C includes magnetizing the third magnetoresistive element to produce a second magnetic orientation different from the first magnetic orientation (from block 412). Figure 4A

[0068] In this configuration, heat generated by a physical input applied to the third magnetoresistive element is dissipated from the third magnetoresistive element (e.g., through the seventh via, the second portion of the first conductive layer, the second metal fill, the eighth via, and the second portion of the second conductive layer toward the silicon-based substrate of the multilayer integrated circuit).

[0069] In block 430, process 400D includes disposing a fourth magnetoresistive element over a third portion of the first conductive layer, and coupling the fourth magnetoresistive element to the third portion of the first conductive layer through a ninth via. Figure 4D In block 432, process 400D includes disposing the third portion of the first conductive layer over a third portion of the second conductive layer, and coupling the third portion of the first conductive layer to the third portion of the second conductive layer through a tenth via. The third portion of the second conductive layer includes a second integrated circuit interconnect connecting the fourth magnetoresistive element to the silicon-based substrate and circuitry of the multilayer integrated circuit.

[0070] In block 434, process 400D includes disposing a second metal jumper interconnect over the third and fourth magnetoresistive elements, coupling the second metal jumper interconnect to the third magnetoresistive element through an eleventh via and to the fourth magnetoresistive element through a twelfth via. In embodiments, the second metal fill is disposed between the third and fourth magnetoresistive elements in the first conductive layer.

[0071]

[0072] ​​In this configuration, heat generated by physical inputs applied to the fourth magnetoresistive element is dissipated from the fourth magnetoresistive element (e.g., through the ninth via, the third portion of the first conductive layer, the tenth via, the second integrated circuit interconnect of the third portion of the second conductive layer, the twelfth via, the second metal jumper interconnect, the eleventh via, the third magnetoresistive element, the seventh via, the second portion of the first conductive layer, the second metal fill, the eighth via, and the second portion of the second conductive layer toward the silicon-based structure of the multilayer integrated circuit.

[0073] As noted above with respect to Figure 2 , the multilayer integrated circuit can also include a top thermally conductive element (e.g., a top metal) that is coupled to the first conductive layer and can also provide heat dissipation properties during the magnetization process of the magnetoresistive elements.

[0074] Turning now to Figure 5 , a cross-sectional view of a multilayer integrated circuit 500 including a magnetoresistive array with enhanced heat dissipation according to another embodiment will now be described. In Figure 5 the illustrated embodiment, the magnetoresistive elements are giant magnetoresistive elements (GMR). Referring to Figure 5 , one embodiment of the integrated circuit 500 generally includes a base substrate 510, a plurality of conductive layers 522, 524, 526, 528, and 529 (which are collectively referred to herein as "520"), magnetoresistive elements 531, metal fill 550A-500C (collectively referred to as "550"), and a variety of interconnects and circuitry (not shown) as will be further described herein.

[0075] In various embodiments, the base substrate 510 can be constructed of silicon. The various layers of the integrated circuit are coupled by vias (collectively shown as 570) that include interconnects that connect the magnetoresistive array elements to lower layer circuitry (not shown) of the integrated circuit 500 (e.g., where such circuitry is located in the base substrate 510). In various embodiments, a lower metal layer 529 (e.g., a polysilicon layer) is located directly above the base substrate 510. The polysilicon layer 529 can be connected to the substrate 510 by an interlayer dielectric (ILD) that forms an insulating layer between the interconnects in the circuit.

[0076] In various embodiments, the level of heat dissipation obtained during the magnetization process of the magnetoresistive array depends at least on the number of conductive layers 520 included in the multilayer integrated circuit, the number and physical location of the metal fill (e.g., 550A-550C), the number and physical location of the interconnect layers 570, the via density in the interconnect layers, and other factors as will now be described.

[0077] As Figure 5As shown in the embodiments depicted, the multilayer integrated circuit 500 includes a first conductive layer 522 and a magnetoresistive element 531. The magnetoresistive element is disposed above a first portion 522A and a second portion 522B of the first conductive layer 520 and coupled to the first portion 522A and the second portion 522B through vias 540A and 540E. Figure 5 In the embodiment shown, the magnetoresistive element 531 includes a giant magnetoresistive (GMR) element.

[0078] A first conductive layer 522 is disposed above a second conductive layer 524 in a multilayer integrated circuit 500, and a first portion 522A of the first conductive layer 522 is coupled to a first portion 524A of the second conductive layer 524 through a second via 540B. In one embodiment, the first portion 524A of the second conductive layer 524 includes a first integrated circuit interconnect that electrically connects a magnetoresistive element 531 to a circuit device located below via layers 522 and 526-529, and further electrically connects to the silicon substrate 510 of the multilayer integrated circuit 500. The circuit device may include various electronic components, such as processors, logic, memory, switches, encoders / decoders, amplifiers, etc.

[0079] In several embodiments, a first metal filler 550A of the first conductive layer 522 is disposed near a first portion 522A of the first conductive layer 520 and the magnetoresistive element 531. The first metal filler 550A may comprise any type of suitable thermally conductive material (e.g., a metal or a compound composed of different metals). In one embodiment, the metal filler may be disposed on the second conductive layer near the magnetoresistive element, and in any available space on the second conductive layer not yet occupied by other components of the circuit 500. The close proximity of the metal filler to the magnetoresistive element enables additional heat sink characteristics.

[0080] like Figure 5 As shown, a first metal filler 550A is disposed above a second portion 524B of a second conductive layer 524 and is coupled to the second portion 524B through a third via 540C.

[0081] The second metal filler 550B is disposed near the first conductive portion 522A in the first conductive layer 522. For example... Figure 5 As shown, a first metal filler 550A is disposed near one end of the first conductive portion 522A, and a second metal filler 550B is shown located near the opposite end of the conductive portion 522B on the first conductive layer 522. The second metal filler 550B is coupled to the third conductive portion 524C of the second conductive layer 524 through a fourth via 540D.

[0082] As described above, the magnetoresistive elements are magnetized, where a physical input is applied to the elements in order to magnetically orient the elements in multiple directions. In one embodiment, the physical input can be one of an electrical current or a laser pulse.

[0083] Accordingly, the magnetoresistive element 531 is magnetized to produce a first magnetic orientation. The elements 532A, 532B can smooth the connection between the via 540A, 550E and the GMR element 531. During magnetization, heat generated by the physical input applied to the magnetoresistive element 531 is drained from the first magnetoresistive element down through the first via 540A, the first portion 522A of the first conductive layer 522, the second via 540B, the first portion 524A of the second conductive layer 524, the first integrated circuit interconnect, the first metal fill 550A, the third via 540C, the second portion 524B of the second conductive layer 524, and the alternating conductive layers 520 and via-containing interconnect layers 570 to the substrate 510. Further, the heat generated by the physical input applied to the magnetoresistive element 531 is further drained through the second metal fill 550B, the fourth via 540D, the third portion 524C of the second conductive layer 524, and the alternating conductive layers 520 and via-containing interconnect layers 570 to the substrate 510. Further, the heat applied to the magnetoresistive element 531 can dissipate, as will be further described herein.

[0084] The second portion 522B is disposed over and coupled to a second integrated circuit interconnect of the fourth portion 524D of the second conductive layer 524. The second integrated circuit interconnect electrically connects the magnetoresistive element 531 to circuitry located below the layers 522 and 526-529, and in turn to the silicon-based substrate 510. The second portion 522B of the first conductive layer is coupled to the fourth portion 524D of the second conductive layer through the sixth via 540F.

[0085] Unlike the TMR embodiment of Figures 1-3 GMR 531 includes a metallic material that does not have an insulating barrier requiring a lateral; thus, no contact / via is needed above GMR 531 (current applied with respect to the GMR array flows through the plane).

[0086] In various embodiments, a third metal fill 550C is disposed proximate to the second portion 522B of the first conductive layer 522 and the element 532B. The second metal fill includes a thermally conductive element. The third metal fill 550C is disposed over and coupled to a fifth portion 524E of the second conductive layer 524 through a seventh via 540G.

[0087] The heat generated by the physical input applied to the magnetoresistive element 531 is discharged in different directions (e.g., through the fifth via 540E, the second portion 522B of the first conductive layer 522, the sixth via 540F, the integrated circuit interconnect of the fourth portion of the second conductive layer 524, the third metal filler 550C, the seventh via 540G, the fifth portion 524B of the second conductive layer 524, downward toward the silicon substrate 510 of the multilayer integrated circuit 500, through the alternating conductive layers 520 and the interconnect layer 570 containing vias).

[0088] Vias 570 (including vias 540A-540G) may be formed in an intermetallic dielectric (IMD) layer (e.g., a material placed between metal layers to isolate them). Non-limiting examples of such materials include silicon oxide or silicon nitride.

[0089] like Figure 5 As shown, two non-connecting elements 590 and 595 are provided to demonstrate compatibility of the added heat dissipation structure with other metal lines located below the magnetoresistive element. These metal lines are configured to route electronic circuitry on the die and are therefore widely applicable. Avoiding this situation when a heat dissipation structure is present would be very limiting for electronic design. Therefore, spaces or holes can be provided in these structures to allow the necessary space for these lines to pass through. However, they are not electrically connected to avoid short circuits (e.g., because non-connecting element 599 is aligned with line 595).

[0090] Now go to Figure 6 A portion of a multilayer integrated circuit 600 with enhanced heat dissipation according to another embodiment will now be described. This circuit 600 may include components similar to those described above. Figure 5 The components described in circuit 500 are similar to those in the circuit and will not be discussed further.

[0091] Circuit 600 includes a substrate 610, multiple conductive layers 620 (layers 622, 624, 626, 628, and 629), a magnetoresistive element 631 and smoothing elements 632A-632B, metal filler 650, and various interconnects (e.g., integrated circuit interconnect 224B) and circuit arrangements (not shown). The magnetoresistive element 631 may include a GMR element. In various embodiments, the achieved level of heat dissipation depends at least on the number of conductive layers, the number and physical location of the metal filler, and the number and physical location of the interconnects included in the multilayer integrated circuit.

[0092] Furthermore, circuit 600 includes a top thermally conductive element 605 extending above and across circuit 600. Thermally conductive element 605 may comprise any suitable conductive material, such as a metal. In one embodiment, element 605 is connected downwards to substrate 610.

[0093] It is appreciated that the width or size of the thermally conductive element 605 is small enough such that the placement or location of the thermally conductive element 605 does not obstruct the provision of the magnetization process to the magnetoresistive element 631 by the laser source.

[0094] The top thermally conductive element 605 is coupled to the first portion 624A of the second conductive layer 624. The first portion 622A of the first conductive layer 622 is disposed above the second portion 624B of the second conductive layer 624 and is coupled to the second portion 624B by the first via 640A.

[0095] The magnetoresistive element 631 is disposed above the respective first and second portions 622A and 622B of the first conductive layer 622 and is coupled to the respective first and second portions 622A and 622B by the respective vias 640B and 640C. The second portion 624B includes an integrated circuit interconnect that connects the magnetoresistive element to the underlying circuitry of the circuit 600 and the base substrate. The second portion 622B is coupled to the fourth portion 624D of the second conductive layer by the fourth via 640D. The first and second portions 622A and 622B of the first conductive layer 622 include interconnects.

[0096] The metal fill 650 in the first conductive layer 622 is coupled to the third portion 624C of the second conductive layer 624 by the fifth via 640E.

[0097] When heat is applied to the first and second magnetoresistive elements, the heat is dissipated downward through the vias 640B and 640C, the first and second portions 622A and 622B of the first conductive layer 622, the vias 640A, 640D, the second and fourth portions 624B and 624D of the second conductive layer 624, the metal fill 650, the via 640, the third portion 624C of the second conductive layer 624, through the underlying alternating conductive layer 620 and interconnect layer 670 containing vias.

[0098] Elements of different embodiments described herein can be combined to form further embodiments not specifically set forth herein. In the context of a single embodiment, various elements thereof can also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

Claims

1. A multilayer integrated circuit, comprising: First conductive layer; A first magnetoresistive element is disposed above a first portion of the first conductive layer and coupled to the first portion of the first conductive layer through a first via. The first magnetoresistive element is magnetized to generate a first magnetic orientation. The first conductive layer is disposed above a second conductive layer in the multilayer integrated circuit, and the first portion of the first conductive layer is coupled to the first portion of the second conductive layer through a second via. A second magnetoresistive element is disposed above a second portion of the first conductive layer and coupled to the second portion of the first conductive layer through a fourth via. The second magnetoresistive element is magnetized to generate the first magnetic orientation. A third magnetoresistive element is disposed above the second portion of the first conductive layer and coupled to the second portion of the first conductive layer through a seventh via. The third magnetoresistive element is magnetized to produce a second magnetic orientation different from the first magnetic orientation. A first metal jumper interconnect is disposed above the first magnetoresistive element and the second magnetoresistive element. The first metal jumper interconnect is coupled to the first magnetoresistive element through a fifth through hole and to the second magnetoresistive element through a sixth through hole. A first metal filler is disposed near the first portion of the first conductive layer and the first magnetoresistive element, and the first metal filler is disposed above the second portion of the second conductive layer and coupled to the second portion of the second conductive layer through a third via. The second metal filler is disposed near the second portion of the first conductive layer and the third magnetoresistive element. The second metal filler is disposed above the second portion of the second conductive layer and coupled to the second portion of the second conductive layer through the eighth through-hole. Wherein, the second portion of the first conductive layer includes opposite first and second edges, the first metal filler is disposed adjacent to the first edge of the second portion of the first conductive layer, and the second metal filler is disposed adjacent to the second edge of the second portion of the first conductive layer; A first heat dissipation path generated by the physical input applied to the first magnetoresistive element, the first heat dissipation path extending through the first via, the first portion of the first conductive layer, the second via, the first integrated circuit interconnect, the first metal filler, the third via, the second portion of the second conductive layer, the fifth via, the first metal jumper interconnect, the sixth via, the second magnetoresistive element, the fourth via, and the second portion of the first conductive layer; and A second heat dissipation path is generated by the physical input applied to the third magnetoresistive element, the second heat dissipation path extending through the seventh via, the second portion of the first conductive layer, the second metal filler, the eighth via, and the second portion of the second conductive layer.

2. The multilayer integrated circuit as described in claim 1, wherein, The first integrated circuit interconnect connects the first magnetoresistive element to the silicon substrate and circuit arrangement of the multilayer integrated circuit.

3. The multilayer integrated circuit as described in claim 1, wherein, The multilayer integrated circuit also includes: A fourth magnetoresistive element is disposed above the third portion of the first conductive layer and coupled to the third portion of the first conductive layer through a ninth through-hole. The third portion of the first conductive layer is disposed above the third portion of the second conductive layer and coupled to the third portion of the second conductive layer through a tenth through-hole. A second metal jumper interconnect is disposed above the third and fourth magnetoresistive elements. The second metal jumper interconnect is coupled to the third magnetoresistive element through an eleventh through-hole and to the fourth magnetoresistive element through a twelfth through-hole. The second metal filler is disposed between the third magnetoresistive element and the fourth magnetoresistive element in the first conductive layer; and A third heat dissipation path is generated by the physical input applied to the fourth magnetoresistive element, the third heat dissipation path extending through the ninth via, the third portion of the first conductive layer, the tenth via, the second integrated circuit interconnect, the twelfth via, the second metal jumper interconnect, the eleventh via, the third magnetoresistive element, the seventh via, the second portion of the first conductive layer, the second metal filler, the eighth via, and the second portion of the second conductive layer.

4. The multilayer integrated circuit as described in claim 3, wherein, The second integrated circuit interconnect connects the fourth magnetoresistive element to the silicon substrate and circuitry of the multilayer integrated circuit.

5. The multilayer integrated circuit as described in claim 1, wherein, The second portion of the first conductive layer includes an interconnect structure that interconnects the second magnetoresistive element with the third magnetoresistive element.

6. The multilayer integrated circuit as described in claim 1, wherein, The multilayer integrated circuit also includes: A top thermal conductive element is coupled to a fourth portion of the first conductive layer and is disposed above the first metal jumper interconnect. The fourth portion of the first conductive layer is disposed above the fourth portion of the second conductive layer and is coupled to the fourth portion of the second conductive layer through the thirteenth via. The first heat dissipation path further extends through the fourth portion of the first conductive layer, the thirteenth via, and the fourth portion of the second conductive layer.

7. The multilayer integrated circuit as described in claim 6, wherein, The first heat dissipation path also extends through the top heat-conducting element via the fourth portion of the first conductive layer.

8. The multilayer integrated circuit as claimed in claim 1, wherein, The first through-hole includes an intermetallic dielectric.

9. The multilayer integrated circuit as claimed in claim 1, wherein, The physical input is either electric current or a laser pulse.

10. The multilayer integrated circuit as claimed in claim 1, wherein, The first metal filler includes a thermally conductive element.

11. The multilayer integrated circuit as claimed in claim 1, wherein, The first metal filler includes one of aluminum and tungsten.

12. The multilayer integrated circuit as claimed in claim 1, wherein, The first magnetoresistive element is a tunnel magnetoresistive (TMR) element.

13. The multilayer integrated circuit as claimed in claim 1, wherein, The first magnetoresistive element is a giant magnetoresistive (GMR) element.

14. The multilayer integrated circuit as claimed in claim 1, wherein, The first heat dissipation path extends further through the circuit layer to the substrate.

15. A method for manufacturing a multilayer integrated circuit, the method comprising: Set a first conductive layer; A first magnetoresistive element is disposed above a first portion of the first conductive layer, and the first magnetoresistive element is coupled to the first portion of the first conductive layer through a first via. A second magnetoresistive element is disposed above the second portion of the first conductive layer, and the second magnetoresistive element is coupled to the second portion of the first conductive layer through a fourth through hole; A third magnetoresistive element is disposed above the second portion of the first conductive layer, and the third magnetoresistive element is coupled to the second portion of the first conductive layer through a seventh through hole; The first conductive layer is disposed above the second conductive layer in the multilayer integrated circuit, and the first portion of the first conductive layer is coupled to the first portion of the second conductive layer through a second via. A first metal filler is disposed in the first conductive layer near the first portion of the first conductive layer and the first magnetoresistive element; The first metal filler is coupled to a second portion of the second conductive layer through a third via. A second metal filler is disposed near the second portion of the first conductive layer and the third magnetoresistive element, and the second metal filler is coupled to the second portion of the second conductive layer through an eighth through-hole; Wherein, the second portion of the first conductive layer includes opposite first and second edges, the first metal filler is disposed adjacent to the first edge of the second portion of the first conductive layer, and the second metal filler is disposed adjacent to the second edge of the second portion of the first conductive layer; A first metal jumper interconnect is provided above the first magnetoresistive element and the second magnetoresistive element, and the first metal jumper interconnect is coupled to the first magnetoresistive element through a fifth through hole and to the second magnetoresistive element through a sixth through hole. The first magnetoresistive element is magnetized to produce a first magnetic orientation, the second magnetoresistive element is magnetized simultaneously with the first magnetoresistive element, and the third magnetoresistive element is magnetized to produce a second magnetic orientation different from the first magnetic orientation. The heat generated by the physical input applied to the first magnetoresistive element is discharged from the first magnetoresistive element through the first through-hole, the first portion of the first conductive layer, the second through-hole, the first integrated circuit interconnect, the first metal filler, the third through-hole, the second portion of the second conductive layer, the fifth through-hole, the first metal jumper interconnect, the sixth through-hole, the second magnetoresistive element, the fourth through-hole, and the second portion of the first conductive layer. Heat generated by the physical input applied to the third magnetoresistive element is discharged from the third magnetoresistive element through the seventh through-hole, the second portion of the first conductive layer, the second metal filler, the eighth through-hole, and the second portion of the second conductive layer.

16. The method of claim 15, wherein, The first integrated circuit interconnect connects the first magnetoresistive element to the silicon substrate and circuit arrangement of the multilayer integrated circuit.

17. The method of claim 15, wherein, The method further includes: A fourth magnetoresistive element is disposed above the third portion of the first conductive layer, and the fourth magnetoresistive element is coupled to the third portion of the first conductive layer through a ninth through hole; The third portion of the first conductive layer is disposed above the third portion of the second conductive layer, and the third portion of the first conductive layer is coupled to the third portion of the second conductive layer through a tenth via; and A second metal jumper interconnect is provided above the third magnetoresistive element and the fourth magnetoresistive element, and the second metal jumper interconnect is coupled to the third magnetoresistive element through the eleventh through hole and to the fourth magnetoresistive element through the twelfth through hole; The second metal filler is disposed between the third magnetoresistive element and the fourth magnetoresistive element in the first conductive layer; Heat generated by the physical input applied to the fourth magnetoresistive element is discharged from the fourth magnetoresistive element through the ninth via, the third portion of the first conductive layer, the tenth via, the second integrated circuit interconnect, the twelfth via, the second metal jumper interconnect, the eleventh via, the third magnetoresistive element, the seventh via, the second portion of the first conductive layer, the second metal filler, the eighth via, and the second portion of the second conductive layer.

18. The method of claim 17, wherein, The second integrated circuit interconnect connects the fourth magnetoresistive element to the silicon substrate and circuitry of the multilayer integrated circuit.

19. The method of claim 15, wherein, The second portion of the first conductive layer includes an interconnect structure, and the method further includes connecting the second magnetoresistive element to the third magnetoresistive element via the interconnect structure.

20. The method of claim 15, wherein, The method further includes: A top thermally conductive element is disposed above the first metal jumper interconnect, and the top thermally conductive element is coupled to a fourth portion of the first conductive layer; and The fourth portion of the first conductive layer is disposed above the fourth portion of the second conductive layer, and the fourth portion of the first conductive layer is coupled to the fourth portion of the second conductive layer through the thirteenth via. The heat applied to the first magnetoresistive element and the second magnetoresistive element is further discharged through the fourth portion of the first conductive layer, the thirteenth through-hole, and the fourth portion of the second conductive layer.

21. The method of claim 20, wherein, The heat applied to the first magnetoresistive element and the second magnetoresistive element is further discharged through the fourth portion of the first conductive layer via the top heat-conducting element.

22. The method of claim 15, wherein, The amount of heat emitted from the first magnetoresistive element depends on the number of conductive layers contained in the multilayer integrated circuit, the number of conductive layers including at least the first conductive layer and the second conductive layer.

23. The method of claim 15, wherein, The heat dissipated from the first magnetoresistive element depends on: The quantity and physical location of the metal filler, wherein the metal filler includes the first metal filler; and The number and physical location of integrated circuit interconnects, including integrated circuit connectors.

24. The method of claim 15, wherein, The first through-hole includes an intermetallic dielectric.

25. The method of claim 15, wherein, The physical input is either electric current or a laser pulse.

26. The method of claim 15, wherein, The first metal filler includes a thermally conductive element.

27. The method of claim 15, wherein, The first metal filler includes one of aluminum and tungsten.

28. The method of claim 15, wherein, The first magnetoresistive element is a tunnel magnetoresistive (TMR) element.

29. The method of claim 15, wherein, The first magnetoresistive element is a giant magnetoresistive (GMR) element.

30. The method of claim 15, wherein, The heat generated by the physical input applied to the first magnetoresistive element is further discharged to the substrate through the circuit layer.

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