Method for manufacturing soi wafer and soi wafer

Abstract

The present application is a manufacturing method of an SOI wafer, including: a step of forming a silicon oxide film on the entire surface of a base wafer including a dopant by thermal oxidation; and a step of bonding a main surface of a bonding wafer to a first main surface of the base wafer via the silicon oxide film. Before the step of thermal oxidation, the manufacturing method further includes: a step of forming a CVD insulating film on a second main surface of the base wafer; and a step of forming a barrier silicon layer containing a dopant at a concentration lower than that of the base wafer on the first main surface of the base wafer. In the step of thermal oxidation, the barrier silicon layer is thermally oxidized to obtain a barrier silicon oxide film. In the step of bonding, the bonding wafer and the base wafer are bonded via a portion of the silicon oxide film, i.e., the barrier silicon oxide film. Thus, a manufacturing method of an SOI wafer is provided, which can manufacture an SOI wafer while suppressing contamination of an SOI layer caused by mixing of a dopant of a base wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to a manufacturing method of an SOI wafer and an SOI wafer. BACKGROUND

[0002] As one of wafers for semiconductor elements, there is an SOI (Silicon On Insulator) wafer in which a silicon layer (hereinafter, sometimes referred to as SOI layer) is formed on an insulating film, i.e., a silicon oxide film. Since the SOI layer of the substrate surface layer portion as a device manufacturing region is electrically separated from the inside of the substrate by a buried insulating layer (buried oxide film (BOX layer)), the SOI wafer has characteristics such as a smaller parasitic capacitance, higher radiation resistance, and the like. Therefore, it is expected that the SOI wafer has effects such as realization of operation at high speed and low power consumption, and prevention of software errors, and is promising as a substrate for high-performance semiconductor elements.

[0003] As a representative method of manufacturing the SOI wafer, there are a wafer bonding method or a SIMOX method. The wafer bonding method is, for example, a method in which a thermal oxide film is formed on the surface of at least one of two single crystal silicon wafers, the two wafers are closely bonded via the formed thermal oxide film, and bonding heat treatment is performed to increase the bonding strength, and thereafter, one of the wafers (a wafer for forming an SOI layer (hereinafter, a bonded wafer)) is thinned by mirror polishing or the like, thereby manufacturing an SOI wafer. In addition, as a method of thinning, there are a method of grinding and polishing the bonded wafer to a desired thickness, or a method called ion implantation separation method in which at least one of hydrogen ions or rare gas ions is implanted into the inside of the bonded wafer in advance to form an ion implanted layer, and the bonded wafer is separated using the formed ion implanted layer as a separation surface to obtain a thinned SOI layer.

[0004] On the other hand, the SIMOX method is a method in which oxygen ions are implanted into the inside of a single crystal silicon substrate, and thereafter, high-temperature heat treatment (oxide film formation heat treatment) is performed to cause the implanted oxygen to react with silicon to form a BOX layer, thereby manufacturing an SOI wafer.

[0005] Among the above-described representative two methods, the wafer bonding method has an excellent property that the thickness of the manufactured SOI layer or BOX layer can be freely set, and thus can be applied to various device uses.

[0006] Among them, the ion implantation separation method has extremely excellent film thickness uniformity of the manufactured SOI layer, and thus has been widely used in recent years.

[0007] On the other hand, in order to suppress warpage of the SOI wafer or to improve gettering ability, a substrate wafer doped with high concentration of boron is often used to manufacture the SOI wafer as described in Patent Documents 1 and 2.

[0008] In the case where such a substrate wafer doped with high concentration of boron is applied to the ion implantation and separation method, for example, it is sometimes necessary to form a buried insulating layer having a thickness of 2 μm or more. In this case, if the thick oxide film is formed on the bonding wafer to be bonded, it is necessary to make the ion implantation energy extremely large or the warpage of the manufactured SOI wafer becomes large, and thus it is necessary to form the thick oxide film on the substrate wafer to be bonded.

[0009] At this time, since the thick oxide film is formed by thermal oxidation of the substrate wafer doped with high concentration of boron, a large amount of boron is contained in the thermal oxide film, and as a result, when the thin-film SOI wafer obtained by the ion implantation and separation method is subjected to bonding heat treatment and planarization heat treatment, or high-temperature heat treatment such as epitaxial growth, boron contained in the thermal oxide film on the back surface of the SOI wafer diffuses outward to cause a problem that the dopant contaminates the SOI layer (so-called self-doping). If such self-doping occurs, as a result, the conduction type or the resistivity of the SOI layer changes.

[0010] The same problem occurs due to heat treatment for thickening the SOI layer by epitaxial growth on the SOI layer after thin-film formation, or heat treatment in a device manufacturing process using the SOI wafer, for example, in the case where another thin-film formation method such as grinding or polishing is used.

[0011] In view of such a problem, the present inventors proposed a method for simultaneously reducing the dopant contamination and the warpage of the SOI layer by forming a CVD insulating film on the surface opposite to the bonding surface of the substrate wafer before the thermal oxidation step of the substrate wafer in Patent Document 3.

[0012] However, it was found that even with this method, the dopant contamination of the SOI layer could not be sufficiently suppressed at times.

[0013] Related Art Documents

[0014] Patent Documents

[0015] Patent Document 1: Japanese Patent Application Laid-Open No. 5-226620

[0016] Patent Document 2: Japanese Patent Application Laid-Open No. 8-37286

[0017] Patent Document 3: Japanese Patent Application Laid-Open No. 2008-294045 SUMMARY

[0018] (1) Technical issues to be resolved

[0019] The inventors of this case have repeatedly and carefully studied the causes of the above-mentioned problems of the method described in Patent Document 3, and found that although the dopant contamination of the SOI layer is mainly caused by the outward diffusion from the back oxide film of the base wafer, in addition, it is also caused by solid-phase diffusion from the buried oxide film of the SOI wafer.

[0020] The present invention has been made in view of such problems, and its object is to provide a method for manufacturing an SOI wafer and an SOI wafer, wherein the method can suppress contamination of the SOI layer caused by mixing of dopants contained in a base wafer, and the SOI wafer can suppress contamination of the SOI layer caused by mixing of dopants contained in a base wafer.

[0021] (2) Technical solution

[0022] To achieve the above-mentioned object, the present invention provides a method for manufacturing an SOI wafer, which comprises at least the following steps:

[0023] a preparation step of preparing a base wafer and a bonding wafer, wherein the base wafer is composed of a single crystal silicon wafer containing a dopant throughout the wafer and having a first main surface and a second main surface opposite to the first main surface; and the bonding wafer is composed of a single crystal silicon wafer containing a dopant at a concentration lower than the dopant concentration of the base wafer;

[0024] a thermal oxidation step of forming a silicon oxide film on the entire surface of the base wafer by thermal oxidation;

[0025] a bonding step of bonding one main surface of the bonding wafer to the first main surface of the base wafer via the silicon oxide film on the base wafer; and

[0026] a thin-filming step of thinning the bonded wafer to form an SOI layer;

[0027] It is characterized by:

[0028] Before the thermal oxidation process of the base wafer, the following process is also included:

[0029] forming a CVD insulating film on the second main surface of the base wafer; and

[0030] forming a barrier silicon layer on the first main surface of the base wafer, the barrier silicon layer containing a dopant at a concentration lower than the dopant concentration of the base wafer;

[0031] In the thermal oxidation step, the barrier silicon layer is thermally oxidized to obtain a barrier silicon oxide film as a portion of the silicon oxide film.

[0032] In the bonding step, the one main surface of the bonding wafer is bonded to the first main surface of the base wafer via a portion of the silicon oxide film, i.e., the barrier silicon oxide film.

[0033] In such a manufacturing method of an SOI wafer of the present application, in the bonding step, a CVD insulating film is formed on the second main surface of the base wafer which is on the opposite side from the bonding surface (first main surface) of the bonding wafer, and an SOI wafer in which the first main surface of the base wafer is bonded to the one main surface of the bonding wafer via the barrier silicon oxide film can be obtained. In addition, the barrier silicon oxide film contains a dopant at a concentration lower than that of the base wafer. In such an SOI wafer, in addition to being able to block self-doping from the second main surface of the base wafer toward the bonding wafer by the CVD insulating film, the barrier silicon oxide film can also function as a dopant diffusion prevention layer, and thus self-doping due to solid-phase diffusion from the first main surface of the base wafer toward the bonding wafer can also be suppressed. In addition, in the thermal oxidation step of the base wafer, a silicon oxide film is formed on the entire surface of the base wafer by thermal oxidation, and thus outward diffusion of a dopant from the terrace portion and the edge portion of the base wafer can also be suppressed by this silicon oxide film.

[0034] Thus, according to the manufacturing method of an SOI wafer of the present application, for example, in the bonding step and the step subsequent to this step, the mixing of a dopant contained in the base wafer into the bonding wafer or the SOI layer due to outward diffusion through the silicon oxide film of the back surface, i.e., the second main surface, of the base wafer, or the mixing of a dopant contained in the base wafer into the bonding wafer or the SOI layer due to solid-phase diffusion through the silicon oxide film between the base wafer and the bonding wafer or the SOI layer can be suppressed. In particular, even in a step involving heat treatment, the above-described mixing of a dopant into the SOI layer can be suppressed.

[0035] That is, according to the manufacturing method of an SOI wafer of the present application, an SOI wafer can be manufactured while suppressing contamination of the SOI layer due to the mixing of a dopant contained in the base wafer. In addition, since self-doping can be prevented in this way, situations in which the conductivity type and the resistivity of the SOI layer change can be prevented.

[0036] In addition, in the case of manufacturing a device using an SOI wafer manufactured by the manufacturing method of an SOI wafer of the present application, the mixing of a dopant contained in the base wafer into the SOI layer due to outward diffusion through the silicon oxide film of the back surface, i.e., the second main surface, of the base wafer, or the mixing of a dopant contained in the base wafer into the SOI layer due to solid-phase diffusion from the silicon oxide film which is a buried oxide film of the SOI wafer can also be suppressed.

[0037] In addition, when a device is manufactured using the SOI wafer manufactured by the manufacturing method of the SOI wafer of the present application, since the outward diffusion of the dopant through the second main surface of the base wafer can be suppressed, the dopant contamination of the furnace interior member of the heat treatment furnace can also be sufficiently suppressed, and the effect of suppressing the secondary contamination of the wafer from the furnace interior member can also be obtained.

[0038] In addition, according to the manufacturing method of the SOI wafer of the present application, by using the base wafer containing the dopant, the SOI wafer in which the warpage can be suppressed and excellent gettering effect can be obtained can be manufactured.

[0039] Before the bonding process, a process of forming a silicon oxide film on the entire surface of the bonding wafer can be further included.

[0040] By forming the silicon oxide film on the entire surface of the bonding wafer as such, in the bonding process, the base wafer and the bonding wafer can be bonded via the silicon oxide film disposed on the first main surface of the base wafer and the silicon oxide film disposed on the bonding wafer. By performing the bonding process as such, the mixing of the dopant from the first main surface of the base wafer into the bonding wafer or the SOI layer can be more reliably suppressed.

[0041] Alternatively, in the bonding process, the single-crystal silicon surface of the one main surface of the bonding wafer and the surface of the barrier silicon oxide film of the base wafer can be directly bonded.

[0042] Even in the case where the bonding wafer is not formed with the silicon oxide film, the mixing of the dopant into the SOI layer due to the solid-phase diffusion through the silicon oxide film disposed on the first main surface of the base wafer can be sufficiently suppressed. In this regard, this method is particularly effective in the case where the oxide films cannot be bonded to each other (for example, in the case where the heat treatment at a high temperature (for example, 1150°C or higher) cannot be performed in the bonding process).

[0043] Further, the ion implantation process can further include a process of implanting ions into the bonding wafer, and the ion implantation layer can be formed by the process of implanting ions into the bonding wafer.

[0044] In the thinning process, the bonding wafer is thinned by peeling the bonding wafer using the ion implantation layer as a peeling surface, thereby obtaining the SOI layer.

[0045] By performing the ion implantation process of forming the ion implantation layer as such and using the ion implantation layer in the thinning process, the thinned SOI layer having excellent film thickness uniformity can be obtained.

[0046] For example, in the process of forming the CVD insulating film, any one of a CVD oxide film, a CVD nitride film, and a CVD oxide-nitride film is preferably formed as the CVD insulating film.

[0047] These films not only can be simply formed, but also can be dense CVD insulating films. Therefore, outward diffusion of the dopant through the second main surface of the base wafer opposite to the first main surface can be more reliably suppressed.

[0048] The dopant concentration of 1 x 10 17 atoms / cm 3 The above wafer can be prepared as the base wafer.

[0049] According to the manufacturing method of the SOI wafer of the present application, even if the base wafer having the dopant concentration of 1 x 10 17 atoms / cm 3 above is used, the SOI wafer can be manufactured while suppressing contamination of the SOI layer due to mixing of the dopant contained in the base wafer.

[0050] The dopant concentration of 1 x 10 16 atoms / cm 3 The layer below can be prepared as the barrier silicon layer.

[0051] By forming such a barrier silicon layer, mixing of the dopant into the SOI layer due to solid-phase diffusion through the silicon oxide film disposed on the first main surface of the base wafer can be more reliably suppressed.

[0052] Also, in the thermal oxidation process, the thermal oxidation can be performed in such a manner that a part of the barrier silicon layer remains in an unoxidized state.

[0053] Subsequently, annealing is performed, and in the annealing, the dopant in the base wafer is diffused to the layer of the part of the barrier silicon layer in the unoxidized state.

[0054] In this case, the annealing can be performed to diffuse the dopant to the layer of the part of the barrier silicon layer in the unoxidized state.

[0055] In addition, in the present application, an SOI wafer including a base wafer, a buried oxide film, and an SOI layer attached to the base wafer via the buried oxide film is provided, characterized in that,

[0056] The base wafer is composed of a single crystal silicon wafer containing a dopant throughout the wafer, and has a first main surface which is a bonding surface with the SOI layer, and a second main surface which is on the opposite side of the first main surface,

[0057] A barrier silicon oxide film is provided on the first main surface of the base wafer as at least a part of the buried oxide film,

[0058] A backside silicon oxide film is provided on the second main surface of the base wafer,

[0059] A CVD insulating film is provided on the side of the backside silicon oxide film which is on the opposite side of the base wafer,

[0060] The SOI layer is composed of a single crystal silicon containing a dopant at a concentration lower than the dopant concentration of the base wafer,

[0061] The concentration of the dopant in the barrier silicon oxide film is lower than the concentration of the dopant in the backside silicon oxide film.

[0062] The SOI wafer of the present application contains a barrier silicon oxide film on the bonding surface, i.e., the first main surface, of the base wafer, and the concentration of the dopant in the barrier silicon oxide film is lower than the concentration of the dopant in the backside silicon oxide film. Such a barrier silicon oxide film can prevent the mixing of the dopant from the base wafer into the SOI layer due to solid phase diffusion through the buried oxide film. In addition, by the backside silicon oxide film and the CVD insulating film, the outward diffusion of the dopant through the second main surface of the base wafer on the opposite side of the first main surface can be prevented. As a result, the SOI wafer of the present application can suppress the contamination of the SOI layer due to the mixing of the dopant contained in the base wafer.

[0063] In addition, even in the case where a device is manufactured using the SOI wafer of the present application, the mixing of the dopant contained in the base wafer into the SOI layer due to the outward diffusion through the second main surface, or the mixing of the dopant into the SOI layer due to the solid phase diffusion through the buried oxide film, can be suppressed.

[0064] In addition, in the case where a device is manufactured using the SOI wafer of the present application, since the outward diffusion of the dopant through the second main surface of the base wafer can be suppressed, the dopant contamination of the furnace interior member of a heat treatment furnace can also be sufficiently suppressed, and the effect of suppressing the secondary contamination of the wafer from the furnace interior member can also be obtained.

[0065] In addition, the SOI wafer of the present application, since it contains a base wafer containing a dopant, can suppress warping, and can produce an excellent gettering effect.

[0066] A barrier silicon layer can be provided between the base wafer and the barrier silicon oxide film,

[0067] In the barrier silicon layer, a dopant of the same kind as the dopant contained in the base wafer is diffused.

[0068] Thus, the SOI wafer of the present application can further include a barrier silicon layer between the base wafer and the barrier silicon oxide film.

[0069] (III) Advantageous Effects

[0070] As described above, if it is the manufacturing method of the SOI wafer of the present application, it is possible to manufacture the SOI wafer while suppressing contamination of the SOI layer due to the mixing of the dopant contained in the base wafer. In addition, since it is possible to prevent self-doping like this, it is possible to prevent the case where the conductivity type or the resistivity of the SOI layer changes.

[0071] In addition, by using the SOI wafer manufactured by the manufacturing method of the SOI wafer of the present application to manufacture a device, it is possible to suppress the mixing of the dopant contained in the base wafer into the SOI layer.

[0072] In addition, the SOI wafer manufactured by the manufacturing method of the SOI wafer of the present application can suppress warping and can produce excellent gettering effects.

[0073] In addition, if it is the SOI wafer of the present application, it is possible to suppress contamination of the SOI layer due to the mixing of the dopant contained in the base wafer.

[0074] In addition, in the manufacturing process of a device using the SOI wafer of the present application, it is possible to suppress contamination of the SOI layer due to the mixing of the dopant contained in the base wafer.

[0075] In addition, the SOI wafer of the present application can suppress warping and can produce excellent gettering effects. BRIEF DESCRIPTION OF DRAWINGS

[0076] Figure 1 is a schematic cross-sectional view showing a first example of the SOI wafer of the present application.

[0077] Figure 2 is a schematic cross-sectional view showing a second example of the SOI wafer of the present application.

[0078] Figure 3 is a schematic cross-sectional view showing a third example of the SOI wafer of the present application.

[0079] Figure 4 is a schematic flowchart showing a first example of the manufacturing method of the SOI wafer of the present application.

[0080] Figure 5 is a schematic flowchart showing a second example of the manufacturing method of the SOI wafer of the present application.

[0081] Figure 6 is a graph showing the simulation results in Example 4.

[0082] Figure 7 is a graph showing the simulation results in Example 5. DETAILED DESCRIPTION

[0083] As described above, a manufacturing method of an SOI wafer and an SOI wafer are sought to be developed, which can manufacture an SOI wafer capable of suppressing contamination of an SOI layer caused by mixing of a dopant contained in a base wafer, while suppressing contamination of an SOI layer caused by mixing of a dopant contained in a base wafer.

[0084] The present inventors have repeatedly and carefully studied in view of the above problem, and as a result, have found that, by forming a CVD insulating film on a second main surface of a base wafer, which is opposite to a bonding surface, and forming a barrier silicon layer containing a dopant at a concentration lower than that of the base wafer on a first main surface of the base wafer, before a thermal oxidation process of the base wafer, and then performing the thermal oxidation process of the base wafer, followed by bonding of the base wafer and a bonding wafer, an SOI wafer can be manufactured while suppressing contamination of an SOI layer caused by mixing of a dopant contained in a base wafer, thereby completing the present application.

[0085] That is, the present application relates to a manufacturing method of an SOI wafer, comprising at least the following processes:

[0086] a preparation process of preparing a base wafer and a bonding wafer, the base wafer being composed of a single crystal silicon wafer containing a dopant throughout the wafer and having a first main surface and a second main surface opposite to the first main surface, the bonding wafer being composed of a single crystal silicon wafer containing a dopant at a concentration lower than that of the base wafer;

[0087] a thermal oxidation process of forming a silicon oxide film on the entire surface of the base wafer by thermal oxidation;

[0088] a bonding process of bonding one main surface of the bonding wafer to the first main surface of the base wafer via the silicon oxide film on the base wafer; and

[0089] a thin film process of thinning the bonding wafer to form an SOI layer,

[0090] characterized in that

[0091] the process further comprises the following processes before the thermal oxidation process of the base wafer:

[0092] a process of forming a CVD insulating film on the second main surface of the base wafer; and

[0093] forming a barrier silicon layer containing a dopant at a concentration lower than the dopant concentration of the base wafer on the first main surface of the base wafer,

[0094] thermally oxidizing the barrier silicon layer in the thermal oxidation step to obtain a barrier silicon oxide film as a part of the silicon oxide film,

[0095] bonding the one main surface of the bond wafer to the first main surface of the base wafer via a part of the silicon oxide film, i.e., the barrier silicon oxide film in the bonding step.

[0096] Further, the present application relates to an SOI wafer including a base wafer, a buried oxide film, and an SOI layer bonded to the base wafer via the buried oxide film, characterized in that,

[0097] the base wafer is composed of a single crystal silicon wafer containing a dopant throughout the wafer and having a first main surface to be bonded to the SOI layer and a second main surface opposite to the first main surface,

[0098] a barrier silicon oxide film as at least a part of the buried oxide film is disposed on the first main surface of the base wafer,

[0099] a backside silicon oxide film is disposed on the second main surface of the base wafer,

[0100] a CVD insulating film is disposed on a surface of the backside silicon oxide film opposite to the base wafer,

[0101] the SOI layer is composed of single crystal silicon containing a dopant at a concentration lower than the dopant concentration of the base wafer,

[0102] the concentration of the dopant in the barrier silicon oxide film is lower than the concentration of the dopant in the backside silicon oxide film.

[0103] Hereinafter, the present application will be described in detail with reference to the accompanying drawings, but the present application is not limited thereto. Figure 1 The present application is not limited to the following embodiments.

[0104] <SOI wafer>

[0105] First, an SOI wafer according to the present application will be described.

[0106] The SOI wafer of the present application includes a barrier silicon oxide film on the bonding surface of the base wafer, i.e., the first main surface, and a backside silicon oxide film and a CVD insulating film are provided on the second main surface of the base wafer opposite the first main surface. The dopant concentration in the barrier silicon oxide film is lower than the dopant concentration in the backside silicon oxide film. Such a barrier silicon oxide film prevents the mixing of dopants from the base wafer into the SOI layer due to solid-phase diffusion through the buried oxide film. In addition, the outward diffusion of dopants through the second main surface of the base wafer opposite the first main surface is prevented by the backside silicon oxide film and the CVD insulating film. As a result, the SOI wafer of the present application can suppress the contamination of the SOI layer due to the mixing of dopants contained in the base wafer.

[0107] In addition, in the case of manufacturing a device using the SOI wafer of the present application, the mixing of dopants contained in the base wafer into the SOI layer due to outward diffusion through the second main surface or the mixing of dopants into the SOI layer through solid-phase diffusion in the buried oxide film can be suppressed.

[0108] In addition, in the case of manufacturing a device using the SOI wafer of the present application, the outward diffusion of dopants through the second main surface of the base wafer is suppressed, so the contamination of the interior parts of the heat treatment furnace by dopants can also be sufficiently suppressed, and the effect of suppressing the secondary contamination of the wafer from the interior parts of the furnace can also be obtained.

[0109] In the SOI wafer of the present application, a barrier silicon layer can also be provided between the base wafer and the barrier silicon oxide film. In this case, the same kind of dopants as those contained in the base wafer can also be diffused in the barrier silicon layer.

[0110] Thus, the SOI wafer of the present application can further include a barrier silicon layer between the base wafer and the barrier silicon oxide film. The SOI wafer of the present application can also include other layers.

[0111] The SOI wafer of the present application can be manufactured, for example, by the manufacturing method of the SOI wafer of the present application described later.

[0112] The various components of the SOI wafer of the present application will be described in more detail below.

[0113] (Base wafer)

[0114] The base wafer is composed of a single-crystal silicon wafer containing dopants throughout the wafer. As the dopants, for example, B, Ga, P, Sb, As, etc. can be given. Such a single-crystal silicon wafer can be obtained, for example, by slicing a single-crystal silicon ingot manufactured by the CZ method or the FZ method.

[0115] The dopant concentration of the base wafer is not particularly limited as long as it is higher than the dopant concentration of the SOI layer, but it can be set to, for example, 1 x 10 17 atoms / cm 3 or more. By using a base wafer having a dopant concentration of 1 x 10 17 atoms / cm 3 or more, an excellent gettering effect can be exhibited, and further, warping of the SOI wafer can be suppressed. In addition, for the reasons explained above, in the SOI wafer of the present application, even if a base wafer having a dopant concentration of 1 x 10 17 atoms / cm 3 or more is used, the dopant contained in the base wafer can be suppressed from mixing into the SOI layer.

[0116] In addition, when the dopant of the base wafer is an n-type dopant, since the dopant concentration incorporated into the silicon oxide film when a silicon oxide film is formed on the base wafer by thermal oxidation is lower than that of a p-type dopant, the problem of the dopant contaminating the SOI layer as described above does not occur significantly, but even if it is an n-type, for example, when the dopant concentration of the base wafer is 1 x 10 17 atoms / cm 3 or more, the problem of the dopant contaminating the SOI layer cannot be ignored. However, as described in the previous paragraph, in the SOI wafer of the present application, even if the dopant concentration of the base wafer is such a high concentration, the dopant contained in the base wafer can be suppressed from mixing into the SOI layer.

[0117] The upper limit of the dopant concentration of the base wafer is not particularly limited, but it can be set to be below the solid solubility limit of the dopant with respect to the single crystal silicon. The dopant concentration of the base wafer is preferably 1 x 10 17 atoms / cm 3 or more and 1 x 10 20 atoms / cm 3 or less.

[0118] A barrier silicon oxide film is provided on the first main surface of the base wafer, which is the surface to which the SOI layer is attached. In addition, a backside silicon oxide film is provided on the second main surface, which is the surface opposite to the first main surface. A side surface silicon oxide film can also be provided on the side surface of the base wafer as desired. When a side surface silicon oxide film is provided, the barrier silicon oxide film, the backside silicon oxide film, and the side surface silicon oxide film can constitute a silicon oxide film formed on the entire surface of the base wafer.

[0119] The concentration of the dopant in the barrier silicon oxide film is lower than the concentration of the dopant in the backside silicon oxide film. The concentration of the dopant in the backside silicon oxide film is below the dopant concentration of the base wafer.

[0120] The base wafer can include a portion, i.e., a terrace portion, on the first main surface where the SOI layer is not formed. The barrier silicon oxide film can also be provided on the terrace portion in the first main surface of the base wafer. In this case, the barrier silicon oxide film can block outward diffusion of the dopant through the terrace portion of the first main surface of the base wafer.

[0121] (SOI layer)

[0122] The SOI layer is composed of single-crystal silicon containing a dopant at a concentration lower than the dopant concentration of the base wafer.

[0123] As the dopant, for example, B, Ga, P, Sb, As, etc. can be given. The SOI layer can include the same kind of dopant as that included in the base wafer, or can include a different kind of dopant.

[0124] The dopant concentration of the SOI layer is not particularly limited as long as it is lower than the dopant concentration of the base wafer, but can be appropriately changed depending on the required conductivity type and resistivity of the SOI layer. The dopant concentration of the SOI layer can be set to, for example, 1 x 10 13 atoms / cm 3 The above 1 x 10 16 atoms / cm 3 or less.

[0125] The SOI layer can also include a portion not containing a dopant.

[0126] A silicon oxide film (hereinafter, also referred to as an SOI-side silicon oxide film) can also be provided on the surface of the SOI layer that is bonded to the base wafer, i.e., one main surface.

[0127] (Buried oxide film)

[0128] The buried oxide film is provided between the base wafer and the SOI layer.

[0129] The buried oxide film includes the barrier silicon oxide film described above as at least a part thereof.

[0130] The buried oxide film can also be composed of the barrier silicon oxide film. In this case, in the SOI wafer, the surface of the single-crystal silicon of the SOI layer can be directly bonded to the surface of the barrier silicon oxide film of the base wafer.

[0131] Alternatively, the buried oxide film can include the barrier silicon oxide film and an oxide film different from it. For example, when the SOI-side silicon oxide film is provided on the surface of the SOI layer that is bonded to the base wafer, i.e., one main surface, the SOI-side silicon oxide film can also be a part of the buried oxide film. In this case, in the SOI wafer, the barrier silicon oxide film and the SOI-side silicon oxide film can be directly bonded.

[0132] (CVD insulating film)

[0133] The CVD insulating film is not particularly limited, but examples of the CVD insulating film include a CVD oxide film, a CVD nitride film, and a CVD oxide-nitride film.

[0134] These films not only can be simply formed, but also can be dense CVD insulating films. Therefore, the outward diffusion of the dopant through the second main surface opposite to the first main surface of the base wafer can be more reliably suppressed.

[0135] Next, several specific examples of the SOI wafer of the present application will be described with reference to Figures 1-3 , with reference to the drawings. Note that the SOI wafer of the present application is not limited to the examples described below. Further, the following description will be given only of the arrangement of each component. For details of each component, refer to the above description.

[0136] [First Example]

[0137] Figure 1 is a schematic cross-sectional view showing the first example of the SOI wafer of the present application.

[0138] Figure 1 The SOI wafer 100 of the first example shown in the drawing includes a base wafer 10, a buried oxide film 20, and an SOI layer 30 attached to the base wafer 10 via the buried oxide film 20.

[0139] The base wafer 10 has a first main surface 11, which is the attachment surface of the SOI layer 30, and a second main surface 12 opposite to the first main surface 11.

[0140] A barrier silicon oxide film 21 is arranged on the first main surface 11 of the base wafer 10. In the first example shown in the drawing, the barrier silicon oxide film 21 is arranged on the entire surface of the first main surface 11 of the base wafer 10. Figure 1 In the SOI wafer 100 of the first example shown in the drawing, the buried oxide film 20 is composed of the barrier silicon oxide film 21. Further, in the SOI wafer 100 of the first example shown in the drawing, the SOI layer 30 is attached to the base wafer 10 via the barrier silicon oxide film 21. Figure 1 In the SOI wafer 100 of the first example shown in the drawing, the barrier silicon oxide film 21 is formed also in the portion of the first main surface 11 of the base wafer 10, which does not carry the SOI layer 30, i.e., the terrace portion 14. On the other hand, a backside silicon oxide film 51 is arranged on the second main surface 12 of the base wafer 10. Further, a side surface silicon oxide film 52 is arranged on the side surface (edge portion) 13 of the base wafer 10.

[0141] That is, in the SOI wafer 100 of the first example shown in the drawing, the entire surface of the base wafer 10 is covered with the silicon oxide film 50 composed of the barrier silicon oxide film 21, the backside silicon oxide film 51, and the side surface silicon oxide film 52. Figure 1 Further, in the SOI wafer 100 of the first example shown in the drawing, the SOI layer 30 is attached to the base wafer 10 via the barrier silicon oxide film 21.

[0142] Figure 1 ​In the SOI wafer 100 of the first example shown, a CVD insulating layer 40 is arranged on the surface of the back side silicon oxide film 51 opposite to the base wafer 10 .

[0143] In addition, Figure 1 In the SOI wafer 100 of the first example shown, one main surface 32 of the SOI layer 30 is directly bonded to the barrier silicon oxide film 21 , that is, the surface of the buried oxide film 20 .

[0144] [Second example]

[0145] Figure 2 This is a schematic cross-sectional view showing a second example of the SOI wafer of the present invention.

[0146] Figure 2 The SOI wafer 100 of the second example shown is the same as the SOI wafer 100 of the first example, except that a silicon oxide film (SOI-side silicon oxide film) 22 is formed on a portion of the surface of the SOI layer 30 .

[0147] Specifically, if Figure 2 As shown, an SOI-side silicon oxide film 22 is provided on one main surface 32 of the SOI layer 30 that is bonded to the base wafer 10 .

[0148] In addition, Figure 2 In the second example SOI wafer 100 shown, the SOI-side silicon oxide film 22 disposed on one main surface 32 of the SOI layer 30 and the barrier silicon oxide film 21 disposed on the first main surface 11 of the base wafer 10 are bonded together to form the buried oxide film 20. In other words, the second example SOI wafer 100 includes the barrier silicon oxide film 21 as a portion of the buried oxide film 20 and the SOI-side silicon oxide film 22 as another portion of the buried oxide film 20.

[0149] [Third example]

[0150] Figure 3 This is a schematic cross-sectional view showing a third example of the SOI wafer of the present invention.

[0151] Figure 3 The SOI wafer 100 of the third example shown is the same as the SOI wafer 100 of the first example, except that a barrier silicon layer 60 is disposed between the base wafer 10 and the barrier silicon oxide film 21 .

[0152] <SOI晶圆的制造方法>

[0153] Next, the method for manufacturing an SOI wafer according to the present invention will be described.

[0154] The method for manufacturing an SOI wafer of the present invention comprises at least the following steps:

[0155] a preparation step of preparing a base wafer and a bonding wafer, the base wafer being composed of a single-crystal silicon wafer containing a dopant throughout the wafer and having a first main surface and a second main surface on the opposite side of the first main surface, the bonding wafer being composed of a single-crystal silicon wafer containing a dopant at a concentration lower than that of the base wafer;

[0156] a thermal oxidation step of forming a silicon oxide film on the entire surface of the base wafer by thermal oxidation;

[0157] a bonding step of bonding one main surface of the bonding wafer to the first main surface of the base wafer via the silicon oxide film on the base wafer; and

[0158] a thinning step of thinning the bonding wafer to form an SOI layer,

[0159] characterized in that

[0160] the preparation step further comprises the following steps before the thermal oxidation step of the base wafer:

[0161] a step of forming a CVD insulating film on the second main surface of the base wafer; and

[0162] a step of forming a barrier silicon layer on the first main surface of the base wafer, the barrier silicon layer containing a dopant at a concentration lower than that of the base wafer,

[0163] in the thermal oxidation step, the barrier silicon layer is thermally oxidized to obtain a barrier silicon oxide film as a part of the silicon oxide film,

[0164] in the bonding step, the one main surface of the bonding wafer is bonded to the first main surface of the base wafer via a part of the silicon oxide film, i.e., the barrier silicon oxide film.

[0165] In such a manufacturing method of the SOI wafer of the present application, in the bonding step, a CVD insulating film can be formed on the surface of the base wafer which is opposite to the bonding surface (first main surface) of the bonding wafer, and an SOI wafer in which the first main surface of the base wafer and one main surface of the bonding wafer are bonded via the barrier silicon oxide film can be obtained. Further, the barrier silicon oxide film contains a dopant at a concentration lower than that of the base wafer. In such an SOI wafer, since the barrier silicon oxide film can function as a dopant diffusion preventing layer in addition to blocking self-doping from the second main surface of the base wafer to the bonding wafer through the CVD insulating film, self-doping due to solid-phase diffusion from the first main surface of the base wafer to the bonding wafer can also be suppressed. Further, in the thermal oxidation step of the base wafer, since a silicon oxide film is formed on the entire surface of the base wafer by thermal oxidation, the outward diffusion of the dopant from the flat portion and the edge portion of the base wafer can also be suppressed by the silicon oxide film.

[0166] Thus, according to the manufacturing method of the SOI wafer of the present application, for example, in the bonding step and the steps subsequent to the step, the dopant contained in the base wafer can be suppressed from being mixed into the bonding wafer or the SOI layer due to outward diffusion through the silicon oxide film of the back surface, i.e., the second main surface, of the base wafer, or due to solid-phase diffusion through the silicon oxide film between the base wafer and the bonding wafer or the SOI layer. In particular, in the steps accompanied by heat treatment, the above-mentioned mixing of the dopant into the SOI layer can also be suppressed.

[0167] That is, according to the manufacturing method of the SOI wafer of the present application, an SOI wafer can be manufactured while suppressing contamination of the SOI layer due to the mixing of the dopant contained in the base wafer. Further, since self-doping can be prevented as such, a situation in which the conductivity type or the resistivity of the SOI layer changes can be prevented.

[0168] Further, even in the case where a component is manufactured using the SOI wafer manufactured by the manufacturing method of the SOI wafer of the present application, the dopant contained in the base wafer can be suppressed from being mixed into the SOI layer due to outward diffusion through the silicon oxide film of the back surface, i.e., the second main surface, of the base wafer, or due to solid-phase diffusion through the silicon oxide film which is a buried oxide film from the SOI wafer.

[0169] In addition, in the case where a component is manufactured using the SOI wafer manufactured by the manufacturing method of the SOI wafer of the present application, since outward diffusion of the dopant through the second main surface of the base wafer can be suppressed, dopant contamination of the internal parts of a heat treatment furnace can also be sufficiently suppressed, and the effect of suppressing secondary contamination from the internal parts of the furnace to the wafer can be obtained.

[0170] Further, according to the manufacturing method of the SOI wafer of the present application, warping can be suppressed by using a base wafer containing a dopant, and an SOI wafer that can exhibit an excellent gettering effect can be manufactured.

[0171] Hereinafter, the manufacturing method of the SOI wafer of the present application will be described in further detail.

[0172] The manufacturing method of the SOI wafer of the present application at least includes a preparation step of preparing a base wafer and a bonding wafer, a thermal oxidation step of the base wafer, a bonding step, and a thinning step, and further includes a step of forming a CVD insulating film and a step of forming a barrier silicon layer before the thermal oxidation step of the base wafer.

[0173] The manufacturing method of the SOI wafer of the present application can further include a step of forming a silicon oxide film on the entire surface of the bonding wafer before the bonding step.

[0174] The manufacturing method of the SOI wafer of the present application can further include an ion implantation step before the bonding step, in which at least one ion selected from the group consisting of hydrogen ions and rare gas ions is implanted into the inside of the bonding wafer to form an ion-implanted layer. In this case, in the thinning step, the bonding wafer can be thinned to obtain the SOI layer by peeling the bonding wafer using the ion-implanted layer as a peeling surface.

[0175] The manufacturing method of the SOI wafer of the present application can further include other steps.

[0176] Next, each step of the manufacturing method of the SOI wafer of the present application will be described in further detail.

[0177] (Preparation step of the base wafer and the bonding wafer)

[0178] In this step, a base wafer composed of "a single crystal silicon wafer containing a dopant on the entire wafer and having a first main surface and a second main surface on the opposite side of the first main surface" and a bonding wafer composed of "a single crystal silicon wafer containing a dopant at a concentration lower than the dopant concentration of the base wafer" are prepared.

[0179] As the prepared base wafer, the base wafer described in the description of the SOI wafer of the present application can be given. In particular, by using a base wafer in which the dopant concentration is 1 x 10 17 atoms / cm 3 The above base wafer can exhibit an excellent gettering effect, and further suppress warping of the SOI wafer. Further, according to the reasons described above, in the manufacturing method of the SOI wafer of the present application, even if a base wafer in which the dopant concentration is 1 x 10 17 atoms / cm 3The base wafer described above can also prevent the dopant contained in the base wafer from mixing into the bonded wafer or the SOI layer.

[0180] Although the upper limit of the dopant concentration of the base wafer is not particularly limited as described above, it can be set to be below the solid solubility limit of the dopant with respect to the single crystal silicon. The dopant concentration of the base wafer is preferably 1 x 10 17 atoms / cm 3 The above 1 x 10 20 atoms / cm 3 or less.

[0181] The bonded wafer becomes the SOI layer in the thinning process described later. Therefore, it is preferable to prepare a bonded wafer having the conductivity type and the resistivity required for the SOI layer of the manufactured SOI wafer. Specifically, as the prepared bonded wafer, a bonded wafer composed of "the single crystal silicon of the SOI layer described in the description of the SOI wafer of the present application" can be cited.

[0182] (Formation of silicon oxide film on the entire surface of the bonded wafer)

[0183] In any of the processes, a silicon oxide film is formed on the entire surface of the prepared bonded wafer before the bonding process described later.

[0184] The means of forming the silicon oxide film is not particularly limited, but for example, the surface of the bonded wafer can be thermally oxidized to form the silicon oxide film.

[0185] (Ion implantation process)

[0186] In any of the processes, at least one ion selected from the group consisting of hydrogen ions and rare gas ions is implanted into the interior of the bonded wafer to form an ion-implanted layer.

[0187] The specific means of implanting ions is not particularly limited and can be performed in a known manner.

[0188] (Formation of CVD insulating film process)

[0189] In the process, a CVD insulating film is formed on the second main surface (back surface with respect to the bonding surface (first main surface) of the bonded wafer) of the base wafer.

[0190] For the CVD insulating film, for example, the base wafer can be placed on a susceptor in a CVD furnace with the first main surface of the base wafer facing downward, and deposited and formed on the second main surface, which is the opposite surface, by a CVD method (Chemical Vapor Deposition method).

[0191] In particular, it is preferable to form any one of a CVD oxide film, a CVD nitride film, and a CVD oxide-nitride film as the CVD insulating film.

[0192] These films not only can be simply formed, but also can be dense CVD insulating films. Therefore, the outward diffusion of the dopant through the second main surface of the base wafer opposite to the first main surface can be more reliably suppressed.

[0193] For further details of the effect of forming the CVD insulating film on the second main surface of the base wafer, refer to paragraphs

[0028] to

[0041] of Patent Document 3.

[0194] (Forming a barrier silicon layer)

[0195] In this step, a barrier silicon layer containing a dopant at a concentration lower than that of the base wafer is formed on the first main surface of the base wafer.

[0196] The barrier silicon layer can be formed on the first main surface of the base wafer, for example, by epitaxial growth.

[0197] It is preferable to prepare the barrier silicon layer so that the dopant concentration is 1 x 10 16 atoms / cm 3 The following layer is used as the barrier silicon layer.

[0198] By forming such a barrier silicon layer, the mixing of the dopant into the SOI layer due to the solid-phase diffusion of the silicon oxide film provided on the first main surface of the base wafer can be more reliably suppressed.

[0199] As for the dopant concentration of the barrier silicon layer, it can be set to the extent of inevitable mixing as so-called non-doping. That is, the concentration of the dopant in the barrier silicon layer can be greater than 0. The dopant contained in the barrier silicon layer can be the same kind as that of the base wafer, or can be different.

[0200] The film thickness of the barrier silicon layer is not particularly limited, but can be set to, for example, more than half of the total thickness of the silicon oxide film (buried oxide film) between the SOI layer and the base wafer of the SOI wafer obtained by the manufacturing method of the SOI wafer of the present application. By forming the barrier silicon layer having such a film thickness and making it a barrier silicon oxide film by the thermal oxidation step described later, the mixing due to the solid-phase diffusion of the dopant from the first main surface of the base wafer into the SOI layer obtained by bonding the wafer or thinning the bonded wafer can be more sufficiently suppressed. The film thickness of the barrier silicon oxide film is preferably 400 nm or more, more preferably 500 nm or more, and further preferably 600 nm or more. The film thickness of the barrier silicon oxide film can be set to, for example, 1000 nm or less.

[0201] Furthermore, by increasing the thickness of the barrier silicon layer, it is easier to suppress the diffusion of dopants from the base wafer. However, if the thickness of the buried oxide film (BOX layer) of the SOI wafer is too thick, a layer with a lower dopant concentration will appear directly below the BOX layer. If it is not desired to manufacture such an SOI wafer, as a method to prevent this, it is desirable to make the thickness of the barrier silicon layer thinner, for example, to make it about half the thickness of the buried oxide film of the manufactured SOI wafer. Here, the oxidation ratio of Si / SiO2 = 0.45 (the ratio of the film thickness of the Si layer to the SiO2 layer when the entire Si layer is converted into the SiO2 layer by thermal oxidation) is reduced to about half.

[0202] The SOI wafer manufacturing method of the present invention can manufacture an SOI wafer including a terrace portion, a portion not bearing an SOI layer, on the first main surface of the base wafer. In this case, during the step of forming the barrier silicon layer, a barrier silicon layer can also be formed on the terrace portion of the first main surface of the base wafer. The barrier silicon layer is converted into a barrier silicon oxide film through the thermal oxidation step described later, thereby causing the portion of the barrier silicon layer formed on the terrace portion to also become part of the barrier silicon oxide film. This portion of the barrier silicon oxide film can suppress the outward diffusion of dopants from the terrace portion of the SOI wafer.

[0203] Therefore, in this case, even in a portion of the base wafer where the SOI layer is not formed, that is, a terrace portion, the barrier silicon oxide film can prevent the dopant from entering the SOI layer through the terrace portion.

[0204] In addition, when an SOI wafer including a terrace portion is manufactured using the SOI wafer manufacturing method of the present invention and the SOI wafer is used to manufacture a component, not only the outward diffusion of dopants through the second main surface of the base wafer can be suppressed, but also the outward diffusion of dopants through the silicon oxide film of the terrace portion of the SOI wafer can be suppressed. Therefore, the dopant contamination of the furnace components of the heat treatment furnace can be fully suppressed, and the effect of suppressing secondary contamination from the furnace components to the wafer can be achieved.

[0205] The order of the "CVD insulating film formation step" and the "barrier silicon layer formation step" performed before the base wafer thermal oxidation step is not particularly limited. Furthermore, to reduce bonding defects, the bonding-side surface of the base wafer (i.e., the barrier silicon layer) on which both the CVD insulating film and the barrier silicon layer are formed may be re-polished before the thermal oxidation step.

[0206] (Thermal oxidation process)

[0207] In this process, a silicon oxide film is formed on the entire surface of the base wafer by thermal oxidation. In this process, the barrier silicon layer formed on the first main surface of the base wafer is thermally oxidized to obtain a barrier silicon oxide film as a part of the silicon oxide film formed on the entire surface of the base wafer.

[0208] In this process, the thermal oxidation can be performed in a manner that a part of the barrier silicon layer remains in a non-oxidized state.

[0209] In the thermal oxidation process, if the thermal oxidation is performed in a manner that the barrier silicon layer is not completely oxidized but remains a non-oxidized residual thickness to form a silicon oxide film as at least a part of a buried oxide film (BOX layer), a layer of a part of the barrier silicon layer in a non-oxidized state having a low dopant concentration can be formed directly below the silicon oxide film. In this case, the dopant concentration directly below the silicon oxide film can be supplemented by adding a dopant diffusion heat treatment (annealing) after the thermal oxidation process. The diffusion heat treatment can be supplemented by a combination of heat treatment, or an extension of the heat treatment time, and the like.

[0210] Alternatively, the barrier silicon layer can be entirely thermally oxidized to become a barrier silicon oxide film, and the portion directly below the barrier silicon layer in the base wafer can be further thermally oxidized.

[0211] The degree of thermal oxidation can be adjusted, for example, by the thermal oxidation temperature and time.

[0212] Since the thermal oxidation reaches the base wafer through the CVD insulating film formed on the second main surface of the base wafer, the portion of the base wafer in contact with the CVD insulating film can also become a silicon oxide film (referred to as a backside silicon oxide film) by the thermal oxidation process. Thus, by the thermal oxidation process, the main surface of the base wafer on which the backside silicon oxide film is disposed becomes a new second main surface.

[0213] In the silicon oxide film obtained by the thermal oxidation, the barrier silicon oxide film is formed by thermal oxidation of at least a part of the barrier silicon layer, and the backside silicon oxide film is formed by thermal oxidation of a part of the base wafer. Since the dopant concentration of the barrier silicon layer is lower than the dopant concentration of the base wafer, the dopant concentration of the barrier silicon oxide film is also lower than the concentration of the backside silicon oxide film.

[0214] (Bonding process)

[0215] In this process, one main surface of the bonding wafer is bonded to the first main surface of the base wafer via the silicon oxide film on the base wafer.

[0216] When a silicon oxide film is formed on the entire surface of the bonding wafer before the bonding process, in the bonding process, the base wafer and the bonding wafer can be bonded via the silicon oxide film provided on the first main surface of the base wafer and the silicon oxide film provided on the bonding wafer. In this way, by performing the bonding process, the mixing of the dopant from the first main surface of the base wafer into the bonding wafer or the SOI layer can be more reliably suppressed.

[0217] Alternatively, in the bonding process, the single-crystal silicon surface of one main surface of the bonding wafer can be directly bonded to the surface of the barrier silicon oxide film of the base wafer.

[0218] Even in the case where the bonding wafer is not formed with a silicon oxide film, the mixing of the dopant into the SOI layer due to solid-phase diffusion through the silicon oxide film provided on the first main surface of the base wafer can be sufficiently suppressed. This mode is particularly effective in cases where the oxide films cannot be bonded to each other (for example, in cases where heat treatment at a high temperature cannot be performed in the bonding process).

[0219] (Thin-film formation process)

[0220] In this process, the bonding wafer is thinned to form an SOI layer.

[0221] The means of thinning is not particularly limited and can be performed by grinding, polishing, or etching, but it is preferable to perform thinning by an ion implantation and separation method. In the case of performing the ion implantation and separation method, the ion implantation layer is formed in advance on the bonding wafer by the ion implantation process described above. In addition, by separating the bonding wafer using the ion implantation layer as a separation surface, the bonding wafer can be thinned to obtain an SOI layer.

[0222] If such an ion implantation and separation method is performed, a thinned SOI layer having excellent film thickness uniformity can be obtained.

[0223] After the thin-film formation process, a sacrificial oxidation treatment process, a planarization heat treatment process, a polishing process, a mirror surface treatment process, a cleaning process, or the like can be performed.

[0224] In the manufacturing method of the SOI wafer of the present application, the SOI wafer can be obtained through the thin-film formation process or any process thereafter. In addition, according to the manufacturing method of the SOI wafer of the present application, for example, the SOI wafer of the present application described above can be manufactured.

[0225] Next, several specific examples of the manufacturing method of the SOI wafer of the present application will be described with reference to Figure 4 and Figure 5 In addition, the manufacturing method of the SOI wafer of the present application is not limited to the examples described below.

[0226] [First Example]

[0227] Figure 4 This is a schematic flow chart showing a first example of a method for manufacturing an SOI wafer according to the present invention. Figure 1 The SOI wafer of the first example has been described.

[0228] First, in step (a), a base wafer 10 and a bonding wafer 31 are prepared. The base wafer 10 has: Figure 4 The bonding wafer 31 has a first principal surface 11 facing upward, a second principal surface 12 opposite to the first principal surface 11, and a side surface (edge ​​portion) 13 connecting the first principal surface 11 and the second principal surface 12. The bonding wafer 31 has a principal surface 32 that is subsequently bonded to the first principal surface 11 of the base wafer 10. Both the base wafer 10 and the bonding wafer 31 contain dopants, but the concentration of dopants in the base wafer 10 is higher.

[0229] Next, in step (b), a CVD insulating film 40 is formed on the second main surface 12 of the base wafer 10 prepared in step (a).

[0230] Next, in step (c), a barrier silicon layer 60 is formed on the first main surface 11 of the base wafer 10 . The dopant concentration of the barrier silicon layer 60 is lower than the dopant concentration of the base wafer 10 .

[0231] Next, in step (d), the base wafer 10 is thermally oxidized to obtain a silicon oxide film 50. In this example, in this thermal oxidation step (d), the entire barrier silicon layer 60 becomes the barrier silicon oxide film 21. In addition, the portion including the second main surface 12 of the base wafer 10 also becomes the back oxide film 51, and a new second main surface 12 in contact with the back oxide film 51 is generated in the base wafer 10. In addition, a side silicon oxide film 52 is formed on the side surface 13 of the base wafer 10. The barrier silicon oxide film 21, the back oxide film 51, and the side silicon oxide film 52 form a silicon oxide film 50 that covers the entire surface of the base wafer 10.

[0232] Next, in step (e), one main surface 32 of the bonded wafer 31 prepared in step (a) is bonded to the first main surface 11 of the base wafer 10 thermally oxidized in step (d) via the silicon oxide film 50 , specifically, the barrier silicon oxide film 21 .

[0233] Next, in step (f), the bonded wafer 31 is thinned to obtain the SOI layer 30 .

[0234] Before the bonding step (e), if an ion implantation step is performed to implant at least one ion selected from the group consisting of hydrogen ions and rare gas ions into the bonded wafer 31 to form an ion implantation layer, the thinning step (f) can be performed by ion implantation lift-off.

[0235] By performing the thinning process (f), it is possible to obtain Figure 1 the SOI wafer 100 of the first example shown in FIG. 1.

[0236] In addition, if the degree of thermal oxidation in the thermal oxidation process (d) is made weak, it is possible to obtain Figure 3 the SOI wafer 100 of the third example shown in FIG. 3.

[0237] [Second Example]

[0238] Figure 5 is a schematic flowchart showing a second example of the manufacturing method of the SOI wafer of the present application. According to the manufacturing method of the present example, for example, the SOI wafer of the second example described with reference to FIG. 2 can be manufactured. Figure 2

[0239] The manufacturing method of the second example differs from the manufacturing method of the first example in that it includes a process (g) of forming a silicon oxide film 34 on the entire surface of the bonding wafer 31 prepared in the process (a), including one main surface 32 on the side of the attachment of the base wafer 10, a main surface (back surface) 36 on the opposite side thereof, and a side surface (edge portion) 33 connecting these surfaces.

[0240] The silicon oxide film 34 formed in the process (g) includes an SOI-side silicon oxide film 22 formed on the one main surface 32 of the bonding wafer 31, a back-surface silicon oxide film 37 formed on the main surface 36, and a side-surface silicon oxide film 35 formed on the side surface 33.

[0241] In the manufacturing method of the second example, in the attachment process (e), the base wafer 10 and the bonding wafer 31 are attached via the barrier silicon oxide film 21 and the SOI-side silicon oxide film 22.

[0242] In the manufacturing method of the second example, in the thinning process (f), a portion including the "portion on which the back-surface silicon oxide film 37 is formed" in the bonding wafer 31 is peeled off, and the SOI layer 30 is obtained. By performing such a thinning process (f), it is possible to obtain Figure 2 the SOI wafer 100 of the second example shown in FIG. 4.

[0243] [Measurement Method]

[0244] As for the dopant concentration in the base wafer, the bonding wafer, the barrier silicon layer, the barrier silicon oxide film, the back-surface silicon oxide film, and the like, for example, a secondary ion mass spectrometer (SIMS) can be used for measurement.

[0245] ​As for the thickness of each component included in the SOI wafer, and the thickness of each wafer prepared by the manufacturing method of the SOI wafer and each layer formed thereby, confirmation can be made, for example, by cross-sectional SEM, light reflection method, ellipsometry, or the like.

[0246] Example

[0247] Hereinafter, the present application will be specifically described using examples and comparative examples, but the present application is not limited thereto.

[0248] (Example 1)

[0249] In Example 1, the manufacturing of the SOI wafer 100 was performed in the same procedure as that shown schematically in the flowchart of Fig. 1. Figure 4

[0250] <Process (a)>

[0251] First, a p-type single crystal silicon wafer (resistivity 10 Ωcm) of 300 mm in diameter, boron-doped (dopant concentration 1 x 1019atoms / cm2) was prepared as the bonding wafer 31. In addition, a p-type single crystal silicon wafer (resistivity 0.1 Ωcm) of 300 mm in diameter, boron-doped (dopant concentration 1 x 1019atoms / cm2) was prepared as the base wafer 10. 15 3 17 3

[0252] In addition, from the bonding surface, i.e., one main surface 32 side, the conditions of Table 1 were used to implant hydrogen ions into the interior of the prepared bonding wafer 31, thereby forming an ion-implanted layer.

[0253] <Process (b)>

[0254] Next, the base wafer 10 was placed on the susceptor of the CVD furnace with the bonding surface, i.e., the first main surface 11 facing downward, and a CVD oxide film was formed as the CVD insulating film 40 on the second main surface 12 by the CVD method. The thickness of the formed CVD oxide film was 300 nm.

[0255] <Process (c)>

[0256] Next, the blocking silicon layer 60 was epitaxially grown on the bonding surface, i.e., the first main surface 11 of the base wafer 10. The conductive type of the blocking silicon layer was p-type, the thickness was 400 nm, the resistivity was 10 Ωcm, and the dopant concentration was 1 x 1019atoms / cm2. 15 3

[0257] <Process (d)>

[0258] Next, thermal oxidation was performed on the entire surface of the base wafer 10, thereby forming the silicon oxide film 50 covering the entire surface of the base wafer 10.​​​​​​​

[0259] The thermal oxidation is performed in such a manner that the film thickness of the silicon oxide film 50 becomes 1000 nm. Thus, by this thermal oxidation process (d), the barrier silicon layer 60 is entirely oxidized to become the barrier silicon oxide film 21. In addition, the portion of the base wafer 10 including the second main surface is also oxidized to become the back surface silicon oxide film 51.

[0260] <Process (e)>

[0261] Next, the base wafer 10 on which the thermal oxidation of process (d) has been performed is attached to the bonding wafer 31 on which the ion implantation layer is formed, in such a manner that the barrier silicon oxide film 21 contacts one main surface 32 of the bonding wafer 31.

[0262] <Process (f)>

[0263] The wafer after the attachment is subjected to a separation heat treatment under an argon atmosphere at 500°C for 30 minutes, and the bonding wafer 31 is separated as a separation surface from the ion implantation layer, thereby thinning the bonding wafer 31 to obtain the SOI layer 30.

[0264] Next, in order to remove damage of the SOI layer 30, a sacrificial oxidation process is performed under the conditions shown in Table 1 below. This sacrificial oxidation process also functions as a bonding heat treatment for strengthening the bonding between the wafers. In addition, a planarization heat treatment is performed under the conditions shown in Table 1 below, and the SOI wafer 100 is manufactured.

[0265] (Examples 2, 3, and Comparative Examples 1 to 3)

[0266] The SOI wafers 100 of each example are manufactured under the same conditions as in Example 1, except that the manufacturing conditions are set to the conditions shown in Tables 1 to 3 below, respectively.

[0267] <Evaluation>

[0268] The dopant concentration in the SOI layer 30 of the SOI wafer 100 of each example is measured using SIMS. The results are shown in Tables 1 to 3 below, respectively.

[0269] [Table 1]

[0270]

[0271] [Table 2]

[0272]

[0273] [Table 3]

[0274]

[0275] From a comparison of the results of Example 1 and Comparative Example 1 shown in Table 1, it is understood that the SOI wafer of Example 1 in which the barrier silicon layer and the CVD insulating film are formed can significantly suppress the increase in the boron concentration of the SOI layer due to the mixing of boron from the base wafer, as compared with the SOI wafer of Comparative Example 1 in which neither of the barrier silicon layer and the CVD insulating film is formed. Further, from a comparison of the results of Example 2 and Comparative Example 2 shown in Table 2, it is understood that the SOI wafer of Example 2 in which the barrier silicon layer and the CVD insulating film are formed can significantly suppress the increase in the boron concentration of the SOI layer due to the mixing of boron from the base wafer, as compared with the SOI wafer of Comparative Example 2 in which the CVD insulating film is formed but the barrier silicon layer is not formed. Further, from a comparison of the results of Example 3 and Comparative Example 3 shown in Table 3, it is understood that the SOI wafer of Example 3 in which the barrier silicon layer and the CVD insulating film are formed can significantly suppress the increase in the phosphorus concentration of the SOI layer due to the mixing of phosphorus from the base wafer, as compared with the SOI wafer of Comparative Example 3 in which the CVD insulating film is formed but the barrier silicon layer is not formed.

[0276] (Example 4)

[0277] In Example 4, the relationship between the "thickness of the barrier silicon layer (epitaxial layer)" and the "boron concentration in the SOI layer in the vicinity of the SOI layer / buried oxide film (BOX layer) interface" when the SOI wafer was produced under the same conditions as in Example 2 except that the thickness of the formed barrier silicon layer was changed was simulated. The simulation results calculated from the graph are shown in Table 2. Figure 6 .

[0278] From Table 2, it is understood that if the barrier silicon layer is formed, the increase in the boron concentration of the SOI layer can be significantly suppressed as compared with Comparative Example 2 in which the barrier silicon layer is not formed. Further, from Table 2, it is understood that if the barrier silicon layer of 400 nm is formed, the increase in the boron concentration of the SOI layer can be suppressed to within twice, and further, if the barrier silicon layer is formed to a thickness of 500 nm which is half of the thickness of the buried oxide film to be formed later, the increase in the boron concentration of the SOI layer can be substantially suppressed. Figure 6 Figure 6 From Table 2, it is understood that if the barrier silicon layer is formed, the increase in the boron concentration of the SOI layer can be significantly suppressed as compared with Comparative Example 2 in which the barrier silicon layer is not formed. Further, from Table 2, it is understood that if the barrier silicon layer of 400 nm is formed, the increase in the boron concentration of the SOI layer can be suppressed to within twice, and further, if the barrier silicon layer is formed to a thickness of 500 nm which is half of the thickness of the buried oxide film to be formed later, the increase in the boron concentration of the SOI layer can be substantially suppressed.

[0279] (Example 5)

[0280] In Example 5, the simulation was performed under the same conditions as in Example 4 except that the film thickness of the buried oxide film was set to 2 μm. The simulation results showing the relationship between the "thickness of the barrier silicon layer (epitaxial layer)" and the "boron concentration in the SOI layer in the vicinity of the SOI layer / buried oxide film interface" are shown in Table 3. Figure 7 .

[0281] From Table 3, it is understood that if the barrier silicon layer is formed, the increase in the boron concentration of the SOI layer can be significantly suppressed as compared with Comparative Example 3 in which the barrier silicon layer is not formed. Further, from Table 3, it is understood that if the barrier silicon layer of 400 nm is formed, the increase in the boron concentration of the SOI layer can be suppressed to within twice, and further, if the barrier silicon layer is formed to a thickness of 500 nm which is half of the thickness of the buried oxide film to be formed later, the increase in the boron concentration of the SOI layer can be substantially suppressed. Figure 7 ​As is apparent from Table 2, even if the thickness of the buried oxide film is increased to 2 μm, if a barrier silicon layer is formed, the increase in the boron concentration of the SOI layer can be suppressed as compared with Comparative Example 2 in which no barrier silicon layer is formed.

[0282] In addition, according to Figure 7 As is apparent from Table 2, even if the thickness of the buried oxide film is increased to 2 μm, if a barrier silicon layer is formed, the increase in the boron concentration of the SOI layer can be suppressed as compared with Comparative Example 2 in which no barrier silicon layer is formed.

[0283] This means that, in the latter half of the buried oxide film of 2 μm in thickness (the portion separated from the SOI layer), although an oxide film containing boron of the substrate wafer at a high concentration at a high concentration is formed, the diffusion speed of boron in the buried oxide film containing the barrier silicon oxide film formed by oxidation of the barrier silicon layer is slow, and therefore boron does not diffuse to the SOI layer, and does not affect the boron concentration in the SOI layer. Thus, even if the buried oxide film is set to a thick film of more than 2 μm, if a barrier silicon layer is formed, the increase in the dopant concentration in the SOI layer can be suppressed, and the thickness of the barrier silicon layer is preferably about 400 to 500 nm, and for safety, it is recommended that it be formed to be about 600 to 1000 nm or more.

[0284] Furthermore, the present application is not limited to the above-described embodiments. The above-described embodiments are examples, and any solution having substantially the same structure as that recited in the technical idea of the claims of the present application and achieving the same effects is included in the technical scope of the present application.

Claims

1. A method for manufacturing an SOI wafer, comprising at least the following steps: a preparation step of preparing a base wafer and a bonding wafer, wherein the base wafer is composed of a single crystal silicon wafer containing a dopant throughout the wafer and having a first main surface and a second main surface opposite to the first main surface; and the bonding wafer is composed of a single crystal silicon wafer containing a dopant at a concentration lower than the dopant concentration of the base wafer; a thermal oxidation step of forming a silicon oxide film on the entire surface of the base wafer by thermal oxidation; a bonding step of bonding one main surface of the bonding wafer to the first main surface of the base wafer via the silicon oxide film on the base wafer; as well as a thin-filming step of thinning the bonded wafer to form an SOI layer; It is characterized by: Before the thermal oxidation process of the base wafer, the following process is also included: forming a CVD insulating film on the second main surface of the base wafer; and forming a barrier silicon layer on the first main surface of the base wafer, the barrier silicon layer containing a dopant at a concentration lower than the dopant concentration of the base wafer; In the thermal oxidation step, the barrier silicon layer is thermally oxidized to obtain a barrier silicon oxide film as a portion of the silicon oxide film. In the bonding step, the one main surface of the bonded wafer and the first main surface of the base wafer are bonded to each other via the barrier silicon oxide film which is a part of the silicon oxide film.

2. The method for manufacturing an SOI wafer according to claim 1, wherein: Before the bonding step, the method further includes forming a silicon oxide film on the entire surface of the bonded wafer.

3. The method for manufacturing an SOI wafer according to claim 1, wherein: In the bonding step, the single crystal silicon surface of the one main surface of the bonded wafer and the surface of the barrier silicon oxide film of the base wafer are directly bonded to each other.

4. The method for manufacturing an SOI wafer according to claim 1, wherein: The method further includes an ion implantation step before the bonding step, wherein at least one ion selected from the group consisting of hydrogen ions and rare gas ions is implanted into the bonded wafer to form an ion implantation layer. In the thinning step, the bonded wafer is peeled off using the ion implanted layer as a peeling surface, thereby thinning the bonded wafer to obtain the SOI layer.

5. The method for manufacturing an SOI wafer according to claim 1, wherein: In the step of forming the CVD insulating film, any one of a CVD oxide film, a CVD nitride film, and a CVD oxide nitride film is formed as the CVD insulating film.

6. The method for manufacturing an SOI wafer according to claim 1, wherein: The dopant concentration is 1×10 17 atoms / cm 3 The above wafer is used as the base wafer.

7. The method for manufacturing an SOI wafer according to claim 1, wherein: The prepared dopant concentration is 1×10 16 atoms / cm 3 The following layer serves as the barrier silicon layer.

8. The method for manufacturing an SOI wafer according to any one of claims 1 to 7, wherein: In the thermal oxidation step, thermal oxidation is performed so that a portion of the barrier silicon layer remains unoxidized; Annealing is then performed, in which the dopant in the base wafer is diffused into the unoxidized portion of the barrier silicon layer.

9. An SOI wafer comprising a base wafer, a buried oxide film, and an SOI layer bonded to the base wafer via the buried oxide film, wherein: The base wafer is composed of a single crystal silicon wafer containing a dopant throughout the wafer and having a first main surface that is a bonding surface to the SOI layer and a second main surface that is opposite to the first main surface. A barrier silicon oxide film serving as at least a portion of the buried oxide film is disposed on the first main surface of the base wafer. A backside silicon oxide film is arranged on the second main surface of the base wafer. A side silicon oxide film is arranged on the side of the base wafer. The entire surface of the base wafer is covered with a silicon oxide film including the barrier silicon oxide film, the back silicon oxide film, and the side silicon oxide film. A CVD insulating film is disposed on the surface of the back silicon oxide film opposite to the base wafer. The SOI layer is composed of single crystal silicon containing a dopant at a concentration lower than the dopant concentration of the base wafer. The concentration of the dopant in the blocking silicon oxide film is lower than the concentration of the dopant in the back silicon oxide film.

10. The SOI wafer according to claim 9, wherein: A barrier silicon layer is arranged between the base wafer and the barrier silicon oxide film. The barrier silicon layer is diffused with the same kind of dopant as that contained in the base wafer.

Images