Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Abstract

The present invention improves the image quality of image data in a solid-state imaging element using a comparator. The solid-state imaging element is equipped with a current source, a pixel circuit, a comparison circuit, a control unit and a counter. The current source generates a constant current. The pixel circuit generates a pixel signal having a voltage higher than a predetermined lower limit voltage corresponding to the conductance of the current source. The comparison circuit amplifies the pixel signal at a predetermined amplification factor and compares it with a predetermined reference signal. When the amplification factor increases, the control unit reduces the conductance. The counter counts and outputs the count value throughout a period of time that lasts until the comparison result from the comparison circuit is inverted.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. Specifically, the present technology relates to a solid-state imaging element that performs analog-to-digital conversion using a comparator and a counter, an imaging device, and a control method for the solid-state imaging element. Background Art

[0002] In the prior art, due to the simple structure of the single slope analog-to-digital converter (ADC), the single slope analog-to-digital converter (ADC) has been used for analog-to-digital (AD) conversion in solid-state imaging elements and the like. The single slope ADC is generally configured by a comparator and a counter that performs counting based on the comparison result of the comparator. For example, a solid-state imaging element in which a p-channel metal oxide semiconductor (pMOS) transistor, a current source, and an inverter are set in the comparator has been proposed (for example, see patent document 1). A reference signal is input to the gate of the pMOS transistor, a pixel signal is input to the source via a vertical signal line, and a current source is connected to the drain. In addition, the voltage at the connection node of the pMOS transistor and the current source is output to the counter via an inverter as a result of the comparison of the pixel signal with the reference signal.

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: U.S. Patent Application Publication No. 2018 / 0103222. Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above-mentioned solid-state imaging element, compared with the configuration in which the comparator is also provided with a power supply separated from the pixel circuit, the power consumption is reduced by the comparator sharing the power supply of the pixel circuit. However, in the above-mentioned solid-state imaging element, the current source and the pMOS transistor are connected in series to the vertical signal line, so the dynamic range of the pixel signal may be degraded compared to the case where they are not connected. In addition, the noise generated by the current source increases as the conductance increases to expand the dynamic range. Therefore, it is impossible to achieve both the expansion of the dynamic range and the reduction of noise in the above-mentioned solid-state imaging element, and there is a problem that the image quality of the image data may be degraded due to the lack of dynamic range and the increase of noise.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to improve the image quality of image data in a solid-state imaging element using a comparator.

[0009] Solution to the problem

[0010] The present technology is made to solve the above-mentioned problems, and according to a first aspect of the present technology, there is provided a solid-state imaging element, including: a current source generating a constant current; a pixel circuit generating a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source; a comparison circuit amplifying the pixel signal at a predetermined amplification factor and comparing the amplified pixel signal with a predetermined reference signal; a control section reducing the conductance as the amplification factor increases; and a counter counting a count value in a time period until the comparison result of the comparison circuit is inverted and outputting the count value, and a method for controlling the solid-state imaging element. This produces an effect of improving the image quality of image data.

[0011] In addition, in the first aspect, the current source may include a plurality of transistors and a switch circuit that switches the connection mode of the plurality of transistors. This produces an effect that the conductance of the current source is controlled.

[0012] In addition, in the first aspect, the plurality of transistors may include: a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a source of the second transistor to a comparison circuit; and a third switch connecting a source of the second transistor to the ground terminal. This produces an effect that conductance is controlled in two stages.

[0013] In addition, in the first aspect, the plurality of transistors may include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to the comparison circuit, and the switch circuit may include: a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a connection node of the second transistor and the third transistor to the comparison circuit; a third switch connecting a connection node of the second transistor and the third transistor to the ground terminal; a fourth switch connecting a connection node of the third transistor and the fourth transistor to the comparison circuit; a fifth switch connecting a connection node of the third transistor and the fourth transistor to the ground terminal; a sixth switch connecting a source of the fourth transistor to the comparison circuit; and a seventh switch connecting a source of the fourth transistor to the ground terminal. This produces an effect that conductance is controlled in three stages.

[0014] In addition, in the first aspect, the plurality of transistors may include a first transistor and a second transistor, the drain of the first transistor being connected to the comparison circuit, the source of the second transistor being connected to a predetermined ground terminal, and the switch circuit may include: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; and a third switch connecting the drain of the second transistor to the comparison circuit. This produces an effect of suppressing surge current.

[0015] In addition, in the first aspect, the plurality of transistors may include: a first transistor, whose drain is connected to the comparison circuit; a second transistor and a third transistor; and a fourth transistor, whose source is connected to a predetermined ground terminal, and the switch circuit may include: a first switch, connecting the source of the first transistor to the ground terminal; a second switch, connecting the source of the first transistor to the drain of the second transistor; a third switch, connecting the drain of the second transistor to the comparison circuit; a fourth switch, connecting the source of the second transistor to the ground terminal; a fifth switch, connecting the source of the second transistor to the drain of the third transistor; a sixth switch, connecting the drain of the third transistor to the comparison circuit; a seventh switch, connecting the source of the third transistor to the ground terminal; an eighth switch, connecting the source of the third transistor to the drain of the fourth transistor; and a ninth switch, connecting the drain of the fourth transistor to the comparison circuit. This produces an effect of suppressing surge current and controlling conductance in three stages.

[0016] In addition, in the first aspect, a bias circuit for generating a constant reference current may be further included, and the reference current is copied by the current source, which produces an effect that the amount of current is kept constant.

[0017] In addition, in the first aspect, an image processing unit may be further included that measures illuminance based on image data in which count values ​​are arranged, and the control unit may control the amplification factor to a value corresponding to the illuminance. This produces an effect of controlling conductance according to the illuminance.

[0018] In addition, in the first aspect, the pixel circuit can be connected to the comparison circuit via the vertical signal line, and the comparison circuit can be inserted between the vertical signal line and the current source. This produces an effect that the lower limit voltage becomes a value corresponding to the operating voltage of the comparison circuit and the current source.

[0019] In addition, in the first aspect, the pixel circuit may be connected to the comparison circuit via the vertical signal line, and the comparison circuit may be connected to the vertical signal line. This results in the lower limit voltage becoming a value corresponding to the operating voltage of the current source.

[0020] In addition, in the first aspect, it can also include: a generator that generates an output signal having a sawtooth waveform; and a source follower transistor that outputs a signal corresponding to the output signal from a source as a reference signal, and the current source can include: a comparator internal current source connected to the comparison circuit; and a source follower current source connected to the source of the source follower transistor. This produces an effect of increasing the control range of the amplitude of the reference signal.

[0021] In addition, according to a second aspect of the present technology, there is provided an imaging device including: a current source generating a constant current; a pixel circuit generating a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source; a comparison circuit amplifying the pixel signal at a predetermined amplification ratio and comparing the amplified pixel signal with a predetermined reference signal; a control section reducing the conductance when the amplification ratio increases; a counter counting a count value in a period until the comparison result of the comparison circuit is inverted and outputting the count value; and a storage section storing image data arranged with a digital signal indicating the count value. This produces an effect of capturing image data with improved image quality.

[0022] In addition, according to a third aspect of the present technology, there is provided a light detection device, comprising: a pixel that outputs a pixel signal according to incident light; a vertical signal line that transmits the pixel signal; a comparator that includes a transistor, either one of a source and a drain of the transistor is connected to the vertical signal line, and a gate of the transistor receives a reference signal; and a current source that is connected to the other of the source and the drain of the transistor, wherein the current source includes: a plurality of transistors; and a switch circuit that switches the connection mode of the plurality of transistors. This produces an effect of improving the image quality of the image data.

[0023] Furthermore, in a third aspect, the plurality of transistors may include a first transistor and a second transistor connected in series to a comparison circuit, and the switch circuit may include: a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a source of the second transistor to the comparison circuit; and a third switch connecting a source of the second transistor to the ground terminal. This produces an effect that conductance is controlled in two stages.

[0024] Furthermore, in a third aspect, the plurality of transistors may include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to a comparison circuit, and the switch circuit may include: a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a connection node of the second transistor and the third transistor to the comparison circuit; a third switch connecting a connection node of the second transistor and the third transistor to the ground terminal; a fourth switch connecting a connection node of the third transistor and the fourth transistor to the comparison circuit; a fifth switch connecting a connection node of the third transistor and the fourth transistor to the ground terminal; a sixth switch connecting a source of the fourth transistor to the comparison circuit; and a seventh switch connecting a source of the fourth transistor to the ground terminal. This produces an effect that conductance is controlled in three stages.

[0025] In addition, in a third aspect, the plurality of transistors may include: a first transistor whose drain is connected to a comparison circuit; and a second transistor whose source is connected to a predetermined ground terminal, and the switch circuit may include: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; and a third switch connecting the drain of the second transistor to the comparison circuit. This produces an effect of suppressing surge current.

[0026] In addition, in the third aspect, the plurality of transistors may include: a first transistor whose drain is connected to a comparison circuit; a second transistor and a third transistor; and a fourth transistor whose source is connected to a predetermined ground terminal, and the switch circuit may include: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; a third switch connecting the drain of the second transistor to the comparison circuit; a fourth switch connecting the source of the second transistor to the ground terminal; a fifth switch connecting the source of the second transistor to the drain of the third transistor; a sixth switch connecting the drain of the third transistor to the comparison circuit; a seventh switch connecting the source of the third transistor to the ground terminal; an eighth switch connecting the source of the third transistor to the drain of the fourth transistor; and a ninth switch connecting the drain of the fourth transistor to the comparison circuit. This produces an effect of suppressing surge current and an effect of conductance being controlled in three levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.

[0028] Figure 2 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0029] Figure 3 is a circuit diagram showing a configuration example of a pixel circuit according to the first embodiment of the present technology.

[0030] Figure 4 is a block diagram showing a configuration example of a column ADC according to the first embodiment of the present technology.

[0031] Figure 5 is a diagram illustrating an example of a waveform of a reference signal according to the first embodiment of the present technology.

[0032] Figure 6 is a circuit diagram showing a configuration example of a comparator according to the first embodiment of the present technology.

[0033] Figure 7 : is a diagram for explaining control of the dynamic range according to the first embodiment of the present technology.

[0034] Figure 8 is a diagram for explaining control of conductance according to the first embodiment of the present technology.

[0035] Fig. 9 : is a circuit diagram showing a configuration example of a current source within a comparator according to the first embodiment of the present technology.

[0036] Fig.10 is a diagram illustrating an example of a state of a current source within a comparator when a high gain is set according to the first embodiment of the present technology.

[0037] Fig.11 is a diagram illustrating an example of a state of a current source within a comparator when a low gain is set according to the first embodiment of the present technology.

[0038] Fig.12 is a timing chart showing an example of the operation of the solid-state imaging element according to the first embodiment of the present technology.

[0039] Fig.13 : is a circuit diagram showing a configuration example of a current source within a comparator according to a second embodiment of the present technology.

[0040] Fig.14 is a diagram illustrating an example of a state of a current source within a comparator when a high gain is set according to the second embodiment of the present technology.

[0041] Fig.15 is a diagram illustrating an example of a state of a current source within a comparator when an intermediate gain is set according to the second embodiment of the present technology.

[0042] Fig.16 is a diagram illustrating an example of a state of a current source within a comparator when a low gain is set according to the second embodiment of the present technology.

[0043] Fig.17 : is a circuit diagram showing a configuration example of a current source within a comparator according to a third embodiment of the present technology.

[0044] Fig.18 is a diagram illustrating an example of a state of a current source within a comparator when a high gain is set according to the third embodiment of the present technology.

[0045] Fig.19 is a diagram illustrating an example of a state of a current source within a comparator when a low gain is set according to the third embodiment of the present technology.

[0046] Fig. 20 : is a circuit diagram showing a configuration example of a current source within a comparator according to a modified example of the third embodiment of the present technology.

[0047] Fig.21: is a diagram illustrating an example of a state of a current source within a comparator when a high gain is set according to a modified example of the third embodiment of the present technology.

[0048] Fig. 22 : is a diagram illustrating an example of a state of a current source within a comparator when an intermediate gain is set according to a modified example of the third embodiment of the present technology.

[0049] Fig.23 : is a diagram illustrating an example of a state of a current source within a comparator when a low gain is set according to a modified example of the third embodiment of the present technology.

[0050] Fig.24 : is a circuit diagram showing a configuration example of a comparator control section according to a fourth embodiment of the present technology.

[0051] Fig.25 is a block diagram showing a configuration example of a solid-state imaging element according to a fifth embodiment of the present technology.

[0052] Fig.26 is a flowchart showing an example of the operation of the solid-state imaging element according to the fifth embodiment of the present technology.

[0053] Fig. 27 is a flowchart illustrating an example of light measurement processing according to the fifth embodiment of the present technology.

[0054] Fig.28 is a flowchart illustrating an example of imaging processing according to the fifth embodiment of the present technology.

[0055] Fig.29 is a block diagram showing a configuration example of a column ADC according to a sixth embodiment of the present technology.

[0056] Fig.30 : is a circuit diagram showing a configuration example of a slope generating section according to a seventh embodiment of the present technology.

[0057] Fig.31 is a block diagram showing a schematic configuration example of a vehicle control system.

[0058] Fig.32 : is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0059] Hereinafter, a mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described. The description will be given in the following order.

[0060] 1. First Embodiment (Example of Controlling Conductance of Current Source Inside Comparator)

[0061] 2. Second Embodiment (Example of Conductance of Current Source Inside Three-Level Control Comparator)

[0062] 3. Third Embodiment (Example of Controlling Conductance of Current Source Inside Comparator and Suppressing Surge Current)

[0063] 4. Fourth Embodiment (Example of Controlling the Conductance of the Current Source Inside the Comparator and Using a Current Mirror Circuit)

[0064] 5. Fifth Embodiment (Example of Setting Analog Gain According to Illuminance and Controlling Conductance of Current Source Inside Comparator)

[0065] 6. Sixth Embodiment (Example of Controlling Conductance of Current Source Inside Slope Generating Section)

[0066] 7. Seventh Embodiment (Example of Controlling Conductance of Current Source External to Comparator)

[0067] 8. Application examples for mobile objects

[0068] <1. First Embodiment>

[0069] [Configuration Example of Imaging Device]

[0070] Figure 1 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical section 110, a solid-state imaging element 200, and a digital signal processing (DSP) circuit 120. In addition, the imaging device 100 includes a display section 130, an operation section 140, a bus 150, a frame memory 160, a storage section 170, and a power supply section 180. As the imaging device 100, a camera mounted on a smartphone, a car-mounted camera, or the like is assumed.

[0071] The optical section 110 is adapted to collect light from a subject and guide the light to the solid-state imaging element 200 . The solid-state imaging element 200 is adapted to generate image data by photoelectric conversion. The solid-state imaging element 200 supplies the generated image data to the DSP circuit 120 via a signal line 209 .

[0072] The DSP circuit 120 is adapted to perform predetermined signal processing on the image data and outputs the processed image data to the frame memory 160 or the like via the bus 150 .

[0073] The display section 130 is adapted to display image data. For example, a liquid crystal panel or an organic electroluminescent (EL) panel is assumed as the display section 130. The operation section 140 is adapted to generate an operation signal in response to a user's operation.

[0074] The bus 150 is a common path through which the optical section 110 , the solid-state imaging element 200 , the DSP circuit 120 , the display section 130 , the operation section 140 , the frame memory 160 , the storage section 170 , and the power supply section 180 exchange data with each other.

[0075] The frame memory 160 is adapted to store image data. The storage section 170 is adapted to store various data such as image data. The power supply section 180 is adapted to supply power to the solid-state imaging element 200, the DSP circuit 120, the display section 130, and the like.

[0076] [Configuration Example of Solid-State Imaging Element]

[0077] Figure 2 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that the connection may also be established by a through hole or a bump instead of Cu-Cu bonding.

[0078] The light receiving chip 201 includes a pixel array section 250 arranged thereon. In addition, a vertical driving section 210 , a gain control section 220 , a slope generating section 230 , a comparator controlling section 240 , a column ADC 270 , a horizontal driving section 280 , and an image processing section 290 are arranged on the circuit chip 202 .

[0079] Note that the circuits arranged on each of the light receiving chip 201 and the circuit chip 202 are not limited to the configuration shown as an example in the drawings. For example, the column pixel array section 250 and the comparator (not shown) in the ADC 270 may be arranged on the light receiving chip 201, and other circuits may be arranged on the circuit chip 202.

[0080] In the pixel array section 250, a plurality of pixel circuits 260 are arranged in a two-dimensional grid shape. Hereinafter, a set of pixel circuits 260 arranged in a predetermined horizontal direction will be referred to as a "row", and a set of pixel circuits 260 arranged in a direction orthogonal to the row will be referred to as a "column".

[0081] The vertical driving section 210 is adapted to sequentially drive the rows and cause the rows to output analog pixel signals to the column ADC 270 .

[0082] The gain control section 220 is adapted to control the analog gain based on the setting data synchronized with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal of a predetermined frequency (such as 60 Hz) indicating the imaging timing. In addition, the analog gain is the amplification factor when the comparator inside the column ADC 270 amplifies the pixel signal. The setting data is data indicating the setting value of the analog gain. The vertical synchronization signal VSYNC and the setting data are generated by a circuit (such as the DSP circuit 120) outside the solid-state imaging element 200, and then input to the solid-state imaging element 200.

[0083] Furthermore, the gain control section 220 generates a digital control signal CTRL for controlling the ramp generation section 230 , and provides the control signal CTRL to the ramp generation section 230 and the comparator control section 240 .

[0084] The ramp generation section 230 is adapted to generate a ramp signal having a sawtooth waveform according to the control signal CTRL and provide the ramp signal as a reference signal to the column ADC 270. For example, the ramp generation section 230 is represented by a digital-to-analog converter (DAC).

[0085] Here, when the analog signal indicated by the setting data is high, the gain control section 220 reduces the amplitude of the ramp signal using the control signal CTRL.

[0086] The comparator control section 240 is adapted to control the conductance of a comparator (not shown) inside the column ADC 270 based on the control signal CTRL. Details of the control of the conductance will be described later.

[0087] An ADC (not shown) is arranged for each column in the column ADC 270 . Each ADC converts a pixel signal of a corresponding column into a digital signal according to control performed by the horizontal driving section 280 and supplies the digital signal to the image processing section 290 .

[0088] The horizontal driving section 280 is adapted to control the column ADC 270 and cause the column ADC 270 to output digital signals in sequence.

[0089] The image processing section 290 is adapted to perform various image processing such as demosaic processing and white balance processing on the digital signal aligned image data. The image processing section 290 supplies the processed image data to the DSP circuit 120 via the signal line 209. Note that a circuit (e.g., the DSP circuit 120) external to the solid-state imaging element 200 may also perform part or all of the processing of the image processing section 290 instead of the image processing section 290.

[0090] [Configuration Example of Pixel Circuit]

[0091] Figure 32 is a circuit diagram showing a configuration example of a pixel circuit 260 according to the first embodiment of the present technology. The pixel circuit 260 includes a photoelectric conversion element 261, a transfer transistor 262, a reset transistor 263, a floating diffusion layer 264, an amplification transistor 265, and a selection transistor 266. In addition, for each column in the pixel array section 250, a vertical signal line 269 is arranged in the vertical direction.

[0092] The photoelectric conversion element 261 is adapted to perform photoelectric conversion on incident light and generate electric charges, and the transfer transistor 262 is adapted to transfer electric charges from the photoelectric conversion element 261 to the floating diffusion layer 264 according to the drive signal TRG from the vertical drive section 210 .

[0093] The reset transistor 263 is adapted to withdraw charges from the floating diffusion layer 264 and initialize the charges according to a driving signal RST from the vertical driving section 210 .

[0094] The floating diffusion layer 264 is adapted to accumulate charges and generate a voltage corresponding to the amount of the charges. The amplifier transistor 265 is adapted to amplify the voltage of the floating diffusion layer 264.

[0095] The selection transistor 266 is adapted to output the signal of the amplified voltage as a pixel signal to the column ADC 270 via the vertical signal line 269 according to the drive signal SEL from the vertical drive section 210 .

[0096] Note that the pixel circuit 260 is not limited to the circuit shown as an example in the drawings as long as it can generate an analog pixel signal by photoelectric conversion.

[0097] [Configuration example of column ADC]

[0098] Figure 4 2 is a block diagram showing a configuration example of a column ADC 270 according to the first embodiment of the present technology. For each column in the column ADC 270, a capacitor 271, a comparator 300, a counter 272, and a latch 273 are arranged. In the case where the number of columns is N (N is an integer), N capacitors 271, N comparators 300, N counters 272, and N latches 273 are arranged.

[0099] The comparator 300 is adapted to compare the reference signal RMP (ramp signal) from the ramp generating section 230 with the pixel signal SIG from the corresponding column. The reference signal RMP is input to the comparator 300 via the capacitor 271, and the pixel signal is input via the vertical signal line 269. The comparator 300 provides a result COMP of comparing the reference signal RMP with the pixel signal SIG to the counter 272 of the corresponding column.

[0100] In addition, the level of the pixel signal when the pixel circuit 260 is initialized is hereinafter referred to as a “reset level”, and the level of the pixel signal when the charge is transferred to the floating diffusion layer 264 is hereinafter referred to as a “signal level”.

[0101] The counter 272 is adapted to count the count value in a time period until the comparison result COMP is inverted. The counter 272 performs down-counting in a time period until the result COMP of the comparison with the reset level is inverted, and performs up-counting in a time period until the result COMP of the comparison with the signal level is inverted. In this way, a correlated double sampling (CDS) process for obtaining a difference between the reset level and the signal level is implemented.

[0102] In addition, the counter 272 causes the latch 273 to hold a digital signal indicating a count value. The comparator 300 and the counter 272 implement an AD conversion process for converting an analog pixel signal into a digital signal. In other words, the comparator 300 and the counter 272 function as an ADC. An ADC using a comparator and a counter in this manner is generally referred to as a single slope type ADC.

[0103] Note that although CDS processing is implemented by up-counting and down-counting, the present technology is not limited thereto. A configuration may also be adopted in which the counter 272 performs only up-counting or down-counting, and CDS processing for obtaining a difference value is performed by a circuit at a subsequent stage.

[0104] The latch 273 is adapted to hold a digital signal and outputs the held digital signal to the image processing section 290 according to control performed by the horizontal driving section 280 .

[0105] Figure 5 : is a diagram showing an example of the waveform of the reference signal RMP according to the first embodiment of the present technology. Graph a in the figure shows an example of the waveform of the reference signal RMP when controlled to low gain (i.e., analog gain below a predetermined boundary value). Graph b in the figure shows an example of the waveform of the reference signal RMP when controlled to high gain (i.e., analog gain above a boundary value).

[0106] As shown in the examples a and b in the figure, the reference signal RMP gradually decreases in the time period from timing t1 to timing t2 for AD conversion of the reset level. In addition, the reference signal RMP also gradually decreases in the time period from timing t3 to timing t4 for AD conversion of the signal level, and its amplitude is larger than the amplitude in the AD conversion period of the reset level.

[0107] In addition, as shown in the example of a in the figure, the amplitude of the reference signal RMP is a value larger when the control is low gain than when the control is high gain. In addition, as shown in the example of b in the figure, the amplitude of the reference signal RMP is a value smaller when the control is high gain than when the control is low gain.

[0108] In the case where the level of the pixel signal is fixed, the time until the comparison result of the comparator 300 is inverted is extended, and the count value of the counter 272 increases as the amplitude of the reference signal RMP decreases. In this way, as the amplitude of the reference signal RMP decreases, the effect of the pixel signal being amplified in the ADC including the comparator 300 and the counter 272 further occurs. The amplification rate of the pixel signal corresponds to the above-mentioned analog gain.

[0109] In the case where the illuminance of ambient light is high, the ratio of the signal level to the reset level increases, and thus setting data indicating a low gain is generated by the DSP circuit 120, etc., in order to suppress white points. On the other hand, in the case where the illuminance of ambient light is low, setting data indicating a high gain is generated by the DSP circuit 120, etc., in order to increase sensitivity. In this way, as the illuminance is higher, a lower analog gain is set.

[0110] [Comparator Configuration Example]

[0111] Figure 6 3 is a circuit diagram showing a configuration example of a comparator 300 according to the first embodiment of the present technology. The comparator 300 includes a comparison circuit 310 and in-comparator current sources 320 and 350 .

[0112] The comparison circuit 310 is adapted to compare the pixel signal SIG from the pixel circuit 260 with the reference signal RMP from the ramp generation section 230 and provide the comparison result COMP to the counter 272. Furthermore, as described above, the pixel signal SIG is amplified with an analog gain according to the amplitude of the reference signal RMP.

[0113] The comparison circuit 310 includes an input transistor 311 , an auto-zero switch 312 , a capacitor 313 , a clamp transistor 314 , and an output transistor 315 .

[0114] The source of the input transistor 311 is connected to the vertical signal line 269, and the pixel signal SIG is input to the source. In addition, the reference signal RMP is input to the gate of the input transistor 311 via the capacitor 271. When the voltage of the pixel signal input to the source and the voltage of the reference signal input to the gate are roughly consistent with each other, the input transistor 311 enters the same voltage state as the voltage state during automatic zeroing, and outputs a drain voltage corresponding to these voltages from the drain. Here, "roughly consistent" means that each change in the voltage value within the self-zeroing time period is completely consistent or the difference between them is within a predetermined allowable value. For example, a pMOS transistor is used as the input transistor 311.

[0115] Furthermore, it is desirable that the back gate and the source of the input transistor 311 be short-circuited to suppress the back gate effect.

[0116] The auto-zero switch 312 is adapted to cause a short circuit between the gate and the drain of the input transistor 311 according to a control signal AZSW from the comparator control section 240 .

[0117] The capacitor 313 is inserted between the source and the drain of the input transistor 311 .

[0118] The clamp transistor 314 is inserted between the source and drain of the input transistor 311. A pMOS transistor is used as the clamp transistor 314, and its gate and drain are short-circuited. In addition, it is desirable that the back gate and source of the clamp transistor 314 are short-circuited. When the input transistor 311 is in a non-conductive state, the clamp transistor 314 can suppress a decrease in the drain voltage.

[0119] The source of the output transistor 315 is connected to the vertical signal line 269, and the pixel signal SIG is input to the source. In addition, the gate of the output transistor 315 is connected to the drain of the input transistor 311, and the drain voltage is input to the gate. For example, a pMOS transistor is used as the output transistor 315. In addition, it is desired that the back gate and the source of the output transistor 315 are short-circuited.

[0120] The output transistor 315 outputs a signal indicating whether the difference between the voltage of the pixel signal SIG input to the source and the drain voltage input to the gate exceeds a predetermined threshold voltage from the drain as a comparison result COMP. The comparison result COMP is provided to the counter 272.

[0121] Here, when the pixel signal SIG and the reference signal RMP are substantially consistent with each other, the drain voltage of the input transistor 311 varies according to the level of the pixel signal SIG. Therefore, the timing of drain voltage inversion may deviate from the ideal timing that the pixel signal SIG and the reference signal RMP are substantially consistent with each other.

[0122] However, by the connection in the figure, the voltage between the drain and source of the input transistor 311 is input as the voltage between the gate and source of the output transistor 315. Since the amount of change in the drain voltage of the input transistor is equal to the amount of change in the voltage of the pixel signal SIG, the comparison result COMP from the output transistor 315 is inverted at the ideal timing when the pixel signal SIG and the reference signal RMP are substantially consistent with each other. Therefore, the error of the inversion timing can be suppressed by adding the output transistor 315.

[0123] The comparator internal current source 320 is inserted between the drain of the input transistor 311 and a predetermined reference terminal (such as a ground terminal) and generates a constant current. The comparator internal current source 350 is inserted between the drain of the output transistor 315 and a predetermined reference terminal (such as a ground terminal) and generates a constant current. In addition, the comparator control section 240 controls the conductance of the comparator internal current sources 320 and 350 using the switch signal CSW. These conductances are substantially the same.

[0124] Note that although the clamp transistor 314 and the output transistor 315 are provided in the comparison circuit 310, a configuration in which at least one of them is not provided may be adopted. In the case where the output transistor 315 is not provided, the in-comparator current source 350 is not required. In addition, although the comparator control section 240 controls the conductance of both the in-comparator current sources 320 and 350, it is also possible to control the conductance of only one of them and keep the other conductance at a fixed value.

[0125] Figure 7 : is a diagram for explaining control of the dynamic range according to the first embodiment of the present technology.

[0126] The sum of the voltages between the drain and the source when each of the amplification transistor 265 and the selection transistor 266 in the pixel circuit 260 is in the on state is defined as the "pixel Tr operating voltage". The upper limit of the voltage of the vertical signal line 269 (i.e., the pixel signal SIG) is a value lower than the power supply voltage VDD by the pixel Tr operating voltage.

[0127] In addition, the voltage between the drain and the source when the input transistor 311 in the comparison circuit 310 is in the on state is defined as the "pMOS operating voltage". It is assumed that the voltage between the drain and the source when the output transistor 315 is in the on state is substantially the same as the voltage of the input transistor 311. The voltage between the connection node between the input transistor 311 and the current source 320 in the comparator and the ground potential VSS is defined as the "current source operating voltage". The lower limit of the pixel signal SIG is the sum of the pMOS operating voltage and the current source operating voltage. The ratio between the upper limit and the lower limit of the pixel signal SIG will be referred to as the "VSL dynamic range".

[0128] Here, the connection node of the vertical signal line 269 and the current source outside the comparator is connected to the input terminal of the comparator in a typical comparator using a differential amplifier circuit. Therefore, in the case of using a differential amplifier circuit, the lower limit of the pixel signal SIG is the current source operating voltage.

[0129] However, the comparison circuit 310 is inserted between the vertical signal line 269 and the comparator internal current source 320 in the comparator 300. Therefore, compared with the case of using a differential amplifier, the lower limit of the pixel signal SIG becomes higher and the VSL dynamic range becomes narrower, corresponding to the amount of the pMOS operating voltage.

[0130] Since the current source operating voltage is inversely proportional to the conductance of the current sources 320 and 350 in the comparator, it is only necessary to increase the conductance to expand the VSL dynamic range. However, the random telegraph signal (RTS) noise increases in proportion to the conductance. Here, the RTS noise is the noise caused by the random capture and release of electrons in the interface state of the gate oxide film of the MOS transistor, and varies according to the gate width and gate length. If the gate width and gate length are adjusted so that the conductance increases, the RTS noise increases.

[0131] The level of RTS noise needs to be equal to or less than a predetermined target value, and this value is defined by the ratio to the level of random noise. In the case of low gain, random noise increases, and therefore the target value of RTS noise is moderated to a larger value than in the case of high gain. On the other hand, in the case of high gain, random noise decreases, and therefore the target value of RTS noise is set to a lower value than in the case of low gain.

[0132] In addition, although a low gain is set when the illumination of the ambient light is high, the ratio of the signal level to the reset level increases as the illumination increases, so it is necessary to expand the VSL dynamic range. On the other hand, although a high gain is set when the illumination of the ambient light is low, the ratio of the signal level to the reset level decreases as the illumination decreases, and the VSL dynamic range may be relatively narrow.

[0133] In consideration of the above, when a low gain is set by setting data, the comparator control section 240 increases the conductance of the current sources 320 and 350 in the comparator compared to when the gain is high. Therefore, the VSL dynamic range can be extended. Although the RTS noise increases due to the increase in conductance, as described above, the target value of the RTS noise is relaxed in the case of low gain, and therefore no problem occurs.

[0134] On the other hand, in the case where a high gain is set by setting data, the comparator control section 240 reduces the conductance of the current sources 320 and 350 in the comparator compared to the conductance at a low gain. Therefore, the RTS noise can be reduced. Although the VSL dynamic range is narrowed due to the reduction in conductance, as described above, the illumination is low at a low gain and the ratio of the signal level to the reset level is low, so there is no problem.

[0135] In short, the current sources 320 and 350 in the comparator generate a constant current. The pixel circuit 260 generates a pixel signal SIG, and its lower limit voltage is a value according to the conductance. The comparison circuit 310 amplifies the pixel signal SIG with an analog gain and compares the amplified pixel signal SIG with the reference signal RMP. As the analog gain increases, the comparator control section 240 reduces the conductance of the current sources 320 and 350 in the comparator. The counter 272 counts the count value in the time period until the comparison result COMP is inverted and outputs the count value.

[0136] The VSL dynamic range can be expanded at low gain and the RTS noise can be reduced at high gain by controlling the conductance. Therefore, the image quality of the image data can be improved.

[0137] Note that the comparator control section 240 is an example of a control section described in the claims. Furthermore, the comparator internal current sources 320 and 350 are examples of current sources described in the claims.

[0138] Note that although the comparator control section 240 uses the same boundary value of the analog gain to switch the conductance of each of the comparator internal current sources 320 and 350, the present technology is not limited to this. When switching between the comparator internal current source 320 and the comparator internal current source 350, different boundary values ​​of the analog gain may also be used.

[0139] Figure 8 1 is a diagram for explaining the control of conductance according to the first embodiment of the present technology. In the case where the illumination of the ambient light is higher than a predetermined value, a low gain equal to or lower than a boundary value is set by the DSP circuit 120 or the like. In this case, the comparator control section 240 makes the conductance of the current source 320 or the like in the comparator greater than the conductance in the case of a high gain. In response to the increase in conductance, the VSL dynamic range is widened, and the level of RTS noise increases.

[0140] On the other hand, in the case where the illuminance of the ambient light is equal to or less than a predetermined value, a high gain exceeding the boundary value is set by the DSP circuit 120, etc. In this case, the comparator control section 240 sets the conductance of the current source 320, etc. in the comparator to be lower than the conductance at the low gain. In response to the reduction in conductance, the VSL dynamic range is narrowed, and the level of the RTS noise is reduced.

[0141] [Current source inside the comparator]

[0142] Fig. 9 1 is a circuit diagram showing a configuration example of the comparator internal current source 320 according to the first embodiment of the present technology. The comparator internal current source 320 includes current source transistors 321 and 322 and a switch circuit 330. As these current source transistors 321 and 322, for example, n-channel MOS (nMOS) transistors are used.

[0143] The switch circuit 330 is adapted to switch the connection mode of the current source transistors 321 and 322 according to the switch signal CSW from the comparator control section 240. The switch signal CSW is a signal including switch signals CSW1, CSW2 and CSW3. The switch circuit 330 includes switches 331, 332 and 333. For example, nMOS transistors are used as these switches. Compared with the current source transistors 321 and 322, the size (gate width and gate length) of the nMOS transistors used as these switches can be smaller. Therefore, the arrangement of the switch has a small influence on the installation area of ​​the current source 320 in the comparator.

[0144] The current source transistors 321 and 322 are connected in series to the comparison circuit 310, and a predetermined bias voltage Vb is applied to the gates thereof. Note that the current source transistors 321 and 322 are examples of the first transistor and the second transistor described in the claims.

[0145] The switch 331 is adapted to open and close the path between the connection node of the current source transistors 321 and 322 and the ground terminal according to the switch signal CSW1. The switch 332 is adapted to open and close the path between the source of the current source transistor 322 and the comparison circuit 310 according to the switch signal CSW2. The switch 333 is adapted to open and close the path between the source of the current source transistor 322 and the ground terminal according to the switch signal CSW3. A logic value of "0" or "1" is set for each of the switch signals CSW1, CSW2, and CSW3. For example, when the logic value is "0", the corresponding switch is controlled to be in an open state, and when the logic value is "1", the corresponding switch is controlled to be in a closed state.

[0146] Note that the configuration of the intra-comparator current source 350 is similar to the configuration of the intra-comparator current source 320 .

[0147] Fig.10 1 is a diagram showing an example of the state of the current source 320 in the comparator when a high gain is set according to the first embodiment of the present technology. In the figure, a shows an example of the state of the switch when a high gain is set. In the figure, b shows an example of the connection mode when a high gain is set.

[0148] As shown in the example in the figure, when a high gain is set, the comparator control section 240 causes switches 331 and 332 to enter an open state and causes switch 333 to enter a closed state. In this way, the source of the current source transistor 322 is connected to the ground terminal. Therefore, as shown in the example in b in the figure, the current source transistors 321 and 322 are connected in series to the comparison circuit 310.

[0149] The gate width of the current source transistors 321 and 322 is defined as W0, and the gate length thereof is defined as 0.5L0. In addition, each transconductance is defined as 2gm0, and the operating voltage is defined as 0.5Vdsat. The effective value of the gate width when connected in series remains W0, and the effective value of the gate length becomes L0. The combined conductance is proportional to (gate width) / (gate length), and thus becomes gm0, which is half of the individual conductance of the current source transistor due to the series connection. In addition, since the conductance becomes half, the current source operating voltage becomes Vdsat, which is twice the operating voltage of the individual current source transistor.

[0150] Note that the sizes (ie, gate width, gate length) of the current source transistors 321 and 322 are the same, but may be different. In addition, the circuit configuration of the current source 320 in the comparator is not limited to the example shown in the drawings as long as the connection configuration of the current source transistors can be switched.

[0151] Fig.11 1 is a diagram showing an example of the state of the current source 320 in the comparator when a low gain is set according to the first embodiment of the present technology. In the figure, a shows an example of the state of the switch when a low gain is set. In the figure, b shows an example of the connection mode when a low gain is set.

[0152] As shown in the example in the figure, when a low gain is set, the comparator control section 240 brings the switches 331 and 332 into a closed state and brings the switch 333 into an open state. In this way, the connection node of the current source transistors 321 and 322 is connected to the ground terminal, and the source of the current source transistor 322 is connected to the comparison circuit 310. Therefore, as shown in the example in b in the figure, the current source transistors 321 and 322 are connected in parallel with the comparison circuit 310.

[0153] The effective value of the gate width when connected in parallel is 2W0, and the effective value of the gate length becomes 0.5L0. Due to the parallel connection, the combined conductance is 2gm0, which is the same as the conductance of the current source transistor alone. In addition, the current source operating voltage is 0.5Vdsat, which is the same as the operating voltage of the current source transistor alone.

[0154] Here, in order to prevent the current amount from changing before and after switching, it is preferable to apply different bias voltages Vb in the case of parallel connection and in the case of series connection. In the case of series connection, for example, a voltage twice that in the case of parallel connection is applied as bias voltage Vb.

[0155] like Fig.10 and Fig.11 As shown, the comparator control section 240 controls the conductance of the comparator internal current source 320 by switching the connection mode of the current source transistors 321 and 322 in the comparator internal current source 320 .

[0156] Here, a configuration in which only one current source transistor is provided in the comparator internal current source 320 is assumed as a comparative example. In order to set the VSL dynamic range according to the high gain, the transconductance of the current source transistor must be set to 2gm0. In addition, in order to achieve the target value of the RTS noise at low gain while setting the transconductance to 2gm0, it is necessary to set the gate area to 2×W0×L0. In order to satisfy these conditions, for example, the gate width is adjusted to 2·2 1 / 2 W0, and the gate length is adjusted to (1 / 2)·2 1 / 2 L0.

[0157] On the other hand, in the configuration in which the connection mode is switched, as described above, the sum of the gate areas of the current source transistors 321 and 322 can be W0×L0, and the mounting area can be reduced compared with the comparative example.

[0158] [Operation Example of Solid-State Imaging Element]

[0159] Fig.12 : is a timing chart showing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology.

[0160] The image data (frame) is captured synchronously with the vertical synchronization signal VSYNC. Then, the analog gain is set according to the illumination of each frame. For example, in the frame period from the timing T1 when the vertical synchronization signal VSYNC falls to the timing T3 which is the timing of the next fall, the control signal CTRL for setting the high gain is output from the gain control section 220. After the timing T3, the gain is switched to the low gain.

[0161] In addition, a period from timing T1 to T2 in the frame period is set as a vertical blanking period VBK. In a pixel reading period from timing T2 to T3 after the period has passed, the pixel signal is AD-converted for each row.

[0162] In the vertical blanking period VBK, the comparator control section 240 switches the connection mode using the switch signal CSW. Since the high gain is set at the timing T1, the comparator control section 240 sets the switch signals CSW1 and CSW2 to the logic value "0", sets the switch signal CSW3 to the logic value "1", and switches the connection mode of the current source 320 and the like in the comparator to the series connection. In addition, since the low gain is set at the timing T3, the comparator control section 240 sets the switch signals CSW1 and CSW2 to the logic value "1", sets the switch signal CSW3 to the logic value "0", and switches the connection mode of the current source 320 and the like in the comparator to the parallel connection.

[0163] As described above, according to the first embodiment of the present technology, when the analog gain (amplification) is high, the comparator control section 240 reduces the conductance of the current source 320 in the comparator, and thus the RTS noise can be suppressed. In addition, when the analog gain is low, the comparator control section 240 increases the conductance of the current source 320 in the comparator, and thus the dynamic range can be expanded. In other words, the image quality of the image data can be improved by the expansion of the VSL dynamic range when the analog gain is low and the suppression of the RTS noise when the analog gain is high.

[0164] <2. Second Embodiment>

[0165] Although in the above-mentioned first embodiment, the comparator control section 240 controls the conductance of the current source 320 etc. in the comparator in two stages, there may be a case where the adjustment range of the current source operating voltage is lacking in the two-stage control. The comparator control section 240 according to the second embodiment is different from the comparator control section in the first embodiment in that the conductance of the current source 320 etc. in the comparator is controlled in three stages.

[0166] Fig.13 3 is a circuit diagram showing a configuration example of a comparator-internal current source 320 according to a second embodiment of the present technology. The comparator-internal current source 320 in the second embodiment is different from the comparator-internal current source in the first embodiment in that the comparator-internal current source 320 further includes current source transistors 323 and 324, and switches 334 to 337 are further included in the switch circuit 330. As the current source transistors 323 and 324, for example, nMOS transistors are used.

[0167] The current source transistors 323 and 324 are connected in series to the current source transistor 322. Furthermore, a bias voltage Vb is applied to the gates of the current source transistors 323 and 324. Note that the current source transistors 323 and 324 are examples of the third transistor and the fourth transistor described in the claims.

[0168] The switch 334 is adapted to open and close a path between a connection node of the current source transistors 323 and 324 and the comparison circuit 310 according to a switch signal CSW4 from the vertical drive section 210. The switch 335 is adapted to open and close a path between a connection node of the current source transistors 323 and 324 and a ground terminal according to a switch signal CSW5 from the vertical drive section 210.

[0169] The switch 336 is adapted to open and close the path between the source of the current source transistor 324 and the comparison circuit 310 according to the switch signal CSW6 from the vertical driving section 210. The switch 337 is adapted to open and close the path between the source of the current source transistor 324 and the ground terminal according to the switch signal CSW7 from the vertical driving section 210.

[0170] Note that the configuration of the intra-comparator current source 350 is similar to the configuration of the intra-comparator current source 320 .

[0171] Fig.14 is a diagram illustrating an example of a state of the in-comparator current source 320 when a high gain is set according to the second embodiment of the present technology.

[0172] As shown in the example in the figure, when a high gain is set, the comparator control section 240 causes the switch 337 to enter a closed state and causes the remaining switches to enter an open state. In this way, the source of the current source transistor 324 is connected to the ground terminal. Therefore, the current source transistors 321 to 324 are connected in series to the comparison circuit 310. If the gate width of the individual current source transistor is defined as W0 and the gate length is defined as 0.25L0, the effective value of the gate width in the figure is W0, and the effective value of the gate length is L0. The conductance is the same as the conductance of the individual current source transistor, and the current source operating voltage is Vdsat.

[0173] Fig.15 2 is a diagram showing an example of a state of the in-comparator current source 320 when an intermediate gain is set according to the second embodiment of the present technology. Here, the intermediate gain is a gain between a high gain and a low gain.

[0174] As shown in the example in the figure, when the intermediate gain is set, the comparator control section 240 causes switches 333 and 336 to enter a closed state and causes the remaining switches to enter an open state. In this way, the connection node of the current source transistors 322 and 323 is connected to the ground terminal, and the source of the current source transistor 324 is connected to the comparison circuit 310. Therefore, the circuit in which the current source transistors 321 and 322 are connected in series and the circuit in which the current source transistors 323 and 324 are connected in series are connected in parallel. The effective value of the gate width in the figure is 2W0, and the effective value of the gate length is 0.5L0. The conductance is twice the conductance of the current source transistor alone, and the current source operating voltage is 0.5Vdsat.

[0175] Fig.16 is a diagram illustrating an example of a state of the in-comparator current source 320 when a low gain is set according to the second embodiment of the present technology.

[0176] As shown in the example in the figure, when a low gain is set, the comparator control section 240 causes switches 331, 332, 335, and 336 to enter a closed state and causes the remaining switches to enter an open state. In this way, the connection node of current source transistors 321 and 322 and the connection node of current source transistors 323 and 324 are connected to the ground terminal. In addition, the connection node of current source transistors 322 and 323 and the source of current source transistor 324 are connected to the comparison circuit 310. Therefore, current source transistors 321 to 324 are connected in parallel. The effective value of the gate width in the figure is 4W0, and the effective value of the gate length is 0.25L0. The conductance is four times the conductance of a single current source transistor, and the current source operating voltage is 0.25Vdsat.

[0177] like Figures 14 to 16 As shown, the comparator control unit 240 can control the conductance of the current source 320 in the comparator in three stages by switching the connection mode. Therefore, compared with the case where the control is performed in two stages, the adjustment range of the current source action voltage can be expanded. By setting an appropriate current source operating voltage according to the analog gain, noise can be minimized while ensuring the necessary VSL dynamic range. For example, the VSL dynamic range when the analog gain is 6 decibels (dB) is only required to be half of the VSL dynamic range when the analog gain is 0 decibels (dB), and the noise can be further reduced by switching the reduced amount to the current source operating voltage.

[0178] Note that the sizes (i.e., gate width and gate length) of the current source transistors 321 to 324 are the same, but may be different. The current source operating voltage may be fine-tuned by combining transistors of different sizes. In addition, the current source operating voltage is controlled in three levels, but may be controlled in four or more levels by adding current source transistors and switches.

[0179] As described above, according to the second embodiment of the present technology, the number of current source transistors is increased to four, the comparator control section 240 switches its connection mode, and thus the current source operating voltage can be controlled in three stages. Therefore, compared with the case where the current source operating voltage is controlled in two stages, the VSL dynamic range and the RTS noise can be controlled to more appropriate values.

[0180] <3. Third embodiment>

[0181] In the first embodiment described above, the switch 332 switches the connection destination of the source of the current source transistor 322 to the power supply side or the ground side. In this configuration, the connection destinations of the drain and source of the current source transistor 322 are reversed from the power supply side and the ground side to the ground side and the power supply side when switching, so there is a concern that surge current may flow through the transistor. The comparator-internal current source 320 in the third embodiment is different from the comparator-internal current source in the first embodiment in that surge current is suppressed.

[0182] Fig.17 1 is a circuit diagram showing a configuration example of a current source 320 in a comparator according to a third embodiment of the present technology. In the current source 320 in the comparator in the third embodiment, similarly to the first embodiment, the drain of the current source transistor 321 is connected to the comparison circuit 310, and the source of the current source transistor 322 is connected to the ground terminal.

[0183] However, the switch 331 in the third embodiment opens and closes the path between the source of the current source transistor 321 and the ground terminal. Furthermore, the switch 332 in the third embodiment opens and closes the path between the source of the current source transistor 321 and the drain of the current source transistor 322. Furthermore, the switch 333 in the third embodiment opens and closes the path between the drain of the current source transistor 322 and the comparison circuit 310.

[0184] Note that the configuration of the intra-comparator current source 350 is similar to the configuration of the intra-comparator current source 320 .

[0185] Fig.18 is a diagram illustrating an example of a state of the in-comparator current source 320 when a high gain is set according to the third embodiment of the present technology.

[0186] When a high gain is set as shown as an example in the drawing, the comparator control section 240 brings the switches 331 and 333 into an open state and brings the switch 332 into a closed state. In this way, the source of the current source transistor 321 is connected to the drain of the current source transistor 322. Therefore, the current source transistors 321 and 322 are connected in series to the comparison circuit 310. In addition, the current source action voltage becomes Vdsat similarly to the first embodiment.

[0187] Fig.19 is a diagram illustrating an example of a state of the in-comparator current source 320 when a low gain is set according to the third embodiment of the present technology.

[0188] When a low gain is set as shown as an example in the drawing, the comparator control section 240 brings the switch 332 into an open state and brings the switches 331 and 333 into a closed state. In this way, the source of the current source transistor 321 is connected to the ground terminal, and the drain of the current source transistor 322 is connected to the comparison circuit 310. Therefore, the current source transistors 321 and 322 are connected in parallel to the comparison circuit 310. In addition, similarly to the first embodiment, the current source action voltage becomes 0.5 Vdsat.

[0189] like Fig.18 and Fig.19 As shown in the example in, the connection destinations of the drain and source of the current source transistor 322 are fixed to the power supply side and the ground side when switching, so the connection destinations of the drain and the source are not reversed from the power supply side and the ground side to the ground side and the power supply side when switching. Therefore, the flow of surge current through the transistor can be suppressed. The same applies to the current source transistor 321.

[0190] In this way, according to the third embodiment of the present technology, the connection destinations of the drain and source of the current source transistor 322 are fixed to the power supply side and the ground side, and therefore the connection destinations of the drain and source are not reversed from the power supply side and the ground side to the ground side and the power supply side at the time of switching. Therefore, the flow of surge current via the current source transistor 322 can be suppressed.

[0191] [Modification example]

[0192] Although in the third embodiment described above, the comparator control section 240 controls the conductance of the current source 320 etc. in the comparator in two stages, there may be a case where the adjustment range of the current source operating voltage is lacking in the two-stage control. The comparator control section 240 according to the modified example of the third embodiment is different from the comparator control section of the third embodiment in that the conductance of the current source 320 etc. in the comparator is controlled in three stages.

[0193] Fig. 20 3 is a circuit diagram showing a configuration example of a comparator-internal current source 320 according to a modified example of the third embodiment of the present technology. The comparator-internal current source 320 in the modified example of the third embodiment is different from the comparator-internal current source in the first embodiment in that the comparator-internal current source 320 further includes current source transistors 323 and 324, and switches 334 to 339 are further included in the switch circuit 330.

[0194] In the modified example of the third embodiment, the connection configuration of the current source transistors 321 and 322 and the switches 331 to 333 is similar to that in the third embodiment.

[0195] The switch 334 is adapted to open and close the path between the source of the current source transistor 322 and the ground terminal according to the switch signal CSW4. The switch 335 is adapted to open and close the path between the source of the current source transistor 322 and the drain of the current source transistor 323 according to the switch signal CSW5. The switch 336 is adapted to open and close the path between the drain of the current source transistor 323 and the comparison circuit 310 according to the switch signal CSW6.

[0196] The switch 337 is adapted to open and close the path between the source of the current source transistor 323 and the ground terminal according to the switch signal CSW7. The switch 338 is adapted to open and close the path between the source of the current source transistor 323 and the drain of the current source transistor 324 according to the switch signal CSW8 from the vertical drive section 210. The switch 339 is adapted to open and close the path between the drain of the current source transistor 324 and the comparison circuit 310 according to the switch signal CSW9 ​​from the vertical drive section 210. The source of the current source transistor 324 is connected to the ground terminal.

[0197] Note that the configuration of the intra-comparator current source 350 is similar to the configuration of the intra-comparator current source 320 .

[0198] Fig.21 is a diagram illustrating an example of a state of the in-comparator current source 320 when a high gain is set according to a modified example of the third embodiment of the present technology.

[0199] As shown in the example in the figure, when a high gain is set, the comparator control section 240 causes switches 332, 335, and 338 to enter a closed state and causes the remaining switches to enter an open state. In this way, the source of the current source transistor 321 is connected to the drain of the current source transistor 322, and the source of the current source transistor 322 is connected to the drain of the current source transistor 323. In addition, the source of the current source transistor 323 is connected to the drain of the current source transistor 324. Therefore, the current source transistors 321 to 324 are connected in series to the comparison circuit 310.

[0200] Fig. 22 is a diagram illustrating an example of a state of the in-comparator current source 320 when an intermediate gain is set according to a modified example of the third embodiment of the present technology.

[0201] As shown in the example in the figure, when the intermediate gain is set, the comparator control section 240 brings the switches 332, 334, 336, and 338 into a closed state and brings the remaining switches into an open state. In this way, the source of the current source transistor 321 is connected to the drain of the current source transistor 322, and the source of the current source transistor 322 is connected to the ground terminal. In addition, the drain of the current source transistor 323 is connected to the comparison circuit 310, and the source of the current source transistor 323 is connected to the drain of the current source transistor 324. Therefore, the circuit in which the current source transistors 321 and 322 are connected in series and the circuit in which the current source transistors 323 and 324 are connected in series are connected in parallel.

[0202] Fig.23 is a diagram illustrating an example of a state of the in-comparator current source 320 when a low gain is set according to a modified example of the third embodiment of the present technology.

[0203] As shown in the example in the figure, when a low gain is set, the comparator control section 240 brings switches 331, 333, 334, 336, 337, and 339 into a closed state and brings the remaining switches into an open state. In this way, the sources of the current source transistors 321, 322, and 323 are connected to the ground terminal, and the drains of the current source transistors 322, 323, and 324 are connected to the comparison circuit 310. Therefore, the current source transistors 321 to 324 are connected in parallel.

[0204] like Figure 21 to Figure 23 As shown, the comparator control unit 240 can control the conductance of the current source 320 in the comparator in three stages by switching the connection mode. Therefore, compared with the case where the control is performed in two stages, the adjustment range of the current source operating voltage can be expanded. In addition, the connection destinations of the drain and source of the current source transistors 321 to 324 are fixed to the power supply side and the ground side when switching, so the surge current can be suppressed.

[0205] As described above, according to the modified example of the third embodiment of the present technology, the number of current source transistors is increased to four, the connection mode of which is switched by the comparator control section 240, and thus the current source operating voltage can be controlled in three stages. Therefore, compared with the case where the current source operating voltage is controlled in two stages, the VSL dynamic range and the RTS noise can be controlled to more appropriate values.

[0206] <4. Fourth embodiment>

[0207] In the first embodiment described above, the current source transistor 321 and the current source transistor 322 having a gate to which a constant bias voltage Vb is applied are provided in the comparator-internal current source 320. However, there is a concern that if the bias voltage Vb is a fixed value in this configuration, the current amount of the comparator-internal current source 320 may vary when the connection mode is switched. The solid-state imaging element 200 in the fourth embodiment is different from the solid-state imaging element in the first embodiment in that the current amount is kept constant using a current mirror circuit.

[0208] Fig.24 2 is a circuit diagram showing a configuration example of a comparator control section 240 according to a fourth embodiment of the present technology. The comparator control section 240 in the fourth embodiment includes a switch circuit 241 and a bias circuit 242.

[0209] The switch circuit 241 is adapted to control the conductance of the current sources 320 and 350 within the comparator using the switch signals CSW1 to CSW3 based on the control signal CTRL from the gain control section 220. In addition, the switch signals CSW1 to CSW3 are also provided to the bias circuit 242.

[0210] The bias circuit 242 includes a current source 243, current source transistors 244 and 245, and switches 246 to 248. As the current source transistors 244 and 245, for example, nMOS transistors are used.

[0211] The current source 243 is adapted to provide a constant reference signal. Current source transistors 244 and 245 are connected in series to the current source 243. In addition, the gates of the current source transistors 244 and 245 are connected to a connection node of the current source 243 and the current source transistor 244. In addition, the voltage of the gates of the current source transistors 244 and 245 is provided as a bias voltage Vb to the comparator-internal current source 320 and the comparator-internal current source 350 of each column.

[0212] The switch 246 is adapted to open and close the path between the connection node of the current source transistors 244 and 245 and the ground terminal according to the switch signal CSW1. The switch 247 is adapted to open and close the path between the source of the current source transistor 245 and the current source 243 according to the switch signal CSW2. The switch 248 is adapted to open and close the path between the source of the current source transistor 245 and the ground terminal according to the switch signal CSW3.

[0213] By the above configuration, the circuit including the bias circuit 242 and the in-comparator current sources 320 and 350 functions as a current mirror circuit. In the current mirror circuit, the reference current in the bias circuit 242 is copied by the in-comparator current sources 320 and 350. In this way, the amount of current in the in-comparator current sources 320 and 350 can be kept constant before and after switching.

[0214] Note that the second embodiment and the third embodiment and the modified example of the third embodiment can also be applied to the fourth embodiment. In this case, it is only necessary to change the circuit configuration of the bias circuit 242 according to the circuit of the comparator internal current source 320 in the second embodiment or the third embodiment or the modified example of the third embodiment.

[0215] As described above, according to the fourth embodiment of the present technology, by replicating the constant reference current in the bias circuit 242 through the current source 320 in the comparator, the bias circuit 242 operates as a current mirror circuit, and thus the amount of current in the current sources 320 and 350 in the comparator can be kept constant before and after switching.

[0216] <5. Fifth embodiment>

[0217] Although in the above-described first embodiment, the circuit outside the solid-state imaging element 200 sets the analog gain according to the illuminance, in this configuration, the amount of processing in the external circuit increases. The imaging device 100 in the fifth embodiment is different from the imaging device 100 in the first embodiment in that the solid-state imaging element 200 itself sets the analog gain according to the illuminance.

[0218] Fig.25 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a fifth embodiment of the present technology. The solid-state imaging element 200 in the fifth embodiment is different from the solid-state imaging element in the first embodiment in that the solid-state imaging element 200 includes a control section 221 and a register 222 instead of a gain control section 220 and a comparator control section 240.

[0219] In addition, the image processing section 290 in the fifth embodiment is different from the image processing section in the first embodiment in that the illuminance is measured based on the image data. The image processing section 290 uses statistical values ​​(such as average values ​​and median values), modes, etc. of pixel signals in the image data as illuminance to perform arithmetic operations. The image processing section 290 provides illuminance data indicating the illuminance to the control section 221.

[0220] The register 222 is used to store setting data associated with each of a plurality of illumination ranges. The illumination range includes, for example, a high illumination range higher than a predetermined value and a low illumination range equal to or less than a predetermined value. In addition, the setting data includes a control signal CTRL and a switch signal CSW for controlling the ramp generating unit 230. The control signal CTRL for generating a reference signal with a large amplitude (in other words, for setting a low gain) and the switch signal CSW for establishing a parallel connection are associated with a range of high illumination. On the other hand, the control signal CTRL for generating a reference signal with a small amplitude (in other words, for setting a high gain) and the switch signal CSW for establishing a series connection are associated with a range of low illumination.

[0221] The control section 221 is adapted to control the slope generation section 230 and the comparator 300 of each column based on the illumination data. The control section 221 provides the control signal CTRL to the slope generation section 230 and the switch signal CSW to the comparator 300 of each column according to the illumination reading control signal CTRL and the switch signal CSW from the register 222. The analog gain is controlled to a value corresponding to the illumination by the control signal. In addition, the conductance is controlled to a value corresponding to the analog gain by the switch signal CSW.

[0222] Note that the second embodiment, the third embodiment, and the fourth embodiment, and the modified example of the third embodiment can also be applied to the fifth embodiment. In the case of applying the second embodiment, setting data is held in the register 222 in association with each of the three illuminance ranges.

[0223] Fig.26 5 is a flowchart showing an example of the operation of the solid-state imaging element 200 according to the fifth embodiment of the present technology. For example, the operation is started when a predetermined application for capturing image data is executed.

[0224] First, the solid-state imaging element 200 performs a light measurement process for measuring the illumination of ambient light based on the image data (step S910). Then, the solid-state imaging element 200 controls the conductance of each of the current sources 320 and 350 in the comparator according to the measured illumination (step S920). The solid-state imaging element 200 performs an imaging process on the image data (step S930). After step S930, the solid-state imaging element 200 ends the operation for imaging.

[0225] Note that when a plurality of image data are continuously captured, steps S910 to S930 are repeatedly performed in synchronization with a vertical synchronization signal.

[0226] Fig. 27 is a flowchart showing an example of light measurement processing according to the fifth embodiment of the present technology. The vertical drive section 210 selects a row to be read (step S911) and exposes the row (step S912). The column ADC 270 performs AD conversion on the read row (step S913) and outputs row data according to the control performed by the horizontal drive section 280 (step S914). The vertical drive section 210 determines whether the read row is the last row (step S915). In the case where the read row is not the last row (step S915: No), the vertical drive section 210 repeats step S911 and the following steps.

[0227] On the other hand, if the read line is the last line (step S915: Yes), the image processing section 290 generates illuminance data based on the image data and outputs the illuminance data to the control section 221 (step S916). After step S916, the solid-state imaging element 200 ends the light measurement process.

[0228] Fig.28 is a flowchart showing an example of imaging processing according to the fifth embodiment of the present technology. The vertical drive section 210 selects a row to be read (step S931) and exposes the row (step S932). The column ADC 270 performs AD conversion on the read row (step S933) and outputs row data according to the control performed by the horizontal drive section 280 (step S934). The vertical drive section 210 determines whether the read row is the last row (step S935). In the case where the read row is not the last row (step S935: No), the vertical drive section 210 repeats step S931 and the following steps.

[0229] On the other hand, when the read line is the last line (step S935: Yes), the image processing section 290 generates image data by processing the line data and outputs the image data (step S936). After step S936, the solid-state imaging element 200 ends the light measurement process.

[0230] As described above, according to the fifth embodiment of the present technology, the image processing section 290 measures the illuminance, the control section 221 controls the analog gain according to the illuminance, and therefore the circuit outside the solid-state imaging element 200 does not need to control the analog gain according to the illuminance. Therefore, the amount of processing performed by the circuit outside the solid-state imaging element 200 can be reduced.

[0231] <6. Sixth embodiment>

[0232] In the first embodiment described above, the comparator control section 240 controls the conductance of the current sources 320 and 350 in the comparator to extend the VSL dynamic range. However, in the case of using a comparator including a differential amplifier circuit, the VSL dynamic range cannot be expanded without controlling the conductance of the current source outside the comparator. The solid-state imaging element 200 according to the sixth embodiment is different from the solid-state imaging element in the first embodiment in that the conductance of the current source outside the comparator is controlled.

[0233] Fig.29 2 is a block diagram showing a configuration example of a column ADC 270 according to a sixth embodiment of the present technology. The column ADC 270 in the sixth embodiment is different from the column ADC 270 in the first embodiment in that the column ADC 270 includes a comparator 400 instead of the comparator 300 .

[0234] The comparator 400 is adapted to compare the reference signal RMP inputted via the capacitor 271 with the pixel signal SIG inputted via the capacitor 274. The comparator 400 provides the comparison result COMP to the counter 272. A differential amplifier circuit (not shown) is provided inside the comparator 400, instead of Figure 6 Note that the differential amplifier circuit is an example of a comparison circuit described in the claims.

[0235] Furthermore, a load MOS current source 255 is connected to each vertical signal line 269. The circuit configuration of the load MOS current source 255 is similar to that of the in-comparator current source 320 in the first embodiment.

[0236] The comparator control section 240 in the sixth embodiment controls the conductance of the load MOS current source 255 according to the analog gain. When the analog gain is high, the comparator control section 240 suppresses the RTS noise by reducing the conductance of the load MOS current source 255. In addition, when the analog gain is low, the comparator control section 240 extends the VSL dynamic range by increasing the conductance of the load MOS current source 255. Therefore, the image quality of the image data can be improved.

[0237] As described above, according to the sixth embodiment of the present technology, the comparator control section 240 controls the conductance of the load MOS current source 255 according to the analog gain, and thus image quality can be improved when the comparator 400 including the differential amplifier circuit is used.

[0238] <7. Seventh Embodiment>

[0239] Although the reference signal is generated in the slope generating section 230 by the DAC in the aforementioned sixth embodiment, the amplitude control range may be insufficient using only the DAC. The solid-state imaging element 200 in the seventh embodiment is different from the solid-state imaging element 200 in the sixth embodiment in that the conductance of the current source in the slope generating section 230 is further controlled.

[0240] Fig.30 2 is a circuit diagram showing a configuration example of a slope generating section 230 according to a seventh embodiment of the present technology. The slope generating section 230 includes a slope signal generator 231, a source follower current source 232, and a source follower transistor 233. For example, a pMOS transistor is used as the source follower transistor 233.

[0241] The ramp signal generator 231 is adapted to generate a sawtooth waveform output signal Vout according to the control signal CTRL. For example, a DAC is used as the ramp signal generator 231. The ramp signal generator 231 provides the generated output signal Vout to the gate of the source follower transistor 233.

[0242] The source follower current source 232 and the source follower transistor 233 are connected in series with each other between the power supply terminal and the ground terminal.

[0243] The source follower transistor 233 is adapted to output a signal corresponding to the output signal Vout as a reference signal RMP from a source to the column ADC 270 .

[0244] The source follower current source 232 is adapted to generate a constant current. This circuit configuration of the source follower current source 232 is similar to the circuit configuration of the in-comparator current source 320 according to the first embodiment.

[0245] In addition, the comparator control section 240 according to the seventh embodiment controls the conductance of the source follower current source 232 according to the analog gain. In the case of low gain, the comparator control section 240 establishes a parallel connection of current source transistors in the source follower current source 232 to increase conductance. On the other hand, in the case of high gain, the comparator control section 240 establishes a series connection of current source transistors in the source follower current source 232 to reduce conductance. The amplitude control range can be increased by the conductance control achieved by the source follower current source 232.

[0246] Note that although the seventh embodiment has been applied to the column ADC 270 in the sixth embodiment, the present technology is not limited to this configuration, and the seventh embodiment can also be applied to the column ADC 270 in the first embodiment. In addition, the modified examples of the second to fifth embodiments or the third embodiment can also be applied to the seventh embodiment.

[0247] As described above, according to the seventh embodiment of the present technology, the comparator control section 240 further controls the conductance of the source follower current source 232 , and thus the amplitude control range of the reference signal RMP can be increased.

[0248] <8. Application examples for mobile objects>

[0249] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile body, an airplane, a drone, a ship, or a robot).

[0250] Fig.31 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0251] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.31In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0252] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0253] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0254] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image an image outside the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a process of detecting an object such as a person, a vehicle, an obstacle, a sign, text on the road surface, or a process of detecting the distance thereof.

[0255] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0256] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0257] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0258] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0259] In addition, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0260] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device that can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.31 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0261] Fig.32 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0262] exist Fig.32 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0263] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper portion of the windshield inside the vehicle. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 disposed to the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0264] By the way, Fig.32 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0265] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0266] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the leading vehicle, which specifically exists on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the following distance to keep in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control for automatic driving that allows the vehicle to automatically travel without relying on the driver's operation, etc. can be performed.

[0267] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0268] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaging images of the imaging units 12101 to 12104 as infrared cameras and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points indicating the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon indicating a pedestrian or the like is displayed at a desired position.

[0269] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 in FIG. 1 can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, a captured image that is easier to see can be obtained, and thus the driver's fatigue can be reduced.

[0270] Note that the above-described embodiments illustrate examples for implementing the present technology, and each item in the embodiments has a corresponding relationship with the invention-specific item in the claims. Similarly, each invention-specific item in the claims has a corresponding relationship with the item with the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be implemented by making various modifications to the embodiments without departing from its gist.

[0271] Note that the effects described in this specification are shown only as examples and are not limited thereto, and there may be other effects.

[0272] Note that the present technology may also be configured as follows.

[0273] (1) A solid-state imaging element comprising:

[0274] A current source, generating a constant current;

[0275] A pixel circuit generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source;

[0276] a comparison circuit that amplifies the pixel signal at a predetermined amplification ratio and compares the amplified pixel signal with a predetermined reference signal;

[0277] a control section that reduces conductance when the amplification factor increases; and

[0278] The counter counts the count value during a period until the comparison result of the comparison circuit is inverted and outputs the count value.

[0279] (2) The solid-state imaging element according to (1), wherein the current source includes:

[0280] a plurality of transistors; and

[0281] A switching circuit switches the connection mode of multiple transistors.

[0282] (3) The solid-state imaging element according to (2),

[0283] wherein the plurality of transistors include a first transistor and a second transistor connected in series to the comparison circuit, and

[0284] The switching circuit includes:

[0285] a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal;

[0286] a second switch connecting the source of the second transistor to the comparison circuit; and

[0287] The third switch connects the source of the second transistor to the ground terminal.

[0288] (4) The solid-state imaging element according to (2),

[0289] wherein the plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to the comparison circuit, and

[0290] The switching circuit includes:

[0291] a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal;

[0292] a second switch connecting a connection node between the second transistor and the third transistor to a comparison circuit;

[0293] a third switch connecting a connection node between the second transistor and the third transistor to a ground terminal;

[0294] a fourth switch connecting a connection node between the third transistor and the fourth transistor to a comparison circuit;

[0295] a fifth switch connecting a connection node between the third transistor and the fourth transistor to a ground terminal;

[0296] a sixth switch connecting the source of the fourth transistor to the comparison circuit; and

[0297] A seventh switch connects the source of the fourth transistor to the ground terminal.

[0298] (5) The solid-state imaging element according to (2),

[0299] Wherein, the plurality of transistors include:

[0300] a first transistor having a drain connected to the comparison circuit; and

[0301] a second transistor having a source connected to a predetermined ground terminal; and

[0302] The switching circuit includes:

[0303] a first switch connecting the source of the first transistor to a ground terminal;

[0304] a second switch connecting the source of the first transistor to the drain of the second transistor; and

[0305] The third switch connects the drain of the second transistor to the comparison circuit.

[0306] (6) The solid-state imaging element according to (2),

[0307] Wherein, the plurality of transistors include:

[0308] a first transistor having a drain connected to the comparison circuit;

[0309] a second transistor and a third transistor; and

[0310] a fourth transistor having a source connected to a predetermined ground terminal; and

[0311] The switching circuit includes:

[0312] a first switch connecting the source of the first transistor to a ground terminal;

[0313] a second switch connecting the source of the first transistor to the drain of the second transistor;

[0314] a third switch connecting the drain of the second transistor to the comparison circuit;

[0315] a fourth switch connecting the source of the second transistor to the ground terminal;

[0316] a fifth switch connecting the source of the second transistor to the drain of the third transistor;

[0317] a sixth switch, connecting the drain of the third transistor to the comparison circuit;

[0318] a seventh switch connecting the source of the third transistor to the ground terminal;

[0319] an eighth switch connecting the source of the third transistor to the drain of the fourth transistor; and

[0320] A ninth switch connects the drain of the fourth transistor to the comparison circuit.

[0321] (7) The solid-state imaging element according to any one of (1) to (6), further comprising:

[0322] Bias circuit, generates a constant reference current,

[0323] Here, the reference current is copied by the current source.

[0324] (8) The solid-state imaging element according to any one of (1) to (7), further comprising:

[0325] an image processing unit that measures illumination based on the image data of the array count value,

[0326] The control unit controls the amplification factor to a value corresponding to the illumination.

[0327] (9) The solid-state imaging element according to any one of (1) to (8),

[0328] The pixel circuit is connected to the comparison circuit via a vertical signal line, and

[0329] The comparison circuit is inserted between the vertical signal line and the current source.

[0330] (10) The solid-state imaging element according to any one of (1) to (8),

[0331] The pixel circuit is connected to the comparison circuit via a vertical signal line, and

[0332] A current source is connected to the vertical signal line.

[0333] (11) The solid-state imaging element according to any one of (1) to (10), further comprising:

[0334] a generator that generates an output signal having a sawtooth waveform; and

[0335] The source follower transistor outputs a signal corresponding to the output signal from the source as a reference signal.

[0336] Among them, the current source includes:

[0337] a current source in the comparator, connected to the comparison circuit; and

[0338] A source follower current source is connected to the source of the source follower transistor.

[0339] (12) An imaging device comprising:

[0340] A current source, generating a constant current;

[0341] A pixel circuit generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source;

[0342] a comparison circuit that amplifies the pixel signal at a predetermined amplification ratio and compares the amplified pixel signal with a predetermined reference signal;

[0343] a control unit that reduces conductance when amplification increases;

[0344] a counter that counts and outputs a count value during a period until a comparison result of the comparison circuit is inverted; and

[0345] The storage unit stores image data in which digital signals indicating count values ​​are arranged.

[0346] (13) A method for controlling a solid-state imaging element, comprising:

[0347] A pixel signal generating process, in which a pixel signal having a voltage higher than a predetermined lower limit voltage is generated by a pixel circuit according to the conductance of a current source generating a constant current;

[0348] a comparison process of amplifying the pixel signal at a predetermined amplification ratio and comparing the amplified pixel signal with a predetermined reference signal;

[0349] controlling the process to reduce conductance as amplification increases; and

[0350] A counting process that counts a count value during a period until a comparison result of the comparison circuit is inverted and outputs the count value.

[0351] (14) A light detection device comprising:

[0352] Pixel, outputs pixel signal according to incident light;

[0353] Vertical signal lines, transmitting pixel signals;

[0354] a comparator including a transistor, either one of a source and a drain of the transistor being connected to the vertical signal line, and a gate of the transistor receiving a reference signal; and

[0355] A current source connected to the other of the source and drain of the transistor,

[0356] Among them, the current source includes:

[0357] Multiple transistors, and

[0358] A switching circuit switches the connection mode of multiple transistors.

[0359] (15) The light detection device according to (14),

[0360] wherein the plurality of transistors include a first transistor and a second transistor connected in series to the comparison circuit, and

[0361] The switching circuit includes:

[0362] a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal;

[0363] a second switch connecting the source of the second transistor to the comparison circuit; and

[0364] The third switch connects the source of the second transistor to the ground terminal.

[0365] (16) The light detection device according to (14),

[0366] wherein the plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to the comparison circuit, and

[0367] The switching circuit includes:

[0368] a first switch connecting a connection node of the first transistor and the second transistor to a predetermined ground terminal;

[0369] a second switch connecting a connection node between the second transistor and the third transistor to a comparison circuit;

[0370] a third switch connecting a connection node between the second transistor and the third transistor to a ground terminal;

[0371] a fourth switch connecting a connection node between the third transistor and the fourth transistor to a comparison circuit;

[0372] a fifth switch connecting a connection node between the third transistor and the fourth transistor to a ground terminal;

[0373] a sixth switch connecting the source of the fourth transistor to the comparison circuit; and

[0374] A seventh switch connects the source of the fourth transistor to the ground terminal.

[0375] (17) The light detection device according to (14),

[0376] Wherein, the plurality of transistors include:

[0377] a first transistor having a drain connected to the comparison circuit; and

[0378] a second transistor having a source connected to a predetermined ground terminal; and

[0379] The switching circuit includes:

[0380] a first switch connecting the source of the first transistor to a ground terminal;

[0381] a second switch connecting the source of the first transistor to the drain of the second transistor; and

[0382] The third switch connects the drain of the second transistor to the comparison circuit.

[0383] (18) The light detection device according to (14),

[0384] Wherein, the plurality of transistors include:

[0385] a first transistor having a drain connected to the comparison circuit;

[0386] a second transistor and a third transistor; and

[0387] a fourth transistor having a source connected to a predetermined ground terminal; and

[0388] The switching circuit includes:

[0389] a first switch connecting the source of the first transistor to a ground terminal;

[0390] a second switch connecting the source of the first transistor to the drain of the second transistor;

[0391] a third switch connecting the drain of the second transistor to the comparison circuit;

[0392] a fourth switch connecting the source of the second transistor to the ground terminal;

[0393] a fifth switch connecting the source of the second transistor to the drain of the third transistor;

[0394] a sixth switch, connecting the drain of the third transistor to the comparison circuit;

[0395] a seventh switch connecting the source of the third transistor to the ground terminal;

[0396] an eighth switch connecting the source of the third transistor to the drain of the fourth transistor; and

[0397] A ninth switch connects the drain of the fourth transistor to the comparison circuit.

[0398] Reference Mark List

[0399] 100 Imaging Device

[0400] 110 Optical Department

[0401] 120 DSP circuit

[0402] 130 Display unit

[0403] 140 Operation Department

[0404] 150 Bus

[0405] 160 frame memory

[0406] 170 Storage

[0407] 180 Power Supply

[0408] 200 Solid-state imaging element

[0409] 201 Optical Receiver Chip

[0410] 202 Circuit Chip

[0411] 210 vertical drive unit

[0412] 220 Gain control unit

[0413] 221 Control Department

[0414] 222 Registers

[0415] 230 Slope Generation Unit

[0416] 231 Ramp signal generator

[0417] 232 Source Follower Current Source

[0418] 233 Source Follower Transistor

[0419] 240 Comparator control unit

[0420] 241 Switching Circuit

[0421] 242 Bias Circuit

[0422] 243 Current Source

[0423] 244, 245, 321 to 324 Current source transistors

[0424] 246 to 248, 331 to 339 Switch

[0425] 250 pixel array unit

[0426] 255 Load MOS Current Source

[0427] 260 pixel circuit

[0428] 261 Photoelectric conversion element

[0429] 262 Transfer transistor

[0430] 263 Reset transistor

[0431] 264 floating diffusion layer

[0432] 265 Amplifier Transistor

[0433] 266 Select transistor

[0434] 270 columns ADC

[0435] 271, 274, 313 capacitors

[0436] 272 Counter

[0437] 273 Latch

[0438] 280 Horizontal drive unit

[0439] 290 Image Processing Department

[0440] 300, 400 Comparator

[0441] 310 Comparison Circuit

[0442] 311 Input transistor

[0443] 312 Auto zero switch

[0444] 314 Clamp Transistor

[0445] 315 Output transistor

[0446] 320, 350 Current source in comparator

[0447] 330 Switching Circuit

[0448] 12031 Imaging Department.

Claims

1. A solid-state imaging element, comprising: A current source, generating a constant current; a pixel circuit for generating a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source; a comparison circuit, amplifying the pixel signal at a predetermined amplification ratio and comparing the amplified pixel signal with a predetermined reference signal; a control unit that reduces the conductance when the amplification rate increases; as well as A counter counts a count value during a period until a comparison result of the comparison circuit is inverted and outputs the count value.

2. The solid-state imaging element according to claim 1, wherein The current source comprises: a plurality of transistors; and The switch circuit switches the connection mode of the plurality of transistors.

3. The solid-state imaging element according to claim 2, in, The plurality of transistors include a first transistor and a second transistor connected in series to the comparison circuit, The switch circuit comprises: a first switch connecting a connection node between the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a source of the second transistor to the comparison circuit; and A third switch connects the source of the second transistor to the ground terminal.

4. The solid-state imaging element according to claim 2, in, The plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to the comparison circuit, and The switch circuit comprises: a first switch connecting a connection node between the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a connection node between the second transistor and the third transistor to the comparison circuit; a third switch connecting a connection node between the second transistor and the third transistor to the ground terminal; a fourth switch, connecting a connection node between the third transistor and the fourth transistor to the comparison circuit; a fifth switch connecting a connection node between the third transistor and the fourth transistor to the ground terminal; a sixth switch, connecting the source of the fourth transistor to the comparison circuit; and A seventh switch connects the source of the fourth transistor to the ground terminal.

5. The solid-state imaging element according to claim 2, in, The plurality of transistors include: a first transistor, a drain of the first transistor being connected to the comparison circuit; and a second transistor having a source connected to a predetermined ground terminal; and The switch circuit comprises: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; and A third switch connects the drain of the second transistor to the comparison circuit.

6. The solid-state imaging element according to claim 2, in, The plurality of transistors include: a first transistor, wherein a drain of the first transistor is connected to the comparison circuit; a second transistor and a third transistor; and a fourth transistor having a source connected to a predetermined ground terminal; and The switch circuit comprises: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; a third switch, connecting the drain of the second transistor to the comparison circuit; a fourth switch connecting the source of the second transistor to the ground terminal; a fifth switch, connecting the source of the second transistor to the drain of the third transistor; a sixth switch, connecting the drain of the third transistor to the comparison circuit; a seventh switch, connecting the source of the third transistor to the ground terminal; an eighth switch connecting the source of the third transistor to the drain of the fourth transistor; and A ninth switch connects the drain of the fourth transistor to the comparison circuit.

7. The solid-state imaging element according to claim 1, further comprising: Bias circuit, generates a constant reference current, Wherein, the reference current is copied by the current source.

8. The solid-state imaging element according to claim 1, further comprising: an image processing unit that measures illuminance based on the image data in which the count values ​​are arranged, The control unit controls the amplification factor to a value corresponding to the illumination.

9. The solid-state imaging element according to claim 1, in, The pixel circuit is connected to the comparison circuit via a vertical signal line, and The comparison circuit is inserted between the vertical signal line and the current source.

10. The solid-state imaging element according to claim 1, in, The pixel circuit is connected to the comparison circuit via a vertical signal line, and The current source is connected to the vertical signal line.

11. The solid-state imaging element according to claim 1, further comprising: a generator, generating an output signal having a sawtooth waveform; as well as a source follower transistor that outputs a signal corresponding to the output signal from a source as the reference signal, Wherein, the current source comprises: a current source in the comparator, connected to the comparison circuit; and A source follower current source is connected to the source of the source follower transistor.

12. An imaging device, comprising: A current source, generating a constant current; a pixel circuit for generating a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source; a comparison circuit, amplifying the pixel signal at a predetermined amplification ratio and comparing the amplified pixel signal with a predetermined reference signal; a control unit that reduces the conductance when the amplification rate increases; a counter that counts and outputs a count value during a period until a comparison result of the comparison circuit is inverted; and The storage unit stores image data in which the digital signal indicating the count value is arranged.

13. A method for controlling a solid-state imaging element, comprising: A pixel signal generating process, in which a pixel signal having a voltage higher than a predetermined lower limit voltage is generated by a pixel circuit according to the conductance of a current source generating a constant current; a comparison process of amplifying the pixel signal at a predetermined amplification ratio and comparing the amplified pixel signal with a predetermined reference signal; a control process for reducing the conductance when the amplification rate increases; as well as A counting process of counting a count value within a period until a comparison result of the comparison circuit is inverted and outputting the count value.

14. A light detection device comprising: Pixel, outputs pixel signal according to incident light; A vertical signal line, transmitting the pixel signal; a comparator including a transistor, any one of a source and a drain of the transistor being connected to the vertical signal line, and a gate of the transistor receiving a reference signal; as well as a current source connected to the other of the source and the drain of the transistor, Wherein, the current source comprises: a plurality of transistors; and The switch circuit switches the connection mode of the plurality of transistors.

15. The light detection device according to claim 14, in, The plurality of transistors include a first transistor and a second transistor connected in series to a comparison circuit, The switch circuit comprises: a first switch connecting a connection node between the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a source of the second transistor to the comparison circuit; and A third switch connects the source of the second transistor to the ground terminal.

16. The light detection device according to claim 14, in, The plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series to the comparison circuit, and The switch circuit comprises: a first switch connecting a connection node between the first transistor and the second transistor to a predetermined ground terminal; a second switch connecting a connection node between the second transistor and the third transistor to the comparison circuit; a third switch connecting a connection node between the second transistor and the third transistor to the ground terminal; a fourth switch, connecting a connection node between the third transistor and the fourth transistor to the comparison circuit; a fifth switch connecting a connection node between the third transistor and the fourth transistor to the ground terminal; a sixth switch, connecting the source of the fourth transistor to the comparison circuit; and A seventh switch connects the source of the fourth transistor to the ground terminal.

17. The light detection device according to claim 14, in, The plurality of transistors include: a first transistor, a drain of the first transistor being connected to a comparison circuit; and a second transistor having a source connected to a predetermined ground terminal; and The switch circuit comprises: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; and A third switch connects the drain of the second transistor to the comparison circuit.

18. The light detection device according to claim 14, in, The plurality of transistors include: a first transistor, wherein a drain of the first transistor is connected to a comparison circuit; a second transistor and a third transistor; and a fourth transistor having a source connected to a predetermined ground terminal; and The switch circuit comprises: a first switch connecting the source of the first transistor to the ground terminal; a second switch connecting the source of the first transistor to the drain of the second transistor; a third switch, connecting the drain of the second transistor to the comparison circuit; a fourth switch connecting the source of the second transistor to the ground terminal; a fifth switch, connecting the source of the second transistor to the drain of the third transistor; a sixth switch, connecting the drain of the third transistor to the comparison circuit; a seventh switch, connecting the source of the third transistor to the ground terminal; an eighth switch connecting the source of the third transistor to the drain of the fourth transistor; and A ninth switch connects the drain of the fourth transistor to the comparison circuit.

Images