A control assembly and server

Abstract

The application discloses a control assembly and a server, relates to the technical field of circuits, and can realize power control of a plurality of disks and a single disk of a server system through timing control of a backboard controller, and reduces hardware cost; the control assembly comprises a backboard controller, a switch unit, a plurality of hard disk connectors and a plurality of hard disks; a power supply end of the backboard controller is electrically connected with a first power supply end, a control end of the backboard controller is connected with an enable end of the switch unit, and one output end of the backboard controller is connected with an input end of one hard disk connector; an input end of the switch unit is electrically connected with a second power supply end, and an output end of the switch unit is used for connecting a power supply end of the hard disk; at least two output ends of the hard disk connector are used for respectively connecting a power supply end and a control end of the hard disk; the backboard controller is configured to output a first control signal through the control end to control the switch unit to be turned on, and output a second control signal to the hard disk connector through the output end to control power-on and power-off of the hard disk.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more particularly to a control component and a server. Background Technology

[0002] With the rapid development of semiconductor technology, solid-state drives (SSDs) are increasingly replacing traditional hard disk drives (HDDs) and are widely used in servers and storage devices due to their significant advantages in read / write speeds, power consumption, noise, and reliability. In particular, with the continuous evolution of NAND flash memory chip manufacturing processes and stacking layers, the capacity density of a single chip is constantly increasing, leading to a continuous increase in the capacity of a single SSD and a corresponding decrease in the cost per unit capacity. This further accelerates the adoption of SSDs in high-performance computing scenarios such as data centers.

[0003] Under this trend, a single server system often needs to integrate 12, 24, or even 40 or more SSDs to meet the demand for high-performance storage. On the one hand, such large-scale deployment will generate huge instantaneous surge currents if all SSDs are powered on at the same time, which will seriously impact the server power system. On the other hand, when a single SSD malfunctions, the operation and maintenance personnel need to be able to perform independent power-off and reset operations on it without affecting other normally functioning SSDs.

[0004] Currently, traditional solutions utilize Complex Programmable Logic Devices (CPLDs) on the server backplane, directly controlling multiple electronic fuse power switches via their general purpose input / output (GPIO) pins. Specifically, each SSD bay is equipped with an independent electronic fuse, and one GPIO pin of the CPLD controls the enable terminal of one electronic fuse, thereby switching the 12V power supply to the corresponding SSD on and off. However, each SSD bay requires an eFuse power switch chip, resulting in high costs; furthermore, the CPLD consumes too many GPIO pins, hindering further expansion. Summary of the Invention

[0005] This application provides a control component and server that, through the timing control of a backplane controller, enables power control of multiple disks and a single disk in a server system, thereby reducing hardware costs.

[0006] This application provides a control component, comprising: a backplane controller, a switching unit, multiple hard disk connectors, and multiple hard disks; the power supply terminal of the backplane controller is electrically connected to a first power supply terminal, the control terminal of the backplane controller is connected to the enable terminal of the switching unit, and one output terminal of the backplane controller is connected to the input terminal of one of the hard disk connectors; the input terminal of the switching unit is electrically connected to a second power supply terminal, and the output terminal of the switching unit is used to connect to the power supply terminal of the hard disk; at least two output terminals of the hard disk connectors are used to connect to the power supply terminal and the control terminal of the hard disk, respectively; the backplane controller is configured to output a first control signal through the control terminal to control the switching unit to conduct; and to output a second control signal through the output terminal to the hard disk connectors to control the power-on and power-off of the hard disks.

[0007] This application also provides a server, including: a control component and a motherboard, the motherboard being connected to the control component; the motherboard being configured to power the control component.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the control process of any of the above-described control components when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the control process of any of the above-mentioned control components.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the control process of any of the aforementioned control components.

[0011] This application provides a control component that introduces a centrally managed backplane controller and uses a shared switching unit to provide main power to multiple hard drives. Simultaneously, it utilizes independent idle pins on the hard drive connectors to transmit precise power control signals to each hard drive. Firstly, this solution significantly reduces hardware cost and complexity, eliminating the need for individual electronic fuses or power switches for each hard drive, requiring only a few components to manage the entire hard drive array. Secondly, it achieves precise and flexible power management. The backplane controller can programmatically power on all hard drives sequentially via a second control signal, effectively suppressing inrush current and independently powering down or resetting any designated hard drive, facilitating fault isolation and maintenance, thereby improving system stability and reliability. Finally, the architecture of this application simplifies layout, improves system maintainability and scalability, and provides a cost-effective and highly controllable power management path for high-density server storage solutions. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of an existing control component;

[0014] Figure 2 This is a schematic diagram of the structure of a control component provided in an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of a conventional hard drive powering on.

[0016] Figure 4 A schematic diagram illustrating the power-on of a hard disk as provided in an embodiment of this application;

[0017] Figure 5 A timing diagram of hard disk power-on is provided for an embodiment of this application;

[0018] Figure 6 This is a schematic diagram of the structure of a hard disk provided in an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of another hard disk structure provided in an embodiment of this application. Attached image description:

[0021] 1. Backplane controller; 2. Switching unit; 3. Hard disk connector; 4. Hard disk; 41. Backup power management module; 42. Logic control module; 43. Main controller; 44. Voltage divider circuit; 45. First switching circuit; 46. Second switching circuit; R1, First resistor; R2, Second resistor; R1, Third resistor; R1, Fourth resistor; R1, Fifth resistor; R1, Sixth resistor; R7, Seventh resistor; Rx, Enable resistor; Q1, First switching transistor; Q2, Second switching transistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; 100. Control component. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Currently, a single server system often needs to integrate 12, 24, or even 40 or more SSDs to meet the demand for high-performance storage. On the one hand, such large-scale deployment will generate huge instantaneous surge currents if all SSDs are powered on at the same time, which will seriously impact the server power system. On the other hand, when a single SSD malfunctions, the operation and maintenance personnel need to be able to perform independent power-off and reset operations on it without affecting other normally functioning SSDs.

[0026] Currently, the mainstream solutions in the industry are such as Figure 1 As shown, traditional solutions utilize Complex Programmable Logic Devices (CPLDs) on the server backplane, directly controlling multiple electronic fuse power switches via their general purpose input / output (GPIO) pins. Specifically, each SSD bay is equipped with an independent electronic fuse, and one GPIO pin of the CPLD controls the enable terminal of one electronic fuse, thereby switching the 12V power supply to the corresponding SSD on and off. However, each SSD bay requires an eFuse power switch chip. As a high-performance power management device integrating multiple protection functions, the eFuse has a high unit price. In large-scale deployments (such as 40 bays), the large number of eFuses required will significantly increase the overall bill of materials (BOM) cost of the system.

[0027] Meanwhile, the GPIO pins of a CPLD are limited system resources; using a one-to-one control method means that controlling N SSDs requires occupying N GPIO pins. This greatly consumes the CPLD's interface capabilities, limits its ability to implement other monitoring or management functions on the backplane, and weakens the system's scalability.

[0028] Based on this, this application provides a control component, such as... Figure 2 As shown, the control assembly 100 includes: a backplane controller 1, a switch unit 2, multiple hard disk 4 connectors 3 and multiple hard disks 4.

[0029] The power supply terminal of the backplane controller 1 is electrically connected to the first power supply terminal, the control terminal of the backplane controller 1 is connected to the enable terminal of the switch unit 2, and one output terminal of the backplane controller 1 is connected to the input terminal of a hard disk 4 connector 3.

[0030] The input terminal of the switch unit 2 is electrically connected to the second power supply terminal, and the output terminal of the switch unit 2 is used to connect to the power supply terminal of the hard disk 4; at least two output terminals of the hard disk 4 connector 3 are used to connect to the power supply terminal and the control terminal of the hard disk 4 respectively.

[0031] The backplane controller 1 is configured to output a first control signal through the control terminal to control the switching unit 2 to conduct; and to output a second control signal through the output terminal to the hard disk 4 connector 3 to control the power-on and power-off of the hard disk 4.

[0032] The backplane controller 1 has multiple output terminals, each output terminal corresponds to a hard disk 4 connector 3, and each hard disk 4 connector 3 is connected to a hard disk 4.

[0033] For example, backplane controller 1 is a Complex Programmable Logic Device (CPLD). Its power supply is connected to the first power supply (+3.3V) from the server power supply, which is present when the system is in standby mode to ensure the initialization of the CPLD.

[0034] Switching unit 2 uses an electronic fuse chip. The input terminal of switching unit 2 is connected to the second power supply terminal (+12V) from the server main power supply. The output terminal of switching unit 2 is connected to the power supply network of the common hard disk 4 on the backplane. The enable terminal of switching unit 2 is connected to a control terminal of the CPLD.

[0035] Hard drive connector 3 is a female connector for multiple U.2 interfaces. Each U.2 connector has multiple pins, of which: two power pins are connected to the common P12V_SSD network on the backplane as power supply terminals. One reserved pin is used as a control terminal, which is connected to a specific output terminal of the CPLD via wiring, for example, GPIO1 corresponds to connector 1, GPIO2 corresponds to connector 2, and so on.

[0036] Hard drive 4 is a U.2 form factor solid-state drive 4 that supports the NVMe protocol, and the corresponding pins of its male connector match the backplane connector.

[0037] The specific control process and working logic are as follows:

[0038] Initialization and default state: After the server is connected to the main power supply, +3.3V powers on the backplane controller 1 and completes initialization; the backplane controller 1 sets the control terminal to low level, so that the switch unit 2 is in the off state, and the hard disk 4 is not powered; +12V powers on the switch unit 2, but the switch unit 2 does not conduct.

[0039] Simultaneously, the backplane controller 1 pulls all connector control outputs (such as GPIO1, GPIO2, ...) to a high level through a pull-up resistor; therefore, the second control signal sent to each hard drive 4 is high by default. This state means that the power is kept off.

[0040] During the power supply network activation phase, the backplane controller 1 sets its control terminal to a high level and outputs the first control signal, turning on the control switch unit 2. The +12V power supply is output through the switch unit 2 to the hard drive 4 connector 3, providing voltage to the power supply terminals of all hard drive 4 connector 3. At this time, all hard drives 4 are powered on, but because the control terminal of the hard drive 4 is at a high level, internal power management is still disabled, and the hard drives 4 are in a standby power-on state.

[0041] Backplane controller 1 starts executing the power-on sequence and outputs a second control signal to hard disk 4 connector 3 through the output terminal to control the power-on of hard disk 4.

[0042] When a faulty hard drive 4 needs to be restarted or isolated, the backplane controller 1 simply sets the corresponding output terminal back to a high level. After receiving the high-level signal, the control terminal of the faulty hard drive 4 executes the power-down procedure and automatically shuts down its internal power upon completion. This process does not affect the normal operation of other hard drives 4. When needed, the backplane controller 1 can pull the level of the corresponding output terminal low again to power on the hard drive 4.

[0043] In some embodiments, the switching unit 2 is not limited to an electronic fuse and can be constructed using a high-current MOSFET in conjunction with a driving circuit. The control terminal of the backplane controller 1 sends a first control signal to control the gate of the MOSFET through the driving circuit, thereby achieving on / off control of the entire power supply network. Furthermore, the MOSFET solution is less expensive.

[0044] In some embodiments, the hard disk 4 connector 3 is not limited to a U.2 interface, but can be an M.2 interface. Its connector usually also has undefined reserved pins, that is, idle pins.

[0045] In some embodiments, the trigger levels for power-on and power-off can be customized. In the above embodiments, a low-level signal is used for power-on and a high-level signal is used for power-off. The pull-up resistor can be changed to a pull-down resistor to make the default signal low, and a high-level signal for power-on and a low-level signal for power-off can be agreed upon. The initialization logic and timing of the backplane controller 1 can be adjusted accordingly; the main point is that the backplane controller 1 can control the level state sequence of this signal through programming.

[0046] In some embodiments, the control component 100 further includes a step-down module for reducing the operating voltage of the backplane controller 1 from the 12V power supply voltage from the motherboard to power the backplane controller 1.

[0047] In summary, this application provides a control component 100 that, by introducing a centrally managed backplane controller 1, uses a shared switching unit 2 to provide main power to multiple hard drives 4, while simultaneously utilizing independent idle pins on the hard drive 4 connector 3 to transmit precise power control signals to each hard drive 4. Firstly, this solution significantly reduces hardware costs and complexity, eliminating the need for individual electronic fuses or power switches for each hard drive 4, requiring only a few components to manage the entire hard drive 4 array. Secondly, it achieves precise and flexible power management; the backplane controller 1 can program the second control signal to sequentially power on all hard drives 4, effectively suppressing inrush current and independently powering down or resetting any designated hard drive 4, facilitating fault isolation and maintenance, thereby improving system stability and reliability. Finally, the architecture of this application simplifies layout, improves system maintainability and scalability, and provides a cost-effective and highly controllable power management path for high-density server storage solutions.

[0048] In some embodiments, the backplane controller 1 is configured to output a command to power on the hard disk 4 by driving its output to a first level.

[0049] In the first case: the first level is low. When a specific hard disk 4 needs to be powered on, the backplane controller 1 configures the corresponding output terminal to output mode and drives it to output to low level, which is the first level. This low level signal is transmitted to the specific hard disk 4 through the reserved pin (idle pin) of the hard disk 4 connector 3.

[0050] The logic circuit inside a specific hard drive 4 detects that the signal received by the control terminal has become a valid low level, and then starts the internal power-on timing to complete the power-on process.

[0051] The second scenario: The first level is high. When a specific hard drive 4 needs to be powered on, the backplane controller 1 configures the corresponding output terminal to output mode and drives it to output to a high level, which is the first level. This high-level signal is transmitted to the specific hard drive 4 through the reserved pin (idle pin) of the hard drive 4 connector 3.

[0052] The logic circuit inside a specific hard drive 4 detects that the signal received by the control terminal has become a valid high level, and then starts the internal power-on timing to complete the power-on process.

[0053] like Figure 2 As shown, the control component 100 also includes a plurality of first resistors R1.

[0054] The first end of each first resistor R1 is electrically connected to the third power supply terminal, and the second end of each first resistor R1 is electrically connected to one output terminal of the backplane controller 1.

[0055] The first resistor R1 is configured to maintain the second control signal at the second level when the backplane controller 1 is not driven.

[0056] The second control signal is maintained at the second level, controlling the hard disk 4 to remain in the power-off state or enter the power-off state.

[0057] by Figure 2 For example, the third power supply terminal is the power supply terminal, and the first resistor R1 is a pull-up resistor. At this time, the first level is low and the second level is high.

[0058] During the initialization phase, all output terminals of the backplane controller 1 are pulled up by the first resistor R1 and are at a high level, that is, the second control signal is maintained at the second level, and the hard disk 4 is in a power-off state or enters a power-off state; during the power-on phase, the backplane controller 1 drives the designated output terminal to a low level, that is, the first level, and issues a power-on command.

[0059] In some embodiments, the third power supply terminal can be a ground terminal, and the first resistor R1 is a pull-down resistor. At this time, the first level is high and the second level is low. During the initialization phase, all output terminals of the backplane controller 1 are at a low level due to the pull-down of the first resistor R1, that is, the second control signal is maintained at the second level, and the hard disk 4 is in a power-off state or enters a power-off state. During the power-on phase, the backplane controller 1 drives the designated output terminal to a high level, that is, the first level, and issues a power-on command.

[0060] In some embodiments, the pull-up or pull-down resistors provided at each output terminal of the backplane controller 1, although being the first resistors, have different resistance values, as shown in the reference. Figure 2 It can be seen that: the first resistor is labeled R1-1; the second resistor is labeled R1-2; and the nth resistor is labeled R1-n.

[0061] In some embodiments, the control component 100 further includes an enable resistor Rx.

[0062] The first end of the enable resistor Rx is electrically connected to the control terminal of the backplane controller 1, and the second end of the enable resistor Rx is grounded.

[0063] Reference Figure 2 As can be seen, the enable resistor is a pull-down resistor. When the backplane controller has not been initialized, the program has not run, or the control terminal is in a high impedance state, the level of this line is floating and is easily triggered by external electromagnetic interference. By connecting this enable resistor Rx to ground GND, the default level of the control terminal is forcibly pulled low. This ensures that the corresponding functional module will not be powered on erroneously during the initial power-up of the system or in abnormal conditions, thus improving the stability and reliability of the system. At the same time, the enable resistor Rx also limits the current flowing out of the backplane controller, providing a certain degree of short-circuit protection.

[0064] By setting pull-down or pull-up resistors between the output of the backplane controller 1 and the fixed power supply, it is ensured that when the backplane controller 1 is not initialized, malfunctions, or is in a reset state, the second control signal output to the hard disk 4 can be automatically clamped to a certain safe level, namely the second level. This level is predefined as an instruction to command the hard disk 4 to maintain or enter a power-off state, thereby fundamentally eliminating the risk of the hard disk 4 being powered on accidentally due to the control signal being unexpectedly floating or uncertain. This enhances the stability and data security of the system under abnormal conditions, provides stronger default power-off protection for the server system, and simplifies the design and reduces costs by eliminating the need for complex monitoring circuits.

[0065] In some embodiments, the second control signal includes: a first level state and a second level state.

[0066] The backplane controller 1 is also configured to sequentially switch the second control signal output to different hard disk 4 connectors 3 from a second level state to a first level state at preset time intervals.

[0067] In other words, power can be supplied sequentially: the backplane controller 1 starts to execute the power-on sequence. First, it pulls the output terminal connected to the first hard disk 4 to a high level. The second control signal is transmitted to the first hard disk 4 through the reserved pin of the hard disk 4 connector 3. The logic control circuit inside the first hard disk 4 converts this high-level signal into a low-level enable signal and sends it to its backup power management module 41. The first hard disk 4 then starts to power on its internal power sequence.

[0068] After a 2ms delay, the backplane controller 1 pulls the second output high, and the second hard drive 4 starts to power on; and so on, until all hard drives 4 are powered on in sequence; this process effectively suppresses the surge current of multiple drives being powered on at the same time.

[0069] Reference Figure 3 and Figure 4Server backplanes typically connect to 12-bay, 24-bay, and 40-bay SSDs. Without power sequencing control, multiple SSDs powering on simultaneously can cause overcurrent issues, preventing the server's PSU power supply unit from outputting P12V power correctly at power-on. For example, the maximum current draw of a single PCIe SSD at power-on is approximately 1.2A. If 24 SSDs power on simultaneously, the maximum instantaneous current will be approximately 28.8A. A diagram of the instantaneous current draw is attached. Figure 4 As shown.

[0070] If multiple output terminals are powered on sequentially via backplane controller 1 using equal I / O levels, multiple SSDs in multiple drive bays can be powered on sequentially, with staggered power-on intervals for instantaneous startup current, as shown in the attached diagram. Figure 5 As shown, attached Figure 5 The display shows the instantaneous current flow when the first 12 SSDs are powered on. The instantaneous current flow when the 24-bay SSD is powered on is similar, so it will not be described in detail here.

[0071] Reference Figure 5 The timing diagram for the sequential power-on of the N hard drives on the server side is attached. Figure 5 As shown, firstly, after the backplane controller 1 is powered on and starts up normally, the backplane controller 1 configures the control terminal level to initially be low. Secondly, the backplane controller 1 configures the output level to be high, that is, the switching unit is turned on, and P12V_SSD normally outputs power to N SSDs, providing P12V_IN power. Since the power-on enable signal PLP signal on the SSD side is low, the SSDs cannot be powered on. Finally, the backplane controller 1 configures GPIO1 to output a low level. At this time, the corresponding PLP_EN signal on the SSD1 side is low, and the SSD1 is powered on. After a 2ms delay, GPIO2 outputs a low level, and the SSD2 is powered on. After another 2ms delay, GPIO3 outputs a low level, and the SSD3 is powered on. And so on, with GPION outputting a low level, the SSDn is powered on.

[0072] like Figure 6 As shown, the hard disk 4 includes: a backup power management module 41, a logic control module 42, and a main controller 43.

[0073] The input terminal of the backup power management module 41 is the power supply terminal of the hard disk 4, the output terminal of the backup power management module 41 is electrically connected to the power supply terminal of the main controller, and the control terminal of the backup power management module 41 is electrically connected to the control terminal of the logic control module 42.

[0074] The first input terminal of the logic control module 42 is the control terminal of the hard disk 4, the second input terminal of the logic control module 42 is electrically connected to the first control terminal of the main controller 43, and the output terminal of the logic control module 42 is electrically connected to the second control terminal of the main controller 43.

[0075] The logic control module 42 is configured to generate a first enable signal to the backup power management module 41 when the second control signal is at the first level, so as to power on the hard disk 4; and transmit the status indication of the second control signal to the main controller 43.

[0076] When the second control signal is at the second level, a second enable signal is generated to the backup power management module 41 to put the hard disk 4 into a power-off state or keep it in a power-off state.

[0077] The main controller 43 is configured to receive a status indication confirming power-off, and the control logic control module 42 generates a second enable signal to the backup power management module 41 so that the hard disk 4 is in a power-off state or remains in a power-off state.

[0078] The specific process is as follows:

[0079] When powered on, the second control signal is at the first level, and the first level is low.

[0080] Backplane controller 1 pulls the PWRDOWN signal low (first level). Logic control module 42's Q1 is cut off, causing PLP_EN to go high (first enable signal), enabling the Nortel management module and powering on all power supplies to hard disk 4. Simultaneously, PWRDOWN_IN goes high, serving as a status indicator to inform the main controller 43 that it has received an external power-on command. The main controller 43 initializes upon power-on, defaulting to outputting PWRDOWN_EN low, without affecting existing logic.

[0081] When the power is off, the second control signal is at the second level, and the second level is high.

[0082] Backplane controller 1 pulls the PWRDOWN signal high (second level). Logic control module 42 causes PWRDOWN_IN to go low, serving as a status indicator to inform the main controller 43 that an external power-down request has been received. After detecting that PWRDOWN_IN has gone low, the main controller 43 initiates a safe power-down process (such as flushing cached data to NAND); upon completion, the main controller 43 actively switches the PWRDOWN_EN output from low to high. After PWRDOWN_EN goes high, it pulls PLP_EN low (second enable signal), thereby shutting down the backup power management module 41 and completing the power-down of hard drive 4.

[0083] This application ensures extremely high operational safety by constructing a dual-path power control architecture controlled by a logic control module 42 within the hard disk 4. Power-down commands must be confirmed by the main controller 43 and complete the internal data protection process before final execution, fundamentally preventing data loss due to unexpected power outages. Secondly, this architecture provides strong reliability. The hardware logic of the logic control module 42 ensures that even if the main controller 43 experiences a software failure, external emergency power-down commands can still be forcibly executed through the hardware path. Simultaneously, the main controller 43 can also proactively initiate a safe power-down when an internal fault is detected. Furthermore, the main controller 43 can intervene in software filtering and delay management, and can intelligently respond to various power-down trigger conditions from the backplane or internal components. Finally, this design maintains low cost and compatibility advantages, utilizing the existing pins of the hard disk 4 connector 3 without adding expensive components to the backplane, thus achieving intelligent and safe collaborative power management that traditional solutions cannot provide, significantly improving the overall reliability of the storage system.

[0084] In some embodiments, the hard disk 4 further includes a buck-boost module.

[0085] The step-up / step-down module is located between the backup power management module 41 and the main controller 43, and is used to provide the main controller 43 with a suitable operating voltage.

[0086] For example, the P12V_OUT power supply is converted into NAND VCC, DRAM VDD, Vcore, and P3V3 power supplies for the internal hard disk 4 via a buck-boost module, respectively, to power the NAND Flash, DRAM, main controller 43, and other power circuits within the hard disk 4.

[0087] like Figure 4 As shown, the logic control module 42 includes: a voltage divider circuit 44, a first switching circuit 45, and a second switching circuit 46.

[0088] The first end of the voltage divider circuit 44 is the power supply end of the hard disk 4, the second end of the voltage divider circuit 44 is grounded, and the third end of the voltage divider circuit 44 is electrically connected to the first end of the first switch circuit 45, and is also the control end of the logic control module 42.

[0089] The second terminal of the first switching circuit 45 is the first input terminal of the logic control module 42, and the third terminal of the first switching circuit 45 is the second input terminal of the logic control module 42.

[0090] The first terminal of the second switch circuit 46 is electrically connected to the second terminal of the first switch circuit 45. The second terminal of the second switch circuit 46 is electrically connected to the fourth power supply terminal. The third terminal of the second switch circuit 46 is grounded. The fourth terminal of the second switch circuit 46 is the output terminal of the logic control module 42.

[0091] The logic control module 42 consists of a voltage divider circuit 44, a first switching circuit 45, and a second switching circuit 46. The voltage divider circuit 44 is connected between the main power input terminal of the hard disk 4 and ground. Its voltage divider point (third terminal) also serves as the external control terminal of the logic control module 42, providing bias voltage to the first switching circuit 45.

[0092] The two input terminals of the first switching circuit 45 receive the raw power control signal from the server backplane and the local enable signal from the main controller, respectively, and their states are determined by these two signals.

[0093] The second switching circuit 46 controls the current path flowing up to the power supply or down to ground according to the output state of the first switching circuit 45, thereby generating a final high-level or low-level enable signal at the output terminal to drive the backup power management module 41.

[0094] The voltage divider circuit 44 includes a second resistor R2 and a third resistor R1.

[0095] The first end of the second resistor R2 is the first end of the voltage divider circuit 44, and the second end of the second resistor R2 is electrically connected to the third resistor R1, which is also the third end of the voltage divider circuit 44.

[0096] The second terminal of the third resistor R1 is the second terminal of the voltage divider circuit 44.

[0097] When the P12V_IN power supply voltage is divided to a value greater than 1.5V by the second resistor R2 and the third resistor R1, the control terminal of the backup power management module 41 is enabled.

[0098] The first switching circuit 45 includes: a first switching transistor Q1, a first diode, a fourth resistor R1, and a fifth resistor R1.

[0099] The control terminal of the first switch Q1 is electrically connected to the second terminal of the fifth resistor R1 and also electrically connected to the positive terminal of the first diode. The first terminal of the first switch Q1 is electrically connected to the second terminal of the fourth resistor R1, and the second terminal of the first switch Q1 is grounded.

[0100] The first end of the fourth resistor R1 is the first end of the first switching circuit 45, the first end of the fifth resistor R1 is the second end of the first switching circuit 45, and the cathode of the first diode is the third end of the first switching circuit 45.

[0101] The fifth resistor R1 serves to limit the current and prevent excessive current from damaging the first switching circuit 45.

[0102] The first switch Q1 and the fourth resistor R1 form an inverter, which inverts the SSD power control signal PWRDOWN from the server or the power enable signal PWRDOWN_EN from the main controller 43 into the power enable signal PLP_EN of the backup power management chip. When the power enable signal exceeds the enable level of the backup power management module 41, the voltage at the P12V_OUT terminal is basically equal to the P12V_IN voltage.

[0103] The second switching circuit 46 includes: a second switching transistor Q2 and a sixth resistor R1.

[0104] The control terminal of the second switch transistor Q2 is the first terminal of the second switch circuit 46. The first terminal of the second switch transistor Q2 is the fourth terminal of the second switch circuit 46 and is also electrically connected to the second terminal of the sixth resistor R1. The second terminal of the second switch transistor Q2 is grounded.

[0105] The first terminal of the sixth resistor R1 is the second terminal of the second switching circuit 46.

[0106] The second switch Q2 and the sixth resistor R1 also form an inverter, which inverts the power enable signal PWRDOWN from the server backplane and converts it into a power control detection signal PWRDOWN_IN. The main controller 43 detects and confirms whether the power enable signal from the server is valid.

[0107] Meanwhile, the PWRDOWN_EN signal output by the main controller 43 serves as an enable signal for power-down control during the operation of the hard disk 4. After the hard disk 4 is powered on, this pin outputs a low level by default. When the hard disk 4 main controller 43 confirms that it has received a power-down request from the server, it outputs a high level through internal logic judgment and software filtering to realize the power-down logic control within the hard disk 4.

[0108] For example, when the power control signal PWRDOWN is high (the hard drive is not powered on), in channel Q1, although there is a voltage divider voltage in P12V_IN, the PLP_EN of the backup power management module remains low due to the inverting logic. There is no voltage inside the hard drive, and the hard drive is in a power-off state.

[0109] When the power control signal PWRDOWN from the server outputs a low level (hard drive power-on signal), PWRDOWN_1 / PWRDOWN_2 are at a low level, the first switching transistor Q1 is turned off, the PLP_EN power-on enable signal becomes high, and the backup power management module and the buck-boost module work normally to output the voltage of each branch. At this time, the main controller and core devices inside the hard drive are powered on.

[0110] Similarly, with P3V3 power supply active, the second switch Q2 is off, and the main controller PWRDOWN_IN confirms receipt of a high level, thus identifying it as a hard drive power-on signal. Then, the main controller PWRDOWN_EN outputs a low-level signal, which, after being clamped by the first diode D1 (the first diode D1 is selected as a diode with a small forward voltage drop, such as 0.1V@10mA), is not conducting, determining that PWRDOWN_2 is at approximately 0V. Since this voltage level is less than the turn-on voltage of the first switch Q1, the first switch Q1 is off. The entire hard drive power-on enable control process is now complete.

[0111] When the hard drive is in normal operating condition under power supply voltage, when the power control signal PWRDOWN from the server is high (hard drive power-off signal), the P3V3 power supply is normal, the second switching transistor Q2 is turned on, and the host controller PWRDOWN_IN receives a low level. After software filtering and a 500ms delay, PWRDOWN_IN checks again and finds a low level, confirming that it is a real power-off signal sent to the hard drive by the server host. The hard drive firmware then begins the backup power process, refreshing the DRAM data to the NAND.

[0112] The main controller changes the output signal PWRDOWN_EN from a low level signal in the default power-on state to a high level signal. Due to the unidirectional clamping effect of the first diode D1, PWRDOWN_2 changes from a low level in the original power-on state to a high level. At this time, the first switch Q1 is turned on, the enable signal PLP_EN of the backup power management module is pulled down to GND, the power-on enable signal is invalid, and P12V_VIN in the hard drive starts to power down; the entire hard drive power-down enable control process is completed.

[0113] In some embodiments, the first switching transistor is a NOMS transistor, and the second switching transistor is also a NOMS transistor.

[0114] In some embodiments, the hard disk 4 further includes: a transient voltage suppression diode (TVS), a first capacitor C1, a second capacitor C2, a third capacitor C3, and a seventh resistor R7.

[0115] The positive terminal of the transient voltage suppressor diode (TVS) is grounded, and the negative terminal of the TVS is the power supply terminal of hard disk 4.

[0116] The first terminal of the first capacitor C1 is the power supply terminal of the hard disk 4, and the second terminal of the first capacitor C1 is grounded.

[0117] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the backup power management module 41, and the second terminal of the second capacitor C2 is grounded.

[0118] The first terminal of the third capacitor C3 is electrically connected to the second terminal of the seventh resistor R7, and the second terminal of the third capacitor C3 is grounded; the first terminal of the seventh resistor R7 is the control terminal of the hard disk 4.

[0119] The transient voltage suppression diode provides overvoltage protection, while the first capacitor C1 and the second capacitor C2 provide filtering. The third capacitor C3 and the seventh resistor R7 provide RC low-pass filtering.

[0120] This application also provides a server, including: a control component 100 and a motherboard, the motherboard being connected to the control component 100; the motherboard being configured to supply power to the control component 100.

[0121] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the power-on or power-off control process of any of the above-described hard disks.

[0122] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the power-on or power-off control process of any of the above-described hard disks when running.

[0123] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0124] An embodiment of this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the power-on or power-off control process of any of the aforementioned hard disks.

[0125] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the power-on or power-off control process of any of the aforementioned hard disks.

[0126] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0127] The control component, server, electronic device, storage medium, and computer program product provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A control component, characterized in that, The control assembly comprises: a backboard controller, a switch unit, a plurality of hard disk connectors and a plurality of hard disks; a power supply end of the backboard controller is electrically connected with a first power supply end, a control end of the backboard controller is connected with an enable end of the switch unit, and an output end of the backboard controller is connected with an input end of one of the hard disk connectors; an input end of the switch unit is electrically connected with a second power supply end, and an output end of the switch unit is used for connecting a power supply end of a hard disk; and at least two output ends of the hard disk connector are used for connecting a power supply end and a control end of a hard disk respectively; the backboard controller is configured to output a first control signal through the control end to control the switch unit to be turned on; a second control signal is outputted through the output end to the hard disk connector to control power-on and power-off of the hard disk; the second control signal comprises a first level state and a second level state; the backboard controller is further configured to switch the second control signal outputted to different hard disk connectors from the second level state to the first level state at a preset time interval; the hard disk is configured to perform power-on operation when the second control signal is in the first level state, and perform power-off operation or keep in a power-off state when the second control signal is in the second level state.

2. The control assembly according to claim 1, wherein: the backboard controller is configured to drive the output end to a first level state to output an instruction for controlling power-on of a hard disk.

3. The control assembly of claim 1, wherein, The control assembly further comprises a plurality of first resistors; a first end of each of the first resistors is electrically connected with a third power supply end, and a second end of each of the first resistors is electrically connected with an output end of the backboard controller; the first resistor is configured to maintain the second control signal in the second level state when the backboard controller is not driven; the second control signal maintained in the second level state controls the hard disk to keep in a power-off state or enter a power-off state.

4. The control assembly of claim 1, wherein, The hard disk comprises a backup power management module, a logic control module and a main controller; an input end of the backup power management module is a power supply end of the hard disk, an output end of the backup power management module is electrically connected with a power supply end of the main controller, and a control end of the backup power management module is electrically connected with a control end of the logic control module; a first input end of the logic control module is a control end of the hard disk, a second input end of the logic control module is electrically connected with a first control end of the main controller, and an output end of the logic control module is electrically connected with a second control end of the main controller; the logic control module is configured to generate a first enable signal to the backup power management module to make the hard disk power on when the second control signal is in the first level state, and transmit a state indication of the second control signal to the main controller; the logic control module is configured to generate a second enable signal to the backup power management module to make the hard disk in a power-off state or keep in a power-off state when the second control signal is in the second level state. The master controller is configured to receive the power-off state indication, control the logic control module to generate the second enable signal to the backup power management module, so that the hard disk is in the power-off state or remains in the power-off state.

5. The control assembly of claim 4, wherein, The logic control module comprises a voltage dividing circuit, a first switch circuit and a second switch circuit. The first end of the voltage dividing circuit is the power supply end of the hard disk, the second end of the voltage dividing circuit is grounded, and the third end of the voltage dividing circuit is electrically connected with the first end of the first switch circuit and also serves as the control end of the logic control module. The second end of the first switch circuit is the first input end of the logic control module, and the third end of the first switch circuit is the second input end of the logic control module. The first end of the second switch circuit is electrically connected with the second end of the first switch circuit, the second end of the second switch circuit is electrically connected with the fourth power supply end, the third end of the second switch circuit is grounded, and the fourth end of the second switch circuit is the output end of the logic control module.

6. The control assembly of claim 5, wherein, The voltage dividing circuit comprises a second resistor and a third resistor. The first end of the second resistor is the first end of the voltage dividing circuit, the second end of the second resistor is electrically connected with the third resistor, and the third end of the second resistor also serves as the third end of the voltage dividing circuit. The second end of the third resistor is the second end of the voltage dividing circuit.

7. The control assembly of claim 5, wherein, The first switch circuit comprises a first switch tube, a first diode, a fourth resistor and a fifth resistor. The control end of the first switch tube is electrically connected with the second end of the fifth resistor and also electrically connected with the anode of the first diode, the first end of the first switch tube is electrically connected with the second end of the fourth resistor, and the second end of the first switch tube is grounded. The first end of the fourth resistor is the first end of the first switch circuit, the first end of the fifth resistor is the second end of the first switch circuit, and the cathode of the first diode is the third end of the first switch circuit.

8. The control assembly of claim 5, wherein, The second switch circuit comprises a second switch tube and a sixth resistor. The control end of the second switch tube is the first end of the second switch circuit, the first end of the second switch tube is the fourth end of the second switch circuit and also electrically connected with the second end of the sixth resistor, and the second end of the second switch tube is grounded. The first end of the sixth resistor is the second end of the second switch circuit.

9. A server, characterized by The control assembly comprises: The control assembly according to any one of claims 1 to 8, a mainboard connected with the control assembly; The mainboard is configured to supply power to the control assembly.

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