A heterogeneous data acquisition and processing system based on GPU and FPGA

Abstract

This invention relates to a heterogeneous data acquisition and processing system based on GPU and FPGA. The system includes a GPU board, an FPGA board, and external devices. The FPGA board includes a ZYNQ processing platform and DDR dynamic memory. The GPU board is connected to the ZYNQ processing platform via a PCIe interface, and the ZYNQ processing platform is connected to the DDR dynamic memory via a memory interface. The GPU board uses a DMA driver to directly access data in the DDR dynamic memory through the PCIe interface. The ZYNQ processing platform is connected to the external devices. The ZYNQ processing platform includes an XDMAIP core. The GPU board includes an application (APP), a DMA driver, and memory units. The APP controls the DMA driver to directly access data in the DDR dynamic memory through the PCIe interface and copies the data from the DDR dynamic memory to the memory units of the GPU board. The XDMAIP core controls the memory units to write data to the FPGA board and read data from the FPGA board. Therefore, this invention is not only small in size and low in power consumption, but also achieves a balance between low power consumption and processing speed, and can be flexibly applied in various scenarios.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and relates to a heterogeneous data acquisition and processing system based on GPU and FPGA. Background Technology

[0002] With the increasing demands of various electronic products on the market, the required speed of data acquisition and processing by systems is also getting faster and faster. Currently, the mainstream acquisition and processing system solutions (ZL202010769501.1, a high-speed acquisition, storage, and analysis system based on FPGA and GPU) are implemented using a PC with a dedicated acquisition card or an embedded system. The former type of system is generally large in size, consumes a lot of power, and is expensive. It is also easily affected by the working environment, and such systems are generally developed for specific purposes, so their flexibility is relatively poor. The latter type of system, in order to reduce power consumption and size, is generally developed using a low-power SoC. The communication interface used is generally a low-speed serial data interface such as UART or IIC. However, excessively large data volumes or excessively high speeds may cause data loss, thus failing to meet the intended requirements.

[0003] Therefore, current data acquisition and processing systems cannot simultaneously achieve a balance between low power consumption and processing speed, and cannot be flexibly applied to various scenarios. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a small-sized, low-power heterogeneous data acquisition and processing system based on GPU and FPGA, thereby simultaneously achieving a balance between low power consumption and processing speed, and being flexibly applicable to various scenarios.

[0005] To achieve the above objectives, this invention provides a heterogeneous data acquisition and processing system based on GPU and FPGA. The system includes a GPU board, an FPGA board, and external devices. The FPGA board includes a ZYNQ processing platform for data acquisition and control of external devices, and a DDR dynamic memory for data storage. The GPU board is connected to the ZYNQ processing platform via a PCIe interface, and the ZYNQ processing platform is connected to the DDR dynamic memory via a memory interface. The GPU board uses a DMA driver to directly access data in the DDR dynamic memory through the PCIe interface. The ZYNQ processing platform is connected to the external devices. The ZYNQ processing platform includes an XDMAIP core for converting between AXI protocol data and data transmitted via the PCIe interface. The GPU board includes an application (APP), a DMA driver, and memory units. The APP controls the DMA driver to directly access data in the DDR dynamic memory through the PCIe interface and copies the data from the DDR dynamic memory to the memory units of the GPU board. The XDMAIP core controls the memory units to write data to the FPGA board. The IP core controls the memory unit to read data from the FPGA board.

[0006] Preferably, the ZYNQ processing platform further includes a FIFO IP core for clock domain conversion of the data output by the XDMA IP core, an AXI CROSSBAR IP core for interconnection with data collected by external devices, and a MIG IP core for controlling the DDR dynamic memory to write and convert AXI format data.

[0007] More preferably, the FIFO IP core is connected to the XDMA IP core via an AXI interface; the AXICROSSBAR IP core is connected to the FIFO IP core and the external device respectively via an AXI interface; and the MIG IP core is connected to the AXI CROSSBAR IP core via an AXI interface.

[0008] More preferably, the data collected by the external device is converted into AXI protocol data by the control logic unit, and then interconnected through the AXI CROSSBAR IP core.

[0009] Preferably, the external device includes a camera, an analog-to-digital converter, a monitor, and a PC.

[0010] More preferably, the GPU board is an NVIDIA embedded GPU.

[0011] Preferably, the FPGA board is a ZYNQ series FPGA that includes an ARM processor.

[0012] The beneficial effects of the present invention are as follows: the technical solution of the present invention uses the PCIe interface to realize efficient data transmission between two boards, and the GPU board uses DMA driver to directly access the data in the DDR dynamic memory through the PCIe interface, so that the FPGA can collect data, the GPU can process data and implement algorithms, and the CPU can perform scheduling, so that all aspects can work together. Attached Figure Description

[0013] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:

[0014] Figure 1 This is a schematic diagram of the structure of a heterogeneous data acquisition and processing system based on GPU and FPGA as described in this invention. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] Definitions:

[0017] XDMA: Xilinx Direct Memory Access;

[0018] FIFO: First In First Out;

[0019] AXI Crossbar: Advanced eXtensible Interface Crossbar;

[0020] MIG: Memory Interface Generators;

[0021] DDR3 SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory Gen3, the third generation of double data rate synchronous dynamic random access memory;

[0022] AXI: Advanced eXtensible Interface, is a bus protocol.

[0023] like Figure 1 As shown, this invention provides a heterogeneous data acquisition and processing system based on GPU and FPGA. The system includes a GPU board 10, an FPGA board 20, and external devices 30. The FPGA board 20 includes a ZYNQ processing platform 21 for data acquisition and control of external devices, and a DDR dynamic memory 22 for data storage. The GPU board 10 is connected to the ZYNQ processing platform 21 via a PCIe interface, and the ZYNQ processing platform 21 is connected to the DDR dynamic memory 22 via a memory interface. The GPU board 10 uses a DMA driver 12 to directly access the data in the DDR dynamic memory 22 through the PCIe interface. The ZYNQ processing platform 21 is connected to the external devices 30. Compared to a PC + acquisition card, the system architecture of this invention is not only smaller in size but also consumes less CPU power.

[0024] The ZYNQ processing platform 21 mainly includes an XDMA IP core 211 for converting between AXI protocol data and data transmitted via the PCIe interface; a FIFO IP core 212 for clock domain conversion of the data output by the XDMA IP core; an AXI CROSSBAR IP core 214 for interconnecting with data collected by external devices; and a MIG IP core 215 for controlling the DDR dynamic memory to write and convert AXI format data. The FIFO IP core 212 is connected to the XDMA IP core 211 via an AXI interface. The AXI CROSSBAR IP core 214 is connected to both the FIFO IP core 212 and the external device 30 via AXI interfaces. The MIG IP core 215 is connected to the AXI CROSSBAR IP core 214 via an AXI interface. In this embodiment of the invention, the GPU board 10 is an NVIDIA embedded GPU, and the FPGA board 20 is a ZYNQ series FPGA containing an ARM processor.

[0025] The GPU board 10 mainly includes an application APP 11, a DMA driver 12, and a memory unit 13. The application APP 11 is used to control the DMA driver 12 to directly access the data of the DDR dynamic memory 22 through the PCIe interface and copy the data from the DDR dynamic memory 22 to the memory unit 13 in the GPU board 10. The DMA driver 12 directly accesses the DDR dynamic memory 22 through the PCIe interface. The XDMA IP core 211 controls the memory unit 13 to write data to the FPGA board 20 and controls the memory unit 13 to read data from the FPGA board 20.

[0026] The data collected by the external device is converted into AXI protocol data by the user acquisition and upload control logic unit 213, and then processed by the AXI CROSSBAR IP core 214. The external device 30 includes a camera, an analog-to-digital converter, a monitor, and a PC computer.

[0027] It should be noted that the system described in this embodiment of the invention uses a ZYNQ series FPGA containing an ARM processor and an NVIDIA embedded GPU. The data between the PS and PL ends of the ZYNQ processing platform 21 interacts through an AXI interface, and the ZYNQ processing platform 21 and the GPU board 10 interact through a PCIE interface. On the PL end of the ZYNQ processing platform 21, a FIFO IP core 212, a MIG IP core 215, and a control logic unit 213 are used to store the user-collected data into the DDR dynamic memory 22. The PL end also uses an XDMA IP core 211. The GPU directly accesses the DDR dynamic memory 22 using a PCIE interface and DMA technology, reads data, processes it, and writes the processed data into the DDR dynamic memory 22 through the DMA driver 12.

[0028] The heterogeneous data acquisition and processing system based on GPU and FPGA described in this invention uses ZYNQ to acquire data and control peripherals, while the GPU performs data processing. It can fully leverage the scheduling advantages of the CPU, the data processing advantages of the GPU, and the flexible configuration advantages of the FPGA. It can be applied to different application scenarios and meet different needs, providing users with a small-sized and low-power data acquisition and processing system for high-speed data acquisition and processing.

[0029] To better understand the embodiments of the present invention, the embodiments of the present invention are now described in detail below:

[0030] The ZYNQ processing platform 21 consists of an XDMA IP core 211, a FIFO IP core 212, a control logic unit 213, an AXI Crossbar IP core 214, and a MIG IP core 215. The IP cores interact with each other through the AXI interface to complete the data acquisition, storage, and transmission processing. The GPU board 10 uses the DMA driver 12 to directly access the data in the DDR dynamic memory 22 (e.g., DDR3 SDRAM memory) through the PCIE interface. The ZYNQ processing platform 21 and the GPU board 10 are connected through the PCIE interface. The ZYNQ processing platform 21 can send data to or receive data from the memory unit 13 of the GPU board 10 through the PCIE interface. The GPU can also send data to or receive data from the memory unit 13 of the GPU board 10, ensuring the implementation of the data acquisition and processing system.

[0031] Because the AXI4 protocol is currently a common bus protocol, and the IP cores used in the design are all AXI interfaces, the AXI4 protocol is specifically adopted in this embodiment of the invention. XDMA IP core 211 is the control IP of the PCIE interface of the ZYNQ processing platform 21. This IP can convert AXI4 protocol data to data that can be transmitted through the PCIE interface. FIFO IP core 212 is used to convert the clock domain of the data output by XDMA IP core 211. Control logic unit 213 converts the user-collected data into data that conforms to the AXI4 protocol. AXI CROSSBAR IP core 214 is used to realize N-1, 1-N, or NN interconnection between AXI bus devices. MIG IP core is used to control DDR dynamic memory and to convert AXI format data into data that can be received by DDR dynamic memory. DDR dynamic memory is used to store data.

[0032] The specific process is as follows: Data collected by the user through external device 30 (such as pixel data converted from images captured by a camera, or voltage data collected by an analog-to-digital voltage converter chip) is converted into data that conforms to the AXI4 protocol by control logic unit 213. After passing through AXI CROSSBAR IP core 214, it is written into DDR through MIG IP core (because the DDR3 memory interface control logic is generated through MIG IP core). Then, GPU board 10 reads data from DDR dynamic memory 22 through DMA driver 12 (such as pre-set algorithms or formula programs written by the user), processes it accordingly, and rewrites it into DDR dynamic memory 22. After that, the user can generate an AXI interface read request on ZYNQ processing platform 21 through control logic unit 213 to read the data written into DDR dynamic memory 22 by GPU board 10. After the control logic unit 213 converts the AXI4 protocol data, it is sent to other external devices (such as monitors, PCs, etc.) to complete data acquisition and processing.

[0033] In summary, the system described in this embodiment of the invention utilizes a PCIe interface to achieve efficient data transmission between two boards. The GPU board employs a DMA driver to directly access data in the DDR dynamic memory via the PCIe interface, enabling the FPGA to acquire data, the GPU to process data and implement algorithms, and the CPU to perform scheduling, all working in tandem. This system is smaller in size and consumes less power than a PC + acquisition card, while also ensuring sufficient data acquisition and processing speed. Furthermore, users can leverage the FPGA in this system to accelerate the implementation of key algorithms, thereby ensuring that specific functionalities are achieved within user requirements.

[0034] The above provides a detailed description of the heterogeneous data acquisition and processing system based on GPU and FPGA provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the platform disclosed in the embodiments, since it corresponds to the system disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the system section description. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0035] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made to it in form and detail without departing from the scope defined by the claims of the present invention.

Claims

1. A heterogeneous data acquisition and processing system based on GPU and FPGA, characterized in that, This heterogeneous data acquisition and processing system includes a GPU board, an FPGA board, and external devices. The FPGA board includes a ZYNQ processing platform for acquiring data and controlling external devices, and DDR dynamic memory for storing data. The GPU board is connected to the ZYNQ processing platform via a PCIe interface, and the ZYNQ processing platform is connected to the DDR dynamic memory via a memory interface. The GPU board uses a DMA driver to directly access data in the DDR dynamic memory through the PCIe interface and the XDMA IP core of the ZYNQ processing platform. The ZYNQ processing platform is connected to the external devices. The ZYNQ processing platform includes an XDMA IP core for converting between AXI protocol data and data transmitted through the PCIe interface. The GPU board includes an application (APP), a DMA driver, and memory units. The APP controls the DMA driver to directly access data in the DDR dynamic memory through the PCIe interface and copies the data from the DDR dynamic memory to the memory units of the GPU board. The XDMA IP core is used to convert between AXI protocol data and data transmitted through the PCIe interface to support the GPU board's access to the DDR dynamic memory through the DMA driver.

2. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 1, characterized in that, The ZYNQ processing platform also includes a FIFO IP core for clock domain conversion of the data output by the XDMA IP core, an AXI CROSSBAR IP core for interconnection with data collected by external devices, and a MIG IP core for controlling the DDR dynamic memory to write and convert AXI format data.

3. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 2, characterized in that, The FIFO IP core is connected to the XDMA IP core via an AXI interface; the AXI CROSSBAR IP core is connected to both the FIFO IP core and the external device via an AXI interface; the MIG IP core is connected to the AXI CROSSBAR IP core via an AXI interface.

4. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 2 or 3, characterized in that, The data collected by the external device is converted into AXI protocol data by the control logic unit, and then interconnected through the AXICROSSBAR IP core.

5. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 1, characterized in that, The external devices include a camera, an analog-to-digital converter, a monitor, and a PC.

6. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 1, characterized in that, The GPU board is an NVIDIA embedded GPU.

7. The heterogeneous data acquisition and processing system based on GPU and FPGA according to claim 1, characterized in that, The FPGA board is a ZYNQ series FPGA containing an ARM processor.

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