Storage device and methods of manufacture, testing and data protection thereof

Abstract

The present disclosure provides a storage device and a manufacturing, testing and data protection method thereof. According to a method of manufacturing a storage device according to the present disclosure, the storage device comprises a package part in which a controller and a memory are packaged, and a test pin exposed from the package part, the method comprising: connecting a test pad corresponding to a functional circuit lead-out end in the controller and / or the memory to the test pin; and configuring the controller so that the controller can trigger a test of the functional circuit in response to an excitation signal applied to the test pin and received via the test pad.

Description

[0001] Divisional application statement

[0002] This application is a divisional application of Chinese invention patent application filed on April 15, 2021, entitled "Storage Device and Method for Manufacturing, Testing and Data Protection Thereof", with application number 202110404823.0. Technical Field

[0003] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the field of memory device design and manufacturing. Background Technology

[0004] The external pins of existing MNAND memories are defined by standard protocols. Only the pads corresponding to certain critical functions or commands are brought out from the external pins, such as input / output (I / O), instruction CMD, and clock CLK. The other pins of the chip are either unconnected (NC) or other spare pins such as VC (VendorConnect). Because many auxiliary circuits inside the chip are not connected to external pins, testing these circuits is difficult. For example, during package testing, only circuits connected to external pins can be tested for open circuits or short circuits; auxiliary circuits not connected to external pins are difficult to test. Summary of the Invention

[0005] This application provides methods and apparatus that can at least partially solve the aforementioned problems existing in the prior art.

[0006] According to one aspect, this application provides a method of manufacturing a storage device, the storage device including a package containing a controller and a memory, and test pins exposed from the package, the method comprising: connecting test pads corresponding to functional circuit leads in the controller and / or the memory to the test pins; and configuring the controller such that the controller is capable of triggering a test of the functional circuits in response to an excitation signal applied to the test pins and received via the test pads.

[0007] In one implementation, the test pin is an empty pin or a spare pin that is not predefined with a specific connection based on a standard protocol.

[0008] In one embodiment, the functional circuit includes a circuit under test, and the test pad corresponds to a lead of the circuit under test.

[0009] In one embodiment, the functional circuit includes a plurality of circuits under test, the leads of which share the test pad.

[0010] In one embodiment, the method further includes configuring the controller such that the controller stores the results of testing the functional circuit into the memory.

[0011] In one embodiment, the excitation signal includes a signal for testing the functional circuit.

[0012] According to another aspect, this application provides a storage device, including: a package containing a controller and a memory; and test pins exposed from the package, the test pins being connected to test pads corresponding to functional circuit leads in the controller and / or the memory, wherein the controller is configured to trigger a test of the functional circuits in response to an excitation signal applied to the test pins and received via the test pads.

[0013] In one implementation, the test pin is an empty pin or a spare pin that is not predefined with a specific connection based on a standard protocol.

[0014] In one embodiment, the functional circuit includes a circuit under test, and the test pad corresponds to a lead of the circuit under test.

[0015] In one embodiment, the functional circuit includes a plurality of circuits under test, the leads of which share the test pad.

[0016] In one embodiment, the method further includes: the controller is further configured to store the results of testing the functional circuitry into the memory.

[0017] According to another aspect, this application provides a method for testing a storage device, comprising: applying an excitation signal to the test pin; the controller receiving the excitation signal via the test pad; and the controller triggering a test of the functional circuitry based on the excitation signal.

[0018] In one embodiment, the excitation signal includes a signal for testing the functional circuit.

[0019] According to another aspect, this application provides a method of manufacturing a storage device, the storage device including a package containing a controller and a memory, and a security pin exposed from the package, the method comprising: connecting at least one virtual pad in the controller and / or the memory to the security pin; and configuring the controller such that the controller is capable of: enabling the memory to be in an operable state in response to an excitation signal applied to the security pin and received via the virtual pad, otherwise enabling the memory to be in an inoperable state.

[0020] In one embodiment, the method further includes: providing a switch pad in the memory, the switch pad changing the operating state of the memory in response to an instruction from the controller.

[0021] In one embodiment, the method further includes: connecting the virtual pad to the switch pad; and sending the instruction to the switch pad through the connection.

[0022] In one implementation, the security pin is an empty pin or a spare pin that is not predefined with a specific connection based on a standard protocol.

[0023] In one embodiment, the method further includes: predefining a safety signal in the controller; and configuring the controller such that the controller compares the excitation signal with the safety signal, and if they are the same, puts the memory in an operable state, and if they are different, puts the memory in an inoperable state.

[0024] According to another aspect, this application provides a storage device comprising: a package containing a controller and a memory; and a security pin exposed from the package, the security pin being connected to at least one virtual pad in the controller and / or the memory, wherein the controller is configured to, in response to an excitation signal applied to the security pin and received via the virtual pad, enable the memory to be in an operable state, otherwise enable the memory to be in an inoperable state.

[0025] In one embodiment, the memory includes a switch pad; and the controller is further configured to send instructions to the switch pad to control the switch pad to change the operating state of the memory.

[0026] In one implementation, the virtual pad is connected to the switch pad so that the instruction can be sent to the switch pad via the connection.

[0027] In one implementation, the security pin is an empty pin or a spare pin that is not predefined with a specific connection based on a standard protocol.

[0028] In one embodiment, the controller pre-stores a safety signal; and the controller is further configured to compare the excitation signal with the safety signal, and if they are the same, to make the memory operable, and if they are different, to make the memory inoperable.

[0029] According to another aspect, this application provides a method for data protection of a storage device, comprising: applying an excitation signal to the security pin; the controller receiving the excitation signal via the virtual pad; and the controller comparing the excitation signal with the security signal, wherein if they are the same, the memory is put into an operable state, and if they are different, the memory is put into an inoperable state. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0031] Figure 1 This is a flowchart of a method for manufacturing a storage device according to an embodiment of this application;

[0032] Figure 2 This is a partial internal connection diagram of a storage device manufactured according to an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of the excitation signal applied to the test pins of the storage device when testing the storage device according to an embodiment of this application;

[0034] Figure 4 This is a flowchart of a method for testing a storage device according to an embodiment of this application;

[0035] Figure 5 This is a flowchart of a method for manufacturing a storage device according to another embodiment of this application;

[0036] Figure 6 This is a partial internal connection diagram of a storage device manufactured according to another embodiment of this application;

[0037] Figure 7 This is a schematic diagram of a security signal defined by a storage device manufactured according to another embodiment of this application; and

[0038] Figure 8 This is a flowchart of a data protection method for a storage device according to an embodiment of this application. Detailed Implementation

[0039] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first side discussed herein may also be referred to as the second side, and the first window may also be referred to as the second window, and vice versa.

[0041] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0042] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0043] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0044] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0047] Figure 1 This is a flowchart of a method for manufacturing a storage device according to an embodiment of this application. See also... Figure 1 The method 2000-1 may include the following steps:

[0048] S1, connect the test pads corresponding to the functional circuit leads in the controller and / or memory to the test pins; and

[0049] S2, Configure the controller so that it can trigger the test of the functional circuit in response to the excitation signal applied to the test pin and received via the test pad.

[0050] Figure 2 This is a partial internal connection diagram of a storage device manufactured according to an embodiment of this application. For example... Figure 2 As shown, the storage device 1000 may include a package 100 and test pins 200 exposed from the package 100. The package 100 may include a controller 110 and a memory 120. Figure 2 Only one test pin 200 is shown, but those skilled in the art will understand that there may be multiple test pins 200.

[0051] Furthermore, the controller 110 may include test pads 111a, which may be leads of functional circuits in the controller 110; the memory 120 may include test pads 121a, which may be leads of functional circuits in the memory 120. Multiple test pads 111a and 121a may also be present.

[0052] In addition, the controller 110 and the memory 120 may also include some specific function pads, such as Figure 2 Both 110-1 and 120-1 shown can be function-specific pads. These function-specific pads can also be leads for specific functional circuits in the controller 110 and memory 120. However, unlike the test pads, these function-specific pads can be specific pins with defined functions that are already connected from the inside of the package 100 to the exposed pins of the package 100 according to existing memory design standard protocols (e.g., ...). Figure 2 The pad for pin 300 in the middle. Figure 2 The connection between pad 120-1 and pad 110-1, and the connection between pad 110-1 and pin 300, are schematic diagrams of the connection of any specific pin in the prior art.

[0053] like Figure 2 As shown, the test pad 111a in the controller 110 can be connected to the test pad 121a in the memory 120, and the test pad 121a in the memory 120 can be connected to the test pin 200 of the storage device 1000.

[0054] The controller 110 is configured to trigger detection of the functional circuitry corresponding to the test pad 111a in response to an excitation signal applied to the test pin 200. Specifically, the excitation signal applied to the test pin 200 is transmitted to the test pad 111a of the controller 110 via, for example, a connection between the test pin 200 and the test pad 121a and the test pad 111a. The controller 110 is configured to sense and identify the excitation signal received at the test pad 111a, and trigger detection of the functional circuitry corresponding to the test pad 111a in the controller 110 based on the excitation signal.

[0055] It will be understood by those skilled in the art that Figure 2 The connections between the test pads and test pins shown are merely exemplary, and the invention is not limited thereto. According to another embodiment, the test pad 111a in the controller 110 may not be connected to the test pad 121a in the memory 120, but may be directly connected to the test pin 200. According to yet another embodiment, the test pad 111a in the controller 110 and the test pad 121a in the memory 120 may be connected to different test pins 200, respectively. The controller 110 is capable of triggering detection of the corresponding functional circuits connected to the test pads based on the excitation signal.

[0056] In one embodiment of this application, the test pin 200 may be an undefined empty pin or a spare pin exposed from the package portion 100 with no specific connection. Specifically, the memory device includes a plurality of pins exposed from the package portion 100, wherein, according to the provisions of the memory standard protocol, some pins are specific pins with defined specific connections, that is, these specific pins are connected to some specific functional circuits inside the memory device as specified by the protocol. For example, pins with defined specific connections may include input / output pins (IO), instruction pins (CMD), and clock pins (CLK), etc. Figure 2 Pin 300 in the package can be a specific pin such as IO, CMD, or CLK. Another portion of the pins exposed from the package 100 are empty pins (NC pins) or spare pins (VC pins), meaning that these pins are not connected to any functional circuitry inside the memory device. Figure 2 The test pin 200 can be any one of such empty pins or spare pins.

[0057] In one embodiment of this application, the functional circuit corresponding to test pad 111a or test pad 121a can be a circuit under test, that is, test pad 111a or test pad 121a can be a lead-out terminal of a circuit under test.

[0058] In some other embodiments of this application, the functional circuit corresponding to test pad 111a or test pad 121a may also be multiple circuits under test, that is, test pad 111a or test pad 121a may be a test pad shared by the leads of multiple circuits under test.

[0059] The circuit under test and the correspondence between the circuit under test and the test pads can be designed specifically according to the test requirements, and this application does not impose any specific limitations on this.

[0060] In one embodiment of this application, the controller 110 is further configured to store the results of tests performed on the internal circuitry of the storage device into the memory 120 for convenient subsequent reading and management of the test results. According to one embodiment, the test results are stored in the memory 120 via, for example, a connection between test pad 111a and test pad 121a (e.g., ...). Figure 2 (As shown).

[0061] In one embodiment of this application, the excitation signal applied to the test pin 200 may include a signal for testing the functional circuit under test. For example, the excitation signal may be as follows: Figure 3 The waveform signal shown. The specific type of waveform signal can be set according to the test requirements, and the excitation signal can be, for example, a single waveform, or, for example, multiple different waveforms sequentially applied to the test pin 200.

[0062] It should be noted that, in specific embodiments, at least one of the plurality of test pads included in the controller 110 and / or memory 120 may be connected to the test pin 200. Alternatively, at least one of the plurality of test pads included in the controller 110 and / or memory 120 may be connected to the test pin 200 while simultaneously being connected to at least one specific function pad in the controller 110 and / or memory 120. As previously mentioned, the specific function pad may be a pad that, according to memory design standard protocols, is connected from the inside of the package 100 to a specific pin exposed from the package 100 with a defined specific function. For example, Figure 2 The pads 110-1 and 120-1 shown can both be function-specific pads, wherein the test pad 111a is connected to the pad 120-1. In summary, the connection between the test pads inside the package 100 and the function-specific pads and test pins inside the package 100 can be designed and connected according to the specific situation of the internal circuit of the memory device to be tested, and this application does not make specific limitations in this regard.

[0063] Figure 4 This is a flowchart of a method for testing the aforementioned storage device according to an embodiment of this application. See also... Figure 4 The method 2000-2 may include the following steps:

[0064] S1, apply an excitation signal to the test pin;

[0065] S2, the controller receives the excitation signal via the test pad; and

[0066] S3, the controller triggers a test of the functional circuit based on the excitation signal.

[0067] As a specific example, controller 110 includes static random access memory (SRAM). Normal packaging testing in the prior art does not support SRAM detection. However, according to the embodiments of this application, see again... Figure 2 When the pads of the SRAM circuit leads in the storage device 1000 are connected to the test pins, the SRAM detection function can be actively controlled by, for example, the host computer. Taking eMMC (embedded multimedia controller) as an example, the specific operation method is as follows:

[0068] First, the host sends a hibernation command to put storage device 1000 into hibernation mode, which can clear the valid data on SRAM and prevent the test from interfering with the data.

[0069] Secondly, an excitation signal is applied to the test pin 200. Depending on the specific implementation, the signal waveform can be defined in various ways. For example, the following three waveforms can be defined: low-high-low waveform, high-low-high waveform, and low-high waveform. These three different waveforms can, for example, correspond to triggering the detection of the first, second, and third regions of the SRAM.

[0070] Subsequently, the excitation signal is transmitted to the test pad 111a via the connection between the test pin 200 and the test pad 121a. The controller 110 triggers the detection of the first region, the second region and the third region of the SRAM in response to the excitation signal received on the test pad 111a.

[0071] After the test is completed, the controller stores the test results in the memory 120 through the connection between test pad 111a and test pad 121a, and pulls the signal at test pin 200 low as feedback to the host that the test is over.

[0072] In response to the above feedback, the host sends a wake-up command to wake up the storage device 1000 and can read the stored detection results through the standard protocol.

[0073] The method for manufacturing / testing a storage device according to the embodiments of this application can directly detect whether the connection or soldering of some auxiliary circuits inside the package is successful without damaging the storage device, in cases including packaging testing and subsequent testing of the storage device.

[0074] Figure 5 This is a flowchart of a method for manufacturing a storage device according to another embodiment of this application. See also... Figure 5 The method 2000-3 may include the following steps:

[0075] S1, connecting at least one virtual pad in the controller and / or memory to a safety pin; and

[0076] S2, Configure the controller so that it can: in response to an excitation signal applied to the safety pin and received via the virtual pad, make the memory operable, otherwise make the memory inoperable.

[0077] Figure 6 This is a partial internal connection diagram of a storage device manufactured according to another embodiment of this application. (See diagram below.) Figure 6 As shown, the storage device 1000 may include a package 100 and a security pin 400 exposed from the package 100. The package 100 may include a controller 110 and a memory 120. Figure 6 Only one safety pin 400 is shown, but those skilled in the art will understand that there may be multiple safety pins 400.

[0078] Furthermore, the controller 110 may include a virtual pad 112a, which may be a lead-out terminal of the functional circuit in the controller 110; the memory 120 may include a virtual pad 122a, which may be a lead-out terminal of the functional circuit in the memory 120. Multiple virtual pads 112a and 122a may also be present.

[0079] In addition, the controller 110 and the memory 120 may also include some specific function pads, such as Figure 6 The 110-2 shown can be a specific function pad. This specific function pad can also be a lead-out of a specific functional circuit in the controller 110 and memory 120. However, unlike the test pad, this specific function pad can be a specific pin with a defined specific function that has been connected from the inside of the package 100 to the exposed portion of the package 100 according to existing memory design standard protocols (e.g., ...). Figure 6 The pad for pin 500 in the middle. Figure 6 The diagram shows the connection between pad 110-2 and pin 500, which is a connection diagram of any specific pin in the prior art.

[0080] like Figure 6 As shown, the virtual pad 112a in the controller 110 can be connected to the virtual pad 122a in the memory 120, and the virtual pad 122a in the memory 120 can be connected to the security pin 400 of the storage device 1000.

[0081] The controller 110 is configured to control the memory to be in an operable state in response to an excitation signal applied to the safety pin 400, or to make the memory in an inoperable state otherwise. Specifically, the excitation signal applied to the safety pin 400 is transmitted to the virtual pad 112a of the controller 110 via, for example, a connection between the safety pin 400 and virtual pads 122a and 112a. The controller 110 is configured to sense and identify the excitation signal received by the virtual pad 112a, and control the memory to be in an operable or inoperable state based on the excitation signal.

[0082] It will be understood by those skilled in the art that Figure 6 The connection between the virtual pad and the safety pin shown is merely exemplary, and the invention is not limited thereto. According to another embodiment, the virtual pad 112a in the controller 110 may not be connected to the virtual pad 122a in the memory 120, but may be directly connected to the safety pin 400. The controller 110 can control the memory to be in an operable or inoperable state based on the excitation signal.

[0083] In one embodiment of this application, the security pin 400 may be an undefined, empty pin or a spare pin exposed from the package portion 100 with no specific connection. As previously described, the storage device may include a plurality of pins exposed from the package portion 100, wherein, according to the provisions of the memory standard protocol, a portion of the pins are specific pins with defined specific connections, that is, these specific pins are connected to some specific functional circuits inside the storage device as specified by the protocol. For example, pins with defined specific connections may include input / output pins (IO), instruction pins (CMD), and clock pins (CLK), etc. Figure 6 Pin 500 in the package can be a specific pin such as IO, CMD, or CLK. Another portion of the pins exposed from the package 100 are empty pins (NC pins) or spare pins (VC pins), meaning that these pins are not connected to any functional circuitry inside the memory device. Figure 6 The safety pin 400 can be any of the following: a null pin or a spare pin.

[0084] It should be further noted that the virtual pads, specific function pads, specific function pins exposed outside the package 100, and empty or spare pins included inside the package can be connected according to design requirements, and this application does not make specific limitations in this regard.

[0085] In one embodiment of this application, a switch pad 120-2 is provided in the memory 120, and the switch pad 120-2 can change the operating state of the memory 120 in response to an instruction from the controller 110.

[0086] In one embodiment of this application, the virtual pad 112a in the controller 110 is connected to the switch pad 120-2, and the instruction sent by the controller 110 to change the operating state of the memory 120 can be sent to the switch pad 120-2 through this connection.

[0087] It will be understood by those skilled in the art that Figure 6 The connection between the virtual pad 112a and the switch pad 120-2 shown is merely exemplary, and the invention is not limited thereto. According to another embodiment, the virtual pad 122a in the memory 120 is connected to the switch pad 120-2. The controller 110 can send instructions to the switch pad 120-2 based on the excitation signal to control the operating state of the memory.

[0088] In one embodiment of this application, the controller 110 is configured to include a predefined safety signal and to compare a sensed and identified stimulus signal, such as that received by the virtual pad 112a, with the predefined safety signal. If the stimulus signal and the safety signal are the same, the memory 120 is put into an operable state; if the stimulus signal and the safety signal are different, the memory 120 is put into an inoperable state.

[0089] In one embodiment of this application, the waveform of the aforementioned security signal may be, for example, as shown below. Figure 7 The waveform shown is different from that of other storage devices. For different storage device products, the waveform of the required security signal can be customized by the user according to its security level; this application does not impose a uniform limitation on this.

[0090] Furthermore, the target platform or terminal to which the storage device 1000 is applied can be set to have a predefined security signal for the storage device. The target platform or terminal can be set to automatically send the security signal to the security pin 400 of the storage device 1000 when it is powered on. The controller 110 of the storage device 1000 monitors and identifies the security signal received on the corresponding virtual pad connected to the security pin 400. Then the controller will not send an instruction to the switch pad 120-2 to make the memory 120 inoperable through the corresponding connection, that is, the memory can be used normally.

[0091] Conversely, if the storage device 1000 does not receive its predefined security signal after being powered on, for example, if the storage device is desoldered from the target platform or terminal and connected to another standard interface that does not have a predefined security signal, then after powering on, since no security signal is sent to its security pin 400, or a different waveform signal is sent to its security pin 400 after powering on, the controller 110 will monitor and identify this situation and send an instruction to the switch pad 120-2 to drive the memory 120 to be inoperable through, for example, the corresponding virtual pad, so that the memory 120 cannot be read or written, thereby achieving the purpose of protecting the data inside the storage device.

[0092] As a specific example, when the aforementioned switch pad 120-2 is the lead-out of the enable circuit of memory 120, the controller 110 drives the switch pad 120-2 to a high signal, which is equivalent to not selecting memory 120. Afterwards, if normal use of the storage device 1000 is to be restored, a safety signal waveform must be applied to the safety pin 400. The controller 110 monitors and identifies a waveform identical to its predefined safety signal and controls the disconnection, for example, of the corresponding virtual pad and the switch pad 120-2, i.e., disconnecting the instruction to not select memory 120 sent to the switch pad 120-2, allowing the memory to be reselected and its normal read / write function restored.

[0093] Figure 8 This is a flowchart of a data protection method for a storage device according to an embodiment of this application. See also... Figure 8 The method 2000-4 may include the following steps:

[0094] S1, apply an excitation signal to the safety pin;

[0095] S2, the controller receives the excitation signal via the virtual pad; and

[0096] S3, the controller compares the excitation signal with the preset safety signal. If they are the same, the memory is put into an operable state; if they are different, the memory is put into an inoperable state.

[0097] The storage device manufactured according to the embodiments of this application provides corresponding protection for the data information stored inside it, so that it cannot be easily read or changed.

[0098] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a storage device, characterized in that, The storage device includes a package housing a controller and a memory, and test pins and function pins exposed from the package. The function pins include at least input / output (IO) pins, instruction pins (CMD), and clock pins (CLK). The controller and memory also include function pads connected to the function pins. The method includes: Connect the test pads corresponding to the functional circuit leads in the controller and / or the memory to the test pins; and The controller is configured such that it can trigger testing of the functional circuit in response to an excitation signal applied to the test pin and received via the test pad. The excitation signal includes a signal used to test the functional circuit.

2. The method according to claim 1, characterized in that, The functional circuit includes a circuit under test, and the test pad corresponds to the lead-out terminal of the circuit under test.

3. The method according to claim 1, characterized in that, The functional circuit includes multiple circuits under test, and the leads of the multiple circuits under test share the test pad.

4. The method according to claim 1, characterized in that, The method further includes: The controller is configured such that it stores the test results of the functional circuit into the memory.

5. The method according to claim 1, characterized in that, The excitation signal includes one waveform or multiple different waveforms.

6. The method according to claim 1, characterized in that, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to the same test pin. or, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to different test pins. or, The test pads corresponding to the functional circuit leads in the memory are connected to the test pins, and the test pads corresponding to the functional circuit leads in the controller are connected to the test pins via the test pads corresponding to the functional circuit leads in the memory.

7. The method according to claim 1, characterized in that, The test pin is either an empty pin or a spare pin; the test pad is a spare pad.

8. A storage device, characterized in that, include: A package containing the controller and memory; as well as Test pins and functional pins exposed from the package portion, the test pins being connected to test pads corresponding to the functional circuit leads in the controller and / or the memory, the functional pins including at least input / output pins (IO), instruction pins (CMD), and clock pins (CLK), the controller and the memory also including functional pads connected to the functional pins; The controller is configured to trigger a test of the functional circuit in response to an excitation signal applied to the test pin and received via the test pad. The excitation signal includes a signal used to test the functional circuit.

9. The storage device according to claim 8, characterized in that, The functional circuit includes a circuit under test, and the test pad corresponds to the lead-out terminal of the circuit under test.

10. The storage device according to claim 8, characterized in that, The functional circuit includes multiple circuits under test, and the leads of the multiple circuits under test share the test pad.

11. The storage device according to claim 8, characterized in that, The controller is also configured to store the results of testing the functional circuitry into the memory.

12. The storage device according to claim 8, characterized in that, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to the same test pin. or, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to different test pins. or, The test pads corresponding to the functional circuit leads in the memory are connected to the test pins, and the test pads corresponding to the functional circuit leads in the controller are connected to the test pins via the test pads corresponding to the functional circuit leads in the memory.

13. The storage device according to claim 8, characterized in that, The test pin is either an empty pin or a spare pin; the test pad is a spare pad.

14. A method for testing a storage device, the storage device comprising a package encapsulating a controller and a memory, and test pins and functional pins exposed from the package, the functional pins including at least input / output pins (IO), instruction pins (CMD), and clock pins (CLK), the controller and the memory further comprising functional pads connected to the functional pins, characterized in that, include: Apply an excitation signal to the test pin corresponding to the functional circuit lead-out terminal in the controller and / or memory of the storage device; The controller receives the excitation signal via test pads; and The controller triggers a test of the functional circuit based on the excitation signal. The excitation signal includes a signal used to test the functional circuit.

15. The method according to claim 14, characterized in that, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to the same test pin. or, The test pads corresponding to the functional circuit leads in the controller and the test pads corresponding to the functional circuit leads in the memory are connected to different test pins. or, The test pads corresponding to the functional circuit leads in the memory are connected to the test pins, and the test pads corresponding to the functional circuit leads in the controller are connected to the test pins via the test pads corresponding to the functional circuit leads in the memory.

16. The method according to claim 14, characterized in that, The test pin is either an empty pin or a spare pin; the test pad is a spare pad.

17. A method for manufacturing a storage device, characterized in that, The storage device includes a package containing a controller and a memory, and a security pin exposed from the package. The method includes: Connect at least one virtual pad in the controller and / or the memory to the security pin; and The controller is configured such that it can: in response to an excitation signal applied to the security pin and received via the virtual pad, put the memory into an operable or inoperable state.

18. The method according to claim 17, characterized in that, The safety pin is either an empty pin or a spare pin; the virtual pad is a spare pad.

19. The method according to claim 17, characterized in that, The method further includes: A switch pad is provided in the memory, and the switch pad changes the operating state of the memory in response to instructions from the controller.

20. The method according to claim 19, characterized in that, The method further includes: A connection is formed between the virtual pad and the switch pad; wherein the controller sends the instruction to the switch pad through the connection.

21. The method according to claim 17, characterized in that, The method further includes: Safety signals are predefined in the controller; and The controller is configured such that it compares the excitation signal with the safety signal; if they are the same, the memory is put into an operable state; if they are different, the memory is put into an inoperable state.

22. The method according to claim 21, characterized in that, The enable circuit of the memory includes a lead, wherein the method further includes: The controller is configured such that if the excitation signal and the safety signal are not the same after comparison, the controller drives the output terminal to a high signal to prevent the memory from being selected; if the controller recognizes the excitation signal that is the same as the safety signal, the controller drives the output terminal to a signal different from the high signal so that the memory can be selected.

23. The method according to claim 21, characterized in that, The security signals include different waveform signals corresponding to different security levels.

24. A storage device, characterized in that, include: A package containing the controller and memory; as well as A security pin exposed from the package portion is connected to at least one virtual pad in the controller and / or the memory. The controller is configured to enable the memory in response to an excitation signal applied to the security pin and received via the virtual pad, and otherwise disable the memory in response to an excitation signal received via the virtual pad.

25. The storage device according to claim 24, characterized in that, The safety pin is either an empty pin or a spare pin; the virtual pad is a spare pad.

26. The storage device according to claim 24, characterized in that, The memory includes switch pads; and The controller is also configured to send instructions to the switch pads to control the switch pads to change the operating state of the memory.

27. The storage device according to claim 26, characterized in that, The virtual pad is connected to the switch pad, and the instruction can be sent to the switch pad through the connection between the virtual pad and the switch pad.

28. The storage device according to any one of claims 24-27, characterized in that, The controller has pre-stored safety signals; and The controller is also configured to compare the excitation signal with the safety signal; if they are the same, the memory is put into an operable state; if they are different, the memory is put into an inoperable state.

29. The storage device according to claim 28, characterized in that, The memory's enable circuit includes a lead, wherein the controller is further configured to: drive the lead to a high signal to prevent the memory from being selected if the excitation signal is different from the security signal after comparison; and drive the lead to a signal different from the high signal to allow the memory to be selected if the excitation signal that is the same as the security signal is detected.

30. The storage device according to claim 28, characterized in that, The security signals include different waveform signals corresponding to different security levels.

31. A method for data protection of a storage device, characterized in that, include: Apply an excitation signal to the safety pin; The controller receives the excitation signal via a virtual pad; as well as The controller compares the excitation signal with a safety signal pre-stored in the controller. If they are the same, the memory is put into an operable state; if they are different, the memory is put into an inoperable state.

32. The method according to claim 31, characterized in that, The safety pin is either an empty pin or a spare pin; the virtual pad is a spare pad.

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