Schottky diode and manufacturing method, as well as electronic device and manufacturing method

Abstract

The present invention provides a Schottky diode, comprising: a Schottky diode structure, which specifically includes: a substrate, an epitaxial layer, and a plurality of gate trenches; an N+ ion implantation region and a first barrier layer; the N+ ion implantation region is formed in the epitaxial layer on a side away from the plurality of gate trenches; the first barrier layer is formed in the surface layer of the N+ ion implantation region; an interlayer dielectric layer covering the surface of the epitaxial layer and exposing the plurality of gate trenches, the epitaxial layer between the plurality of gate trenches, and the N+ ion implantation region; a first metal layer and a passivation layer, wherein the first metal layer is formed on top of the first barrier layer; the passivation layer wraps around the first metal layer and exposes a portion of the surface of the first metal layer; and a first pad is formed on the exposed surface of the first metal layer. This technical solution solves the technical problem of limiting the effective chip area caused by traditional wire bonding processes. This further achieves the technical effects of reducing the voltage drop of the Schottky diode and improving the overcurrent capability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a Schottky diode and a manufacturing method thereof, as well as an electronic device and a manufacturing method thereof. Background Art

[0002] A Schottky diode is a unidirectionally conductive device made using the Schottky barrier principle formed by the contact between metal and semiconductor. It is a single-carrier conducting device and therefore has an extremely short conduction recovery time. Due to its fast switching speed and extremely low switching losses, it is widely used in circuits such as switching power supplies. TMBS uses charge coupling to reduce the surface electric field of the Schottky diode. Therefore, compared with conventional planar Schottky products, it can better balance reverse leakage current and forward voltage drop, and has better forward conduction and reverse blocking characteristics. Currently, most Schottky products on the market are vertically designed and packaged using traditional wire bonding technology. However, traditional wire bonding technology limits the size of the chip, making it difficult to further increase the effective size of the chip within the same package size, and thus it is impossible to achieve a lower voltage drop and higher overcurrent capability.

[0003] Therefore, developing a new Schottky structure and manufacturing process to increase the effective design area of ​​the chip under the same package size has become a technical focus that needs to be urgently solved by technical personnel in this field. Summary of the Invention

[0004] The present invention provides a Schottky diode and a manufacturing method thereof, as well as an electronic device and a manufacturing method thereof, so as to solve the problem of limitation on the effective area of ​​a chip caused by a traditional wire bonding process.

[0005] According to a first aspect of the present invention, there is provided a Schottky diode, comprising:

[0006] A Schottky diode structure comprising: a substrate, an epitaxial layer, and a plurality of gate trenches; the epitaxial layer is formed on the substrate; the plurality of gate trenches are formed in the epitaxial layer;

[0007] An N+ type ion implantation region and a first barrier layer; the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gate trenches; the first barrier layer is formed in a surface layer of the N+ type ion implantation region;

[0008] an interlayer dielectric layer covering a surface of the epitaxial layer and exposing the plurality of gate trenches, the epitaxial layer between the plurality of gate trenches, and the N+ type ion implantation region;

[0009] a first metal layer and a passivation layer, wherein the first metal layer is formed on top of the first barrier layer; the passivation layer wraps the first metal layer and exposes a portion of the surface of the first metal layer;

[0010] A first pad is formed on the exposed surface of the first metal layer.

[0011] Optionally, the Schottky diode structure further includes:

[0012] a field oxide layer formed on inner walls of the plurality of gate trenches;

[0013] a plurality of gates, respectively filled in the plurality of gate trenches;

[0014] A second barrier layer is formed on a surface layer of the epitaxial layer between the plurality of gate trenches.

[0015] Optionally, the Schottky diode further includes:

[0016] a second metal layer, covering the second barrier layer and a top of the gate;

[0017] Wherein, the passivation layer further wraps the second metal layer and exposes a portion of the surface of the second metal layer;

[0018] The second pad is formed on the exposed surface of the second metal layer.

[0019] According to a second aspect of the present invention, a method for manufacturing a Schottky diode is provided, which is used to manufacture the Schottky diode according to any one of the first aspects of the present invention, comprising:

[0020] The Schottky diode structure, the N+ type ion implantation region, the first barrier layer, and the interlayer dielectric layer are formed; the Schottky diode structure includes: the substrate, the epitaxial layer, and the plurality of gate trenches; the epitaxial layer is formed on the substrate; the plurality of gate trenches are formed in the epitaxial layer; wherein the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gate trenches; the first barrier layer is formed in a surface layer of the N+ type ion implantation region; the interlayer dielectric layer covers the surface of the epitaxial layer and exposes the plurality of gate trenches, the epitaxial layer between the plurality of gate trenches, and the N+ type ion implantation region;

[0021] The first metal layer, the passivation layer and the first pad are formed; wherein the first metal layer is formed on the top of the first barrier layer; the passivation layer wraps the first metal layer and exposes a portion of the surface of the first metal layer; the first pad is formed on the exposed surface of the first metal layer.

[0022] Optionally, when forming the first metal layer, the passivation layer, and the first pad, the method further includes:

[0023] forming the second metal layer and the second pad; the second metal layer covers the epitaxial layer between the plurality of gate trenches and the tops of the plurality of gate trenches;

[0024] The passivation layer further wraps the second metal layer and exposes a portion of the surface of the second metal layer; and the second pad is formed on the exposed surface of the second metal layer.

[0025] Optionally, forming the Schottky diode structure, the N+ type ion implantation region, the first barrier layer, and the interlayer dielectric layer specifically includes:

[0026] Providing the substrate; and forming the epitaxial layer and the plurality of gate trenches;

[0027] forming the field oxide layer;

[0028] forming the plurality of gates; and filling the plurality of gate trenches with the plurality of gates;

[0029] forming the N+ type ion implantation region; wherein the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gates;

[0030] The interlayer dielectric layer is formed; the interlayer dielectric layer covers the surface of the epitaxial layer and exposes the plurality of gates, the epitaxial layer between the plurality of gates, and the N+ type ion implantation region.

[0031] The first barrier layer and the second barrier layer are formed; the first barrier layer is formed in the surface layer of the N+ type ion implantation region; the second barrier layer is formed in the surface layer of the epitaxial layer between the plurality of gates.

[0032] Optionally, forming the N+ type ion implantation region specifically includes:

[0033] forming a photoresist layer on the surface of the epitaxial layer and on top of the plurality of gates;

[0034] exposing and developing the photoresist layer to expose the N+ type ion implantation region to form a patterned photoresist layer; the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gates;

[0035] Implanting N+ type ions into the N+ type ion implantation region and performing annealing to form the N+ type ion implantation region;

[0036] The patterned photoresist layer is removed.

[0037] Optionally, forming the interlayer dielectric layer specifically includes:

[0038] Depositing an interlayer dielectric layer material on the epitaxial layer, the N+ type ion implantation region and the top of the gate;

[0039] The interlayer dielectric material is patterned to form the interlayer dielectric layer.

[0040] According to a third aspect of the present invention, there is provided an electronic device comprising the Schottky diode according to any one of the first aspects of the present invention.

[0041] According to a fourth aspect of the present invention, a method for manufacturing an electronic device includes the method for manufacturing a Schottky diode according to any one of the second aspects of the present invention.

[0042] The present invention provides a Schottky diode that creatively proposes: forming an N+ type ion implantation region in an epitaxial layer on a side away from a plurality of gate trenches, and sequentially forming a first barrier layer, a first metal layer, and a first pad on top of the N+ type ion implantation region in a direction away from the epitaxial layer. Compared to the prior art, the technical solution provided by the present invention forms the first metal layer and the first pad on the front of the Schottky diode structure through the first barrier layer and the N+ type ion implantation region, eliminating the need for a frame structure. This reduces the package size and significantly increases the effective chip area for the same package size, resolving the technical issue of limiting the effective chip area due to traditional wire bonding processes. This further achieves the technical effects of reducing the voltage drop of the Schottky diode and improving the overcurrent capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a schematic diagram of a Schottky diode structure provided by one embodiment of the present invention;

[0045] Figure 2 This is a flow chart of a method for manufacturing a Schottky diode provided by one embodiment of the present invention;

[0046] Figure 3 It is a schematic diagram of a process for forming a Schottky diode structure, the N+ type ion implantation region, the first barrier layer and the interlayer dielectric layer according to an embodiment of the present invention;

[0047] Figure 4-Figure 7 1 is a schematic diagram of a device structure at different process stages of a method for manufacturing a Schottky diode provided by one embodiment of the present invention;

[0048] Description of reference numerals:

[0049] 101-substrate;

[0050] 102- epitaxial layer;

[0051] 103-gate;

[0052] 104-field oxygen layer;

[0053] 105-patterned photoresist layer;

[0054] 106-N+ type ion implantation area;

[0055] 107-interlayer dielectric layer;

[0056] 108-first barrier layer;

[0057] 109-second barrier layer;

[0058] 110-first metal layer;

[0059] 111- second metal layer;

[0060] 112-passivation layer;

[0061] 113-first pad;

[0062] 114 - second solder pad. DETAILED DESCRIPTION

[0063] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0064] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatus.

[0065] A Schottky diode is a unidirectionally conductive device fabricated using the Schottky barrier principle formed by the contact between a metal and a semiconductor. As a single-carrier conducting device, it exhibits an extremely short recovery time. Due to its fast switching speed and extremely low switching losses, it is widely used in circuits such as switching power supplies. TMBS utilizes charge coupling to reduce the surface electric field of the Schottky diode. This reduces the reverse leakage current and forward voltage drop compared to conventional planar Schottky diodes, resulting in superior forward conduction and reverse blocking characteristics. Currently, most Schottky diodes on the market feature a vertical design and utilize traditional wire bonding for packaging. Traditional wire bonding requires separate backside and frontside metallization. The backside metallization, facing away from the substrate, is formed on a frame, with a backside pad formed on the side of the frame facing away from the backside metallization. The frontside metallization is connected to another frame via a reverse wire bonding arc structure, with the frame formed on another pad. Therefore, traditional wire bonding requires the device's two terminals to be connected from the front and back sides, respectively, and requires separate frames.

[0066] Therefore, the traditional wire bonding process will limit the size of the chip, and it is difficult to further increase the effective size of the chip under the same package size, and thus it is impossible to achieve lower voltage drop and higher overcurrent capability.

[0067] In view of this, the inventors of this application will introduce CSP packaging technology into the packaging of Schottky diodes, specifically by forming an N+ type ion implantation region and a metal barrier layer in the surface layer of the epitaxial layer on the side away from several gates, wherein the metal barrier layer is formed on the top of the N+ type ion implantation region; and transferring the back metal and the pad to the top of the metal barrier layer; it can be seen that the technical solution provided by this application uses CSP technology to package Schottky diodes, without the need to separately produce a back frame and a front frame, reducing the size required for the wire bonding process. Therefore, under the same package size, the effective size of the chip can be increased, thereby achieving a lower voltage drop and a higher overcurrent capability of the device.

[0068] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0069] Please refer to Figure 1-Figure 7 According to an embodiment of the present invention, a Schottky diode is provided, comprising:

[0070] A Schottky diode structure, comprising: a substrate 101, an epitaxial layer 102, and a plurality of gate trenches; the epitaxial layer 102 is formed on the substrate 101; the plurality of gate trenches are formed in the epitaxial layer 102;

[0071] An N+ type ion implantation region 106 and a first barrier layer 108; the N+ type ion implantation region 106 is formed in the epitaxial layer 102 on a side away from the plurality of gate trenches; the first barrier layer 108 is formed in a surface layer of the N+ type ion implantation region 106;

[0072] an interlayer dielectric layer 107 covering a surface of the epitaxial layer 102 and exposing the plurality of gate trenches, the epitaxial layer 102 between the plurality of gate trenches, and the N+ type ion implantation region 106;

[0073] a first metal layer 110 and a passivation layer 112 , wherein the first metal layer 110 is formed on top of the first barrier layer 108 ; the passivation layer 112 wraps around the first metal layer 110 and exposes a portion of the surface of the first metal layer 110 ;

[0074] The first pad 113 is formed on the surface of the first metal layer 110 that is exposed. The structure of the Schottky diode is as follows. Figure 1 shown.

[0075] The present invention provides a Schottky diode that incorporates CSP packaging technology and creatively proposes: forming an N+ ion implantation region in an epitaxial layer on a side away from a plurality of gate trenches, and sequentially forming a first barrier layer, a first metal layer, and a first pad on top of the N+ ion implantation region in a direction away from the epitaxial layer. Compared to the prior art, the present invention provides a technical solution that forms the first metal layer and the first pad on the front of the Schottky diode structure through the first barrier layer and the N+ ion implantation region, eliminating the need for a frame structure. This reduces the package size and significantly increases the effective chip area for a given package size, resolving the technical issue of limiting the effective chip area due to traditional wire bonding processes. This further achieves the technical effects of reducing the voltage drop of the Schottky diode and improving its overcurrent capability.

[0076] In one embodiment, the Schottky diode structure further includes:

[0077] A field oxide layer 104 is formed on the inner walls of the plurality of gate trenches;

[0078] a plurality of gates, respectively filled in the plurality of gate trenches;

[0079] The second barrier layer 109 is formed on the surface of the epitaxial layer 102 between the gate trenches.

[0080] In one embodiment, the Schottky diode further includes:

[0081] a second metal layer 111 covering the second barrier layer 109 and a top of the gate 103;

[0082] The passivation layer 112 further wraps the second metal layer 111 and exposes a portion of the surface of the second metal layer 111;

[0083] The second pad 114 is formed on the exposed surface of the second metal layer 111 .

[0084] Secondly, according to an embodiment of the present invention, a method for manufacturing a Schottky diode is also provided. The flow chart of the method for manufacturing a Schottky diode is as follows: Figure 2 As shown, the method is used to manufacture the Schottky diode described in any one of the aforementioned embodiments of the present invention, comprising:

[0085] S11: forming the Schottky diode structure, the N+ type ion implantation region 106, the first barrier layer 108 and the interlayer dielectric layer 107; the Schottky diode structure includes: the substrate 101, the epitaxial layer 102 and the plurality of gate trenches; the epitaxial layer 102 is formed on the substrate 101; the plurality of gate trenches are formed in the epitaxial layer 102; wherein the N+ type ion implantation region 106 is formed in the epitaxial layer 102 on a side away from the plurality of gate trenches; the first barrier layer 108 is formed in the surface layer of the N+ type ion implantation region 106; the interlayer dielectric layer 107 covers the surface of the epitaxial layer 102 and exposes the plurality of gate trenches, the epitaxial layer 102 between the plurality of gate trenches and the N+ type ion implantation region 106;

[0086] S12: forming the first metal layer 110, the passivation layer 112 and the first pad 113; wherein the first metal layer 110 is formed on the top of the first barrier layer 108; the passivation layer 112 wraps the first metal layer 110 and exposes a portion of the surface of the first metal layer 110; the first pad 113 is formed on the exposed surface of the first metal layer 110, such as Figure 7 shown.

[0087] According to the present invention, a method for manufacturing a Schottky diode is provided. By introducing CSP packaging technology, the Schottky diode produced by the present invention reduces the package size compared to the existing technology, greatly increasing the effective chip area under the same package size, and solving the technical problem of the chip effective area being limited by the traditional wire bonding process. This further achieves the technical effects of reducing the voltage drop of the Schottky diode and improving the overcurrent capability.

[0088] In one embodiment, step S12, when forming the first metal layer 110, the passivation layer 112 and the first pad 113, further includes:

[0089] The second metal layer 111 and the second pad 114 are formed; the second metal layer 111 covers the epitaxial layer 102 between the plurality of gate trenches and the tops of the plurality of gate trenches;

[0090] The passivation layer 112 further wraps the second metal layer 111 and exposes a portion of the surface of the second metal layer 111; the second pad 114 is formed on the exposed surface of the second metal layer 111, wherein the device structure after forming the first metal layer 110, the second metal layer 111 and the passivation layer 112 is as follows Figure 7 shown.

[0091] In one embodiment, step S11, forming the Schottky diode structure, the N+ type ion implantation region 106, the first barrier layer 108 and the interlayer dielectric layer 107, specifically includes: step S111 to step S116 (the specific flow diagram of step S11 is shown in FIG. Figure 3 shown):

[0092] Step S111: providing the substrate 101; and forming the epitaxial layer 102 and the plurality of gate trenches;

[0093] Step S112: forming the field oxide layer 104;

[0094] Step S113: forming the plurality of gates; filling the plurality of gate trenches with the plurality of gates, such as Figure 4 As shown;

[0095] Step S114: forming the N+ type ion implantation region 106; the N+ type ion implantation region 106 is formed in the epitaxial layer 102 on the side away from the plurality of gates;

[0096] In one embodiment, step S114, forming the N+ type ion implantation region 106, specifically includes: step S1141-step S1142:

[0097] Step S1141: forming a photoresist layer on the surface of the epitaxial layer 102 and on top of the plurality of gates;

[0098] Step S1142: exposing and developing the photoresist layer to expose the N+ type ion implantation region 106 to form a patterned photoresist layer 105; the N+ type ion implantation region 106 is formed in the epitaxial layer 102 on a side away from the plurality of gates;

[0099] N+ type ions are implanted into the N+ type ion implantation region 106, and annealing is performed to form the N+ type ion implantation region 106. Figure 5 As shown;

[0100] The patterned photoresist 105 layer is removed.

[0101] Step S115 : forming the interlayer dielectric layer 107 ; the interlayer dielectric layer 107 covers the surface of the epitaxial layer 102 and exposes the gates, the epitaxial layer 102 between the gates, and the N+ type ion implantation region 106 .

[0102] Before forming the interlayer dielectric layer 107 , the process further includes removing the field oxide layer 104 on the top of the epitaxial layer 102 .

[0103] In one embodiment, step S115, forming the interlayer dielectric layer 107 specifically includes: step S1151 to step S116:

[0104] Step S1151 : depositing an interlayer dielectric layer material on top of the epitaxial layer 102 , the N+ type ion implantation region 106 and the gate 103 ;

[0105] Step S1152: Patterning the interlayer dielectric material to form the interlayer dielectric layer 107, such as Figure 6 shown.

[0106] Step S116: forming the first barrier layer 108 and the second barrier layer 109; the first barrier layer 108 is formed in the surface layer of the N+ type ion implantation region 106; the second barrier layer 109 is formed in the surface layer of the epitaxial layer 102 between the plurality of gates, as shown in FIG. Figure 6 shown.

[0107] The size of a chip manufactured using a conventional wire bonding process is at most 30-50% of the package size. In the technical solution provided by the present invention, the chip size can be made close to the package size.

[0108] In one specific embodiment, the Schottky diode produced using the present invention has an effective chip area of ​​0.6 x 0.3 mm, compared to a conventional DFN0603 type with an effective chip area of ​​0.21 x 0.21 mm, while maintaining the same overall packaged dimensions. The DFN0603 designation refers to a DFN package with an overall packaged size of 0.6 x 0.3 mm.

[0109] In another specific embodiment, under the same overall packaged dimensions, compared to the conventional DFN1006 type with a chip effective area of ​​0.5*0.45mm, the Schottky diode manufactured with the technical solution provided by the present invention has a chip effective area of ​​1.0*0.6mm. The DFN1006 refers to a DFN package type with an overall packaged dimension of 1.0*0.6mm.

[0110] In other specific embodiments, under the same overall packaged dimensions, compared to the conventional DFN1610 type with a chip effective area of ​​0.85*0.85mm, the Schottky diode manufactured with the technical solution provided by the present invention has a chip effective area of ​​1.6*1.0mm. DFN1610 refers to a DFN package type with an overall packaged dimension of 1.6*1.0mm.

[0111] In addition, according to an embodiment of the present invention, an electronic device is provided, comprising the Schottky diode according to any one of the aforementioned embodiments of the present invention.

[0112] Finally, according to an embodiment of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing the Schottky diode according to any one of the aforementioned embodiments of the present invention.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Schottky diode, characterized in that: include: A Schottky diode structure comprising: a substrate, an epitaxial layer, a field oxide layer, a plurality of gates, a second barrier layer, and a plurality of gate trenches; the epitaxial layer is formed on the substrate; the plurality of gate trenches are formed in the epitaxial layer; the field oxide layer is formed on the inner walls of the plurality of gate trenches; a plurality of gates are respectively filled in the plurality of gate trenches; and the second barrier layer is formed on the surface of the epitaxial layer between the plurality of gate trenches; An N+ type ion implantation region and a first barrier layer; the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gate trenches; the first barrier layer is formed in a surface layer of the N+ type ion implantation region; an interlayer dielectric layer covering a surface of the epitaxial layer and exposing the plurality of gate trenches, the epitaxial layer between the plurality of gate trenches, and the N+ type ion implantation region; a first metal layer and a passivation layer, wherein the first metal layer is formed on top of the first barrier layer; the passivation layer wraps the first metal layer and exposes a portion of the surface of the first metal layer; a first pad formed on the exposed surface of the first metal layer; a second metal layer, covering the second barrier layer and a top of the gate; Wherein, the passivation layer further wraps the second metal layer and exposes a portion of the surface of the second metal layer; The second pad is formed on the exposed surface of the second metal layer.

2. A method for manufacturing a Schottky diode, for manufacturing the Schottky diode according to claim 1, characterized in that: include: forming the Schottky diode structure, the N+ type ion implantation region, the first barrier layer and the interlayer dielectric layer; The Schottky diode structure includes: the substrate, the epitaxial layer, and the plurality of gate trenches; the epitaxial layer is formed on the substrate; the plurality of gate trenches are formed in the epitaxial layer; wherein the N+ type ion implantation region is formed in the epitaxial layer away from the plurality of gate trenches; the first barrier layer is formed in the surface layer of the N+ type ion implantation region; the interlayer dielectric layer covers the surface of the epitaxial layer and exposes the plurality of gate trenches, the epitaxial layer between the plurality of gate trenches, and the N+ type ion implantation region; The first metal layer, the passivation layer and the first pad are formed; wherein the first metal layer is formed on the top of the first barrier layer; the passivation layer wraps the first metal layer and exposes a portion of the surface of the first metal layer; the first pad is formed on the exposed surface of the first metal layer.

3. The method for manufacturing a Schottky diode according to claim 2, wherein: When forming the first metal layer, the passivation layer and the first pad, the method further includes: forming the second metal layer and the second pad; the second metal layer covers the epitaxial layer between the plurality of gate trenches and the tops of the plurality of gate trenches; The passivation layer further wraps the second metal layer and exposes a portion of the surface of the second metal layer; and the second pad is formed on the exposed surface of the second metal layer.

4. The method for manufacturing a Schottky diode according to claim 3, wherein: Forming the Schottky diode structure, the N+ type ion implantation region, the first barrier layer, and the interlayer dielectric layer specifically includes: Providing the substrate; and forming the epitaxial layer and the plurality of gate trenches; forming the field oxide layer; forming the plurality of gates; and filling the plurality of gate trenches with the plurality of gates; forming the N+ type ion implantation region; wherein the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gates; forming the interlayer dielectric layer; the interlayer dielectric layer covers the surface of the epitaxial layer and exposes the plurality of gates, the epitaxial layer between the plurality of gates, and the N+ type ion implantation region; The first barrier layer and the second barrier layer are formed; the first barrier layer is formed in the surface layer of the N+ type ion implantation region; the second barrier layer is formed in the surface layer of the epitaxial layer between the plurality of gates.

5. The method for manufacturing a Schottky diode according to claim 4, wherein: Forming the N+ type ion implantation region specifically includes: forming a photoresist layer on the surface of the epitaxial layer and on top of the plurality of gates; exposing and developing the photoresist layer to expose the N+ type ion implantation region to form a patterned photoresist layer; the N+ type ion implantation region is formed in the epitaxial layer on a side away from the plurality of gates; Implanting N+ type ions into the N+ type ion implantation region and performing annealing to form the N+ type ion implantation region; The patterned photoresist layer is removed.

6. The method for manufacturing a Schottky diode according to claim 5, wherein: Forming the interlayer dielectric layer specifically includes: Depositing an interlayer dielectric layer material on the epitaxial layer, the N+ type ion implantation region and the top of the gate; The interlayer dielectric material is patterned to form the interlayer dielectric layer.

7. An electronic device comprising the Schottky diode according to claim 1.

8. A method for manufacturing an electronic device, comprising the method for manufacturing the Schottky diode according to any one of claims 2 to 6.

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