Phase interpolator and phase buffer circuit

Abstract

The present disclosure relates to a phase interpolator and a phase buffer circuit. The phase interpolator includes a plurality of phase interpolator circuit systems. The plurality of phase interpolator circuit systems generate output clock signals from an output node in response to a plurality of phase control bits and a plurality of clock signals. The phases of the plurality of clock signals differ from one another. Each phase interpolator circuit system includes a plurality of phase buffer circuits. Each phase buffer circuit is turned on in response to first and second bits of the phase control bits to generate a signal component in the output clock signal in response to a corresponding clock signal in the plurality of clock signals. Each phase buffer circuit includes first and second resistors and transmits one of a first and a second voltage to the output node in response to the corresponding clock signal, wherein the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.

Description

Technical Field

[0001] The present invention relates to a phase interpolator, and more particularly to a phase interpolator and a phase buffer circuit with high linearity. Background Art

[0002] Conventional phase interpolators often use multiple differential pair circuits and current source circuits to control current, and convert the current through resistors to generate an output clock signal. These circuits discharge through current and charge through resistors. The above-mentioned charging and discharging behavior will cause the charging and discharging speed or time constant to be asymmetric, affecting linearity. In other technologies, the phase interpolator is implemented using a circuit based on an inverter. However, under the influence of process variations, the offsets generated by P-type transistors and N-type transistors under process variations are different. As a result, the output common-mode level of the phase interpolator will be inaccurate. In addition, if the swing of the output clock signal is large, the transistors in the differential pair and / or current source circuit will operate in a nonlinear region, resulting in poor linearity of the output clock signal. Summary of the Invention

[0003] In some embodiments, the phase interpolator includes a plurality of phase interpolator circuit systems. The plurality of phase interpolator circuit systems is configured to generate output clock signals from an output node in response to a plurality of phase control bits and a plurality of clock signals. The clock signals have different phases, and each of the phase interpolator circuit systems includes a plurality of phase buffer circuits. Each of the phase buffer circuits is configured to be turned on in response to a first bit and a second bit of the phase control bits to generate a signal component in the output clock signal in response to a corresponding clock signal in the clock signals. Each of the phase buffer circuits includes a first resistor and a second resistor, and is configured to transmit one of a first voltage and a second voltage to the output node in response to the corresponding clock signal, wherein the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.

[0004] In some embodiments, the phase buffer circuit includes a first resistor, a second resistor, a first switch, a second switch, a third switch, and a fourth switch. One end of the first resistor is configured to receive a first voltage. One end of the second resistor is configured to receive a second voltage. A first end of the first switch is coupled to the other end of the first resistor, and a control end of the first switch is configured to receive a clock signal. A first end of the second switch is coupled to the second end of the first switch, a second end of the second switch is coupled to an output node to generate a signal component, and a control end of the second switch is configured to receive a first phase control bit. A first end of the third switch is coupled to the output node, and a control end of the third switch is configured to receive a second phase control bit. A first end of the fourth switch is coupled to the second end of the third switch, a second end of the fourth switch is coupled to the other end of the second resistor, and a control end of the fourth switch is configured to receive the clock signal.

[0005] The features, implementation and effects of the present invention are described in detail below with reference to the drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a phase interpolator according to some embodiments of the present invention is provided;

[0007] Figure 2 According to some embodiments of the present invention Figure 1 A schematic diagram showing the relationship between the phase of the output clock signal and multiple phase control bits;

[0008] Figure 3A According to some embodiments of the present invention Figure 1 A circuit schematic diagram of a plurality of phase interpolator circuit systems in FIG. 1 ; and

[0009] Figure 3B According to some embodiments of the present invention Figure 1 Circuit schematic diagram of a multiple phase interpolator circuit system in FIG. DETAILED DESCRIPTION

[0010] All terms used herein have their ordinary meanings. The definitions of the aforementioned terms in commonly used dictionaries and any examples of their use discussed herein are provided for illustrative purposes only and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments described herein.

[0011] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action between two or more components. As used herein, the term "circuitry" may refer to a single system formed by at least one circuit, and the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive component connected in a certain manner to process signals.

[0012] As used herein, the term "and / or" encompasses any combination of one or more of the listed associated items. Terms such as first, second, and third are used herein to describe and identify individual elements. Thus, a first element herein could also be referred to as a second element without departing from the intent of the present invention. For ease of understanding, similar elements in the drawings will be designated with the same reference numerals.

[0013] Figure 1 A schematic diagram of a phase interpolator 100 according to some embodiments of the present invention is shown. The phase interpolator 100 includes a plurality of phase interpolator circuit systems 110, 120, 130, and 140. The plurality of phase interpolator circuit systems 110, 120, 130, and 140 are configured to generate an output clock signal CKO from an output node N1 in response to a plurality of phase control bits ST[0]-ST

[63] and STB[0]-STB

[63] and a plurality of clock signals CK1-CK4.

[0014] In some embodiments, the phases of the multiple clock signals CK1 to CK4 are different from each other. For example, the phase of the clock signal CK1 is 0 degrees, the phase of the clock signal CK2 is 90 degrees, the phase of the clock signal CK3 is 180 degrees, and the phase of the clock signal CK4 is 270 degrees. In some embodiments, the corresponding ones of the multiple phase control bits ST[0] to ST

[63] have opposite logical values to the corresponding ones of STB[0] to STB

[63] . For example, when the phase control bit ST[0] has a logical value of 1, the phase control bit STB[0] has a logical value of 0. Alternatively, when the phase control bit ST[0] has a logical value of 0, the phase control bit STB[0] has a logical value of 1. Similarly, the corresponding relationship between the remaining multiple phase control bits ST[1] to ST

[63] and STB[1] to STB

[63] should be understood.

[0015] In detail, the phase interpolator circuit system 110 generates a signal component S1 in response to a plurality of phase control bits ST[0]-ST

[15] and STB[0]-STB

[15] and a clock signal CK1, and outputs the signal component S1 to the output node N1. The signal component S1 is used to form the output clock signal CKO. In other words, the signal component S1 is a portion of the clock signal CKO. The plurality of phase control bits ST[0]-ST

[15] (and / or the plurality of phase control bits STB[0]-STB

[15] ) can be used to set the proportion of the clock signal CK1 in the clock signal CKO. For example, if the number of bits with a preset logic value (e.g., a logic value of 0) in the plurality of phase control bits ST[0]-ST

[15] is greater, the proportion of the clock signal CK1 in the clock signal CKO is higher. Conversely, if the number of bits with a preset logic value (e.g., a logic value of 0) in the plurality of phase control bits ST[0]-ST

[15] is smaller, the proportion of the clock signal CK1 in the clock signal CKO is lower.

[0016] Similarly, the phase interpolator circuit system 120 generates a signal component S2 in response to a plurality of phase control bits ST

[16] -ST

[31] and STB

[16] -STB

[31] and a clock signal CK2, and outputs the signal component S2 to the output node N1. The phase interpolator circuit system 130 generates a signal component S3 in response to a plurality of phase control bits ST

[32] -ST

[47] and STB

[32] -STB

[47] and a clock signal CK3, and outputs the signal component S3 to the output node N1. The phase interpolator circuit system 140 generates a signal component S4 in response to a plurality of phase control bits ST

[48] -ST

[63] and STB

[48] -STB

[63] and a clock signal CK4, and outputs the signal component S4 to the output node N1. The plurality of signal components S1-S4 can be added at the output node N1 to form the output clock signal CKO.

[0017] In some embodiments, each of the plurality of phase interpolator circuit systems 110, 120, 130, and 140 includes a plurality of phase buffer circuits ( Figure 1 Not shown). Each phase buffer circuit includes a first resistor and a second resistor. The phase buffer circuit can transmit one of a first voltage and a second voltage to the output node N1 according to the corresponding clock signal (i.e., the corresponding one of the clock signals CK1 to CK4), wherein the first voltage is transmitted to the output node N1 via the first resistor, and the second voltage is transmitted to the output node N1 via the second resistor. In this way, the first resistor and the second resistor can set the common mode level of the output node N1 and effectively maintain the common mode level under the influence of process variation, so as to improve the linearity and available swing of the output clock signal. The setting method here will be referred to later. Figure 3A and Figure 3B illustrate.

[0018] Figure 2 According to some embodiments of the present invention Figure 1 Schematic diagram of the relationship between the phase of the output clock signal CKO and multiple phase control bits ST[0]~ST

[63] . Figure 2 As shown, the phase of the output clock signal CKO can be divided into four quadrants. In the first quadrant, the phase of the output clock signal CKO can be 0 to 90 degrees. In the second quadrant, the phase of the output clock signal CKO can be 90 to 180 degrees. In the third quadrant, the phase of the output clock signal CKO can be 180 to 270 degrees. In the fourth quadrant, the phase of the output clock signal CKO can be 270 to 0 degrees.

[0019] In detail, when the plurality of phase control bits ST[0] to ST

[15] all have a first logic value (e.g., logic value 0 (i.e., the aforementioned preset logic value)) and the remaining plurality of phase control bits ST

[16] to ST

[63] all have a second logic value (e.g., logic value 1), the phase interpolator 100 can output an output clock signal CKO having a phase of 0 degrees. Then, the plurality of phase control bits ST[0] to ST

[63] can be shifted to gradually increase the phase of the output clock signal CKO. When the plurality of phase control bits ST

[16] to ST

[31] have a preset logic value (e.g., logic value 0) and the remaining plurality of phase control bits ST[0] to ST

[15] and ST

[32] to ST

[63] all have a second logic value (e.g., logic value 1), the phase interpolator 100 can output an output clock signal CKO having a phase of 90 degrees.

[0020] Similarly, when the plurality of phase control bits ST

[32] to ST

[47] all have a preset logic value (e.g., logic value 0) and the remaining plurality of phase control bits ST[0] to ST

[31] and ST

[48] to ST

[63] all have a second logic value (e.g., logic value 1), the phase interpolator 100 can output an output clock signal CKO having a phase of 180 degrees. When the plurality of phase control bits ST

[48] to ST

[63] all have a preset logic value (e.g., logic value 0) and the remaining plurality of phase control bits ST[0] to ST

[47] all have a second logic value (e.g., logic value 1), the phase interpolator 100 can output an output clock signal CKO having a phase of 270 degrees.

[0021] Figure 2 The encoding method of the multiple phase control bits ST[0] to ST

[63] is used as an example, and the present invention is not limited thereto. In some embodiments, an additional quadrant control signal can be added to switch the quadrant corresponding to the phase of the output clock signal CKO.

[0022] Figure 3AAccording to some embodiments of the present invention Figure 1 Schematic diagram of the phase interpolator circuit system 110 and the phase interpolator circuit system 120 in FIG. Figure 3B According to some embodiments of the present invention Figure 1 Schematic diagram of the phase interpolator circuit system 130 and the phase interpolator circuit system 140 in FIG. It should be understood that Figure 3A The phase interpolator circuit system 110 and the phase interpolator circuit system 120 and Figure 3B The phase interpolator circuit system 130 and the phase interpolator circuit system 140 together form Figure 1 Phase interpolator 100.

[0023] like Figure 3A As shown, the phase interpolator circuit system 110 includes a plurality of phase buffer circuits 110[0] to 110

[15] . Each of the plurality of phase buffer circuits 110[0] to 110

[15] receives a corresponding bit (hereinafter referred to as the first bit) among a plurality of phase control bits ST[0] to ST

[15] , a corresponding bit (hereinafter referred to as the second bit) among a plurality of phase control bits STB[0] to STB

[15] , and a clock signal CK1. Each of the plurality of phase buffer circuits 110[0] to 110

[15] is configured to be turned on according to the first bit and the second bit to generate a portion of the signal component S1 according to the clock signal CK1. For example, the phase buffer circuit 110[0] receives the phase control bit ST[0] (i.e., the first bit), the phase control bit STB[0] (i.e., the second bit), and the clock signal CK1 to generate a portion of the signal component S1. Phase buffer circuit 110

[15] receives phase control bit ST

[15] (i.e., the first bit), phase control bit STB

[15] (i.e., the second bit), and clock signal CK1 to generate a portion of signal component S1. Similarly, the corresponding relationship between the multiple phase buffer circuits 110[0]-110

[15] , the multiple phase control bits ST[0]-ST

[15] , and the multiple phase control bits STB[0]-STB

[15] can be understood.

[0024] Similarly, the phase interpolator circuit system 120 includes a plurality of phase buffer circuits 120[0]-120

[15] . Each of the plurality of phase buffer circuits 120[0]-120

[15] receives a corresponding bit of the plurality of phase control bits ST

[16] -ST

[31] , a corresponding bit of the plurality of phase control bits STB

[16] -STB

[31] , and a clock signal CK2, and the plurality of phase buffer circuits 120[0]-120

[15] are used to generate a signal component S2 in response to the plurality of phase control bits ST

[16] -ST

[31] , the plurality of phase control bits STB

[16] -STB

[31] , and the clock signal CK2. The correspondence between the plurality of phase buffer circuits 120[0]-120

[15] , the plurality of phase control bits ST

[16] -ST

[31] , and the plurality of phase control bits STB

[16] -STB

[31] can be referred to the configuration method of the phase interpolator circuit system 110, and will not be described in detail here.

[0025] Each of the plurality of phase buffer circuits 110[0] to 110

[15] and the plurality of phase buffer circuits 120[0] to 120

[15] has the same circuit structure. Taking the phase buffer circuit 110[0] as an example, the phase buffer circuit 110[0] includes a resistor R1 and a resistor R2. The phase buffer circuit 110[0] is used to selectively transmit a first voltage to the output node N1 via the resistor R1 or to transmit a second voltage to the output node N1 via the resistor R2. In some embodiments, the first voltage is higher than the second voltage. For example, the first voltage may be the supply voltage VDD, and the second voltage may be the ground voltage GND. By the above configuration, the resistors R1 and R2 can set the common mode level of the output node N1.

[0026] In detail, the phase buffer circuit 110[0] further includes a plurality of switches T1 to T4. One end of the resistor R1 receives the supply voltage VDD, and the other end of the resistor R1 is coupled to the first end (e.g., source) of the switch T1. The second end (e.g., drain) of the switch T1 is coupled to the first end of the switch T2, and the control end (e.g., gate) of the switch T1 receives the clock signal CK1. The switch T1 can be selectively turned on in response to the clock signal CK1. The second end of the switch T2 is coupled to the first end (e.g., drain) of the switch T3 and the output node N1, and the control end of the switch T2 receives the phase control bit ST[0]. The switch T2 can be selectively turned on in response to the phase control bit ST[0] to generate a portion of the signal component S1 to the output node N1. The second end (e.g., source) of the switch T3 is coupled to the first end of the switch T4, and the control end (e.g., gate) of the switch T3 receives the phase control bit STB[0]. Switch T3 can be selectively turned on in response to phase control bit STB[0] to generate a portion of signal component S1 to output node N1. One end of resistor R2 receives ground voltage GND. A second end of switch T4 is coupled to the other end of resistor R2. A control end of switch T4 receives clock signal CK1. Switch T4 can be selectively turned on in response to clock signal CK1.

[0027] In some embodiments, switches T1 and T2 are P-type transistors, and switches T3 and T4 are N-type transistors. When the phase control bit ST[0] has a predetermined logic value (e.g., a logic value of 0) and the clock signal CK1 has a low level, switches T1 and T2 are turned on. Under this condition, the supply voltage VDD can be transmitted to the output node N1 via the resistor R1. In other words, when both switches T1 and T2 are turned on, the phase buffer circuit 110[0] can output a signal component (i.e., a portion of the signal component S1) having a high level (i.e., the supply voltage VDD) to the output node N1. Alternatively, when the phase control bit ST[0] has a predetermined logic value (e.g., a logic value of 0) and the clock signal CK1 has a high level, switches T3 and T4 are turned on. Under this condition, the ground voltage GND can be transmitted to the output node N1 via the resistor R2. In other words, when both switches T3 and T4 are turned on, the phase buffer circuit 110[0] can output a signal component having a low level (i.e., ground voltage GND) (i.e., a portion of the signal component S1) to the output node N1. Similarly, the operations of the remaining phase buffer circuits 110[1]-110

[15] and the plurality of phase buffer circuits 120[0]-120

[15] can be understood.

[0028] In some related technologies, multiple phase buffers in a phase interpolator are implemented using current-mode logic circuits. In these technologies, each current-mode logic circuit is implemented using a differential input pair and a current source circuit. Resistors are used to convert the currents generated by all current-mode logic circuits into output clock signals. Because the offsets of the current source circuits and resistors vary due to process variations, the output common-mode level of the phase interpolator may be inaccurate. Furthermore, if the output clock signal swing is large, the transistors in the differential input pair and / or the current source circuit may operate in a nonlinear region, causing the output clock signal swing to be distorted (i.e., reduced linearity).

[0029] Compared to the above-mentioned techniques, in some embodiments of the present invention, resistors R1 and R2 can divide the supply voltage VDD and the ground voltage GND to set the common-mode level of the output node N1. For example, since the supply voltage VDD and the ground voltage GND are DC voltages, the supply voltage VDD and the ground voltage GND can be divided by resistors R1, R2, and multiple switches T1 to T4 (even if multiple switches T1 to T4 are not conducting) to set the common-mode level of the output node N1. In some embodiments, the resistance of each of resistors R1 and R2 can be higher than the equivalent resistance of each of the multiple switches T1 to T4. In this way, the voltage division result of the supply voltage VDD and the ground voltage GND can be mainly determined by resistors R1 and R2. Therefore, even if the P-type transistor and the N-type transistor have different offsets, the common-mode level of the output node N1 can still be set by resistors R1 and R2. In some embodiments, resistors R1 and R2 can be implemented using the same or similar layout. For example, each of resistors R1 and R2 can be implemented using (but not limited to) polysilicon resistors. With this configuration, resistors R1 and R2 can produce similar offsets under process variations, ensuring that the common-mode level of output node N1 remains stable (e.g., maintained at half the sum of the supply voltage VDD and the ground voltage GND). This ensures that the swing of the output clock signal CKO remains symmetrical.

[0030] In addition, if Figure 3AAs shown, in the phase buffer circuit 110[0], some switches (i.e., switch T2 and switch T3) are directly connected to the output node N1, and another part of the switches (i.e., switch T1 and switch T4) are not directly connected to the output node N1. In some embodiments, switch T2 and switch T3 receive multiple phase control bits ST[0] and STB[0] but do not receive the clock signal CK1, and switch T1 and switch T4 receive the clock signal CK1 and are selectively turned on in response to the clock signal CK1. With the above-mentioned configuration, some of the switches directly connected to the output node N1 are selectively turned on in response to multiple phase control bits ST[0] and STB[0] (rather than the clock signal CK1). In this way, the switching of the clock signal CK1 does not directly affect the output node N1, which can reduce the jitter of the output clock signal CKO generated during the phase switching process.

[0031] like Figure 3B As shown, the phase interpolator circuit system 130 includes a plurality of phase buffer circuits 130[0]-130

[15] , and the phase interpolator circuit system 140 includes a plurality of phase buffer circuits 140[0]-140

[15] . Each of the plurality of phase buffer circuits 130[0]-130

[15] receives a corresponding bit of a plurality of phase control bits ST

[32] -ST

[47] , a corresponding bit of a plurality of phase control bits STB

[32] -STB

[47] , and a clock signal CK3. The plurality of phase buffer circuits 130[0]-130

[15] are used to generate a signal component S3 in response to the plurality of phase control bits ST

[32] -ST

[47] , the plurality of phase control bits STB

[32] -STB

[47] , and the clock signal CK3. Each of the plurality of phase buffer circuits 140[0]-140

[15] receives a corresponding bit of the plurality of phase control bits ST

[48] -ST

[63] , a corresponding bit of the plurality of phase control bits STB

[48] -STB

[63] , and a clock signal CK4. The plurality of phase buffer circuits 140[0]-140

[15] are configured to generate a signal component S4 in response to the plurality of phase control bits ST

[48] -ST

[63] , the plurality of phase control bits STB

[48] -STB

[63] , and the clock signal CK4.

[0032] Each of the plurality of phase buffer circuits 110[0]-110

[15] , 130[0]-130

[15] and 140[0]-140

[15] has the same circuit structure. The configuration and / or operation of the plurality of phase buffer circuits 130[0]-130

[15] and 140[0]-140

[15] can be referred to. Figure 3A The configuration of the multiple phase buffer circuits 110[0] to 110

[15] is described in detail, so it will not be repeated here.

[0033] As previously mentioned, in some embodiments, a quadrant control signal may be added to switch the quadrant corresponding to the phase of the output clock signal CKO. In these embodiments, an additional phase multiplexer may be used to perform quadrant switching of the phase, thereby reducing the number of phase buffer circuits. This further reduces the number of resistors used, thereby saving chip area.

[0034] In summary, the phase interpolator and phase buffer circuits in some embodiments of the present invention can use resistors to set the common-mode level of the node generating the output clock signal. This allows the linearity and available swing of the output clock signal to be maintained despite process variations.

[0035] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0036] Explanation of symbols

[0037] 100: Phase Interpolator

[0038] 110, 120, 130, 140: Phase interpolator circuit system

[0039] 110[0]~110

[15] 、120[0]~120

[15] : Phase buffer circuit

[0040] 130[0]~130

[15] 、140[0]~140

[15] : Phase buffer circuit

[0041] CK1~CK4: clock signal

[0042] CKO: output clock signal

[0043] GND: ground voltage

[0044] N1: output node

[0045] R1, R2: resistors

[0046] S1~S4: signal components

[0047] ST[0]~ST

[63] , STB[0]~STB

[63] : Phase control bits

[0048] T1~T4: switch

[0049] VDD: supply voltage

Claims

1. A phase interpolator comprising: a plurality of phase interpolator circuit systems for generating output clock signals from output nodes in response to a plurality of phase control bits and a plurality of clock signals; wherein the phases of the clock signals are different from each other, each of the phase interpolator circuit systems includes a plurality of phase buffer circuits, each of the phase buffer circuits being turned on according to a first bit and a second bit of the phase control bits to generate a signal component of the output clock signal to the output node according to a corresponding clock signal of the clock signals, each of the phase buffer circuits including a first resistor and a second resistor, and being configured to transmit one of a first voltage and a second voltage to the output node according to the corresponding clock signal, the first voltage being transmitted to the output node via the first resistor, and the second voltage being transmitted to the output node via the second resistor; The first resistor and the second resistor are used to set the common mode level of the output node.

2. The phase interpolator as claimed in claim 1, wherein the first voltage is higher than the second voltage. The phase interpolator as claimed in claim 1 , wherein the first bit is opposite to the second bit.

4. The phase interpolator of claim 1 , wherein each of the phase buffer circuits further comprises a plurality of switches coupled between the first resistor and the second resistor, and a portion of the switches directly connected to the output node does not receive the corresponding clock signal. 5 . The phase interpolator as claimed in claim 4 , wherein the portion of switches is configured to receive the first bit and the second bit.

6. The phase interpolator of claim 1 , wherein each of the phase buffer circuits further comprises a plurality of switches coupled between the first resistor and the second resistor, and a portion of the switches not directly connected to the output node is configured to be selectively turned on in response to the corresponding clock signal.

7. The phase interpolator of claim 1 , wherein each of the phase buffer circuits further comprises: A first switch, coupled to the first resistor and configured to selectively turn on in response to the corresponding clock signal; a second switch coupled to the first switch and configured to selectively turn on in response to the first bit to generate the signal component to the output node; a third switch coupled to the second switch and configured to selectively turn on in response to the second bit to generate the signal component to the output node; as well as The fourth switch is coupled between the second resistor and the third switch and is configured to be selectively turned on in response to the corresponding clock signal.

8. A phase buffer circuit comprising: a first resistor, wherein one end of the first resistor is used to receive a first voltage; a second resistor, wherein one end of the second resistor is used to receive a second voltage; a first switch, wherein a first terminal of the first switch is coupled to the other terminal of the first resistor, and a control terminal of the first switch is used to receive a clock signal; a second switch, wherein a first terminal of the second switch is coupled to the second terminal of the first switch, a second terminal of the second switch is coupled to the output node to generate a signal component, and a control terminal of the second switch is configured to receive a first phase control bit; a third switch, wherein a first terminal of the third switch is coupled to the output node, and a control terminal of the third switch is configured to receive a second phase control bit; as well as a fourth switch, wherein a first terminal of the fourth switch is coupled to the second terminal of the third switch, a second terminal of the fourth switch is coupled to the other terminal of the second resistor, and a control terminal of the fourth switch is configured to receive the clock signal; The first resistor and the second resistor are used to set the common mode level of the output node.

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