A Hardware-in-the-Loop Simulation Model Bus Signal Generation System and Method
By using the CAN board to automatically select and send messages in the ring simulation model bus signal generation system in the hardware, and divided into two mapping methods: non-mapping and full-mapping, the problem of manual operation and error-prone mode of message selection and sending in the existing technology is solved, and efficient and accurate bus signal generation is achieved.
Patent Information
- Application Number
- CN202310065732.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-12
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2043-01-12
AI Technical Summary
In the prior art, the message selection and sending methods have problems such as large manual operation volume and easy errors, especially when the number of messages and information volume of automobile buses is large, resulting in complex signal matching.
It provides a hardware-in-loop simulation model bus signal generation system, including a HIL test host computer, a HIL test emulator and a CAN board. By selecting messages sent by not being pre-selected network nodes on the CAN board, and sending selected messages through the platform, the automatic transmission of messages is realized. At the same time, the mapping of messages sent by the gantry is divided into two types: all-mapping and all-mapping, solving the problem of distinguishing signal mapping relationships.
Automatic transmission of packets is realized, avoiding the problem of manually selecting sending packets, greatly improving work efficiency and avoiding errors. By dividing into mapping methods that are not mapped and all mapped, the problem of increasing or decreasing signals after database update is solved, and the correct correspondence between model packets and bus packets is ensured.
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Figure CN116074206B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of simulation, and particularly to a hardware-in-the-loop simulation model bus signal generation system and method. Background Art
[0002] HIL (Hardware-in-the-Loop) testing is a very important link in the electrification control development process, and the construction of the model of the object under test in HIL testing is crucial. When building the model, the matching of bus signals directly affects the reception and transmission of signals. Incorrect message configuration or incorrect signal mapping relationship will affect the signal reception and transmission. Due to the large amount of automotive bus messages and the large amount of message information, the matching is complex. Therefore, how to efficiently and quickly select messages and the corresponding transmitted signals is very important for model construction.
[0003] Currently, for the selection and transmission of messages, the technical solutions adopted are as follows: First, select the messages sent by the test bench, and then manually check one by one the messages that the test bench needs to send; Second, select the messages received by the test bench and select all the messages received by the test bench; Third: perform signal mapping, manually screen the messages to be sent and the corresponding signals to be sent, and then manually input the mapping relationship between the two, that is, establish the mapping relationship between the bus signals and the relevant signals used in the model. For example, if the gear position of the transmission is required in the model, then the corresponding transmission gear position signal on the bus needs to be mapped to the model; Fourth, after generating the mapping relationship of the bus signals, connect the signals of the model to the bus signals to complete the transmission of the bus signals.
[0004] It can be seen that the existing message selection and transmission methods have the following problems: 1. The manual message selection method has a large workload and is prone to errors; 2. Manually screening the signal mapping relationship results in a large workload and is prone to omission; 3. The generated message transmission signals are relatively chaotic, which is not convenient for the correspondence between the signals in the model and the bus signals. Moreover, when the signal names in the model are inconsistent with the bus signals, the mapping relationship is not clear, increasing the workload and being prone to errors. Summary of the Invention
[0005] Aiming at the defects existing in the prior art, the purpose of the present invention is to provide a hardware-in-the-loop simulation model bus signal generation system and method, which can realize the automatic transmission of messages, avoid the problem of manually selecting and transmitting messages, greatly improve work efficiency and avoid errors; by dividing the mapping of the messages sent by the test bench into two types: all non-mapping and all mapping, it solves the problem that when the database is updated, it is impossible to distinguish whether the signals increase or decrease, and at the same time, solves the problem that when the messages in the model are inconsistent with the bus messages, it is impossible to correspond to the bus messages.
[0006] To achieve the above object, the present invention provides a hardware-in-the-loop simulation model bus signal generation system, which is located on a test bench, and the test bench is also used to connect to the controller under test in the HIL test. The hardware-in-the-loop simulation model bus signal generation system includes a HIL test host computer, a HIL test simulator, and a CAN board. The HIL test host computer is used to control the HIL test simulator to implement the HIL test, and the CAN board is installed on the HIL test simulator to implement the selection of message sending and receiving.
[0007] Based on the above solution,
[0008] The HIL test host computer and the HIL test simulator are connected through an Ethernet interface;
[0009] The CAN board is embedded on the HIL test simulator through a card slot;
[0010] The signal communication end of the controller under test is connected to the corresponding communication interface on the HIL test simulator.
[0011] Based on the above solution, the calibration protocol of the controller under test is the XCP calibration protocol or the CCP calibration protocol.
[0012] A hardware-in-the-loop simulation model bus signal generation method provided by the present invention is implemented based on the above-mentioned hardware-in-the-loop simulation model bus signal generation system, and specifically includes the following steps:
[0013] Select network nodes on the HIL test simulator to achieve the pre-selection of network nodes. The network nodes are the controllers under test;
[0014] Select the messages sent by the network nodes not pre-selected on the CAN board, and send the selected messages through the test bench;
[0015] Determine the selection of the messages received by the test bench on the CAN board;
[0016] Based on the default mapping relationship configured in the database, establish the mapping between the messages sent by the test bench and the messages of the controller under test to achieve the mapping of the messages sent by the test bench.
[0017] Based on the above solution, the step of selecting network nodes on the HIL test simulator to achieve the pre-selection of network nodes specifically includes:
[0018] Select the controller under test connected to the test bench on the HIL test simulator, and use the selected controller under test as the network node to achieve the pre-selection of network nodes.
[0019] Based on the above solution, select the messages sent by the network nodes not pre-selected on the CAN board, and send the selected messages through the test bench. The specific steps include:
[0020] Select the messages sent by the network nodes not pre-selected in the bus;
[0021] Send the selected messages through the test bench.
[0022] Based on the above solution, the messages received by the test bench are all the messages on the bus.
[0023] Based on the above solution, the mapping of the messages sent by the test bench includes all non-mapping and all mapping.
[0024] All non-mapping means that when mapping the messages sent by the test bench and the messages of the controller under test, no mapping is performed, and the generated mapping relation table does not contain mapping relations.
[0025] All mapping means that when mapping the messages sent by the test bench and the messages of the controller under test, customize the mapping relations, and automatically realize all mappings between the messages sent by the test bench and the messages of the controller under test through macro commands.
[0026] Compared with the prior art, the advantages of the present invention are as follows: By selecting the messages sent by the network nodes not pre-selected on the CAN board and sending the selected messages through the test bench, the automatic sending of messages is realized, avoiding the problem of manually selecting messages to be sent, greatly improving work efficiency and avoiding errors; By dividing the mapping of the messages sent by the test bench into two types: all non-mapping and all mapping, the problem of being unable to distinguish whether signals increase or decrease after the database is updated is solved. At the same time, the problem of being unable to correspond to the bus messages when the messages in the model are inconsistent with the bus messages is solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0028] Figure 1 It is a schematic structural diagram of a hardware-in-the-loop simulation model bus signal generation system in an embodiment of the present invention;
[0029] Figure 2 It is a flowchart of a hardware-in-the-loop simulation model bus signal generation method in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0030] An embodiment of the present invention provides a hardware-in-the-loop simulation model bus signal generation system. Correspondingly, an embodiment of the present invention also provides a method for generating a hardware-in-the-loop simulation model bus signal. By selecting the messages sent by the network nodes that are not pre-selected on the CAN board and sending the selected messages through the test bench, the automatic sending of messages is realized, avoiding the problem of manually selecting and sending messages, greatly improving the work efficiency and avoiding errors; by dividing the mapping of the messages sent by the test bench into two types: all unmapped and all mapped, the problem of being unable to distinguish whether the signals increase or decrease after the database is updated is solved. At the same time, the problem of being unable to correspond to the bus messages when the messages in the model are inconsistent with the bus messages is solved.
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. It should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. Unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. In the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.
[0032] See Figure 1As shown in the figure, a hardware-in-the-loop simulation model bus signal generation system provided by an embodiment of the present invention is arranged on a test bench, and the test bench is also used to be connected to the controller under test in the HIL test. The hardware-in-the-loop simulation model bus signal generation system specifically includes a HIL test host computer, a HIL test simulator, and a CAN (Controller Area Network) board. The HIL test host computer is used to control the HIL test simulator to implement the HIL test. The CAN board is installed on the HIL test simulator to implement the selection of message sending and receiving. The CAN board is a core hardware for generating hardware-in-the-loop simulation model bus signals.
[0033] Specifically, the HIL test host computer is connected to the HIL test simulator through an Ethernet interface; the CAN board is embedded in the HIL test simulator through a card slot and is connected through CAN_H and CAN_L; the signal communication end of the controller under test is connected to the corresponding communication interface on the HIL test simulator.
[0034] Specifically, the calibration protocol of the controller under test is the XCP calibration protocol or the CCP calibration protocol.
[0035] See Figure 2 As shown in the figure, an embodiment of the present invention also provides a hardware-in-the-loop simulation model bus signal generation method, which is implemented based on the above-mentioned hardware-in-the-loop simulation model bus signal generation system. By pre-selecting network nodes and automatically selecting all messages sent by the test bench, the message mapping is also fully automatic, and the messages can be assigned on the HIL test host computer, avoiding repetitive manual operations, and can avoid errors, improving efficiency while ensuring the correct rate. The hardware-in-the-loop simulation model bus signal generation method of the present invention specifically includes the following steps:
[0036] S1: Select network nodes on the HIL test simulator to implement pre-selection of network nodes. The network nodes are the controllers under test.
[0037] In the present invention, to select network nodes on the HIL test simulator to implement pre-selection of network nodes, the specific steps include: Select the controller under test connected to the test bench on the HIL test simulator, and use the selected controller under test as the network node to implement pre-selection of network nodes.
[0038] Step S1 is the pre-selection of network nodes. The pre-selection of network nodes means pre-selecting network nodes, and generally, the physical controller under test connected to the HIL test system (i.e., the test bench) is selected as the network node.
[0039] S2: Select the messages sent by the network nodes not pre-selected on the CAN board and send the selected messages through the test bench.
[0040] In the present invention, a message sent by a network node that is not pre-selected is selected on the CAN board, and the selected message is sent through the rack. The specific steps include:
[0041] S201: Selecting a message sent by a network node that is not pre-selected in the bus;
[0042] S202: Sending the selected message through the rack.
[0043] Step S2 is the selection of the message sent by the rack. The selection criteria for the rack to send the message is to select the message sent by the network node that is not pre-selected. The message sent by the network node that is not pre-selected on the bus is sent by the rack. This sending method can avoid the omission of the message, because the pre-selected network node is the physical controller under test connected to the rack, which will send the message by itself, so the other messages are sent by the rack. The messages received by the rack are all the messages on the bus.
[0044] S3: Select and determine the message received by the test bench on the CAN board;
[0045] S4: Based on the default mapping relationship configured in the database, a mapping between the test bench sent message and the measured controller message is established to achieve the mapping of the test bench sent message.
[0046] In the present invention, the mapping of the message sent by the test bench includes no mapping and full mapping. No mapping means that when mapping between the message sent by the test bench and the message of the controller under test, no mapping is performed, and the generated mapping relationship table does not contain a mapping relationship. Full mapping means that when mapping between the message sent by the test bench and the message of the controller under test, a mapping relationship is customized, and all mappings between the message sent by the test bench and the message of the controller under test are automatically realized through macro commands.
[0047] That is, the mapping of the message sent by the rack can be divided into two steps: step one is not mapping at all; step two is mapping all. For the mapping of the message sent by the rack, it can be configured according to the default mapping relationship in the database.
[0048] In the present invention, the mapping of the message sent by the test bench includes two parts: no mapping and full mapping. Both parts require setting the signal source to a constant instead of grounding. The purpose of setting the signal source to a constant is to facilitate the test engineer to assign values during testing. After setting it to ground, the test engineer cannot assign values during testing, which makes testing inconvenient.
[0049] For the first part: no mapping is performed. At this time, the generated signal source is a constant, and there is a link channel between the constant and the signal source. For the second part: full mapping is performed, generating a signal mapping channel with an input source. When generating the second part, the module name generated in the first part needs to be modified. The purpose of this is to avoid overwriting the generation of the first time during the second generation. The input is a message, and the output is the specific mapped message; the signal source has the same meaning as the above-mentioned ground and constant; the input source refers to the source of the message; the linked channel refers to the link relationship between the signal value and the signal; the signal mapping channel refers to the corresponding channel between the bus message and the model message; the module name modification refers to the name of the bus real-time interface module.
[0050] By using macro operations for message mapping, it is convenient, efficient, and not error-prone, and the mapping relationship will map all the messages sent by all the test benches as required.
[0051] After performing the mapping of the message, the mapping relationship of all the messages sent by all the test benches on one bus will be obtained. Finally, by linking the variables related to the model and the bus message, the link between the model (such as a vehicle dynamics model, etc.) and the corresponding interface model can be completed.
[0052] The method for generating bus signals of the hardware-in-the-loop simulation model according to the embodiment of the present invention selects the messages sent by the network nodes not pre-selected on the CAN board and sends the selected messages through the test bench, realizing the automatic sending of messages, avoiding the problem of manually selecting and sending messages, greatly improving work efficiency and avoiding errors; by dividing the mapping of the messages sent by the test bench into two types: all non-mapping and all mapping, it solves the problem that when the database is updated, it is impossible to distinguish whether the signals increase or decrease, and at the same time, solves the problem that when the messages in the model are inconsistent with the bus messages, it is impossible to correspond to the bus messages.
[0053] In a possible implementation manner, the present invention further provides a readable storage medium, which is located in a PLC (Programmable Logic Controller) controller. A computer program is stored on the readable storage medium. When the program is executed by a processor, the steps of the above-mentioned method for generating bus signals of the hardware-in-the-loop simulation model are implemented:
[0054] Select network nodes on the HIL test simulator to achieve pre-selection of the network nodes, and the network nodes are the controllers to be tested;
[0055] Select the messages sent by the network nodes not pre-selected on the CAN board and send the selected messages through the test bench;
[0056] Determine the selection of the messages received by the test bench on the CAN board;
[0057] Based on the default mapping relationship configured in the database, establish the mapping between the bench - sent messages and the messages of the controller under test, and realize the mapping of the bench - sent messages.
[0058] In the present invention, select network nodes on the HIL test simulator to achieve the pre - selection of network nodes. The specific steps include:
[0059] Select the controller under test connected to the bench on the HIL test simulator, and use the selected controller under test as a network node to achieve the pre - selection of network nodes.
[0060] The pre - selection of network nodes means pre - selecting network nodes. Generally, the physical controller under test connected to the HIL test system (i.e., the bench) is selected as the network node.
[0061] In the present invention, select the messages sent by the network nodes not pre - selected on the CAN board, and send the selected messages through the bench. The specific steps include:
[0062] Select the messages sent by the network nodes not pre - selected in the bus;
[0063] Send the messages selected through the bench.
[0064] The selection criterion for the bench - sent messages is to select the messages sent by the network nodes not pre - selected. The messages sent by the network nodes not pre - selected on the bus are sent by the bench. Using this sending method can avoid the omission of message sending. Because the pre - selected network nodes are the physical controllers under test connected to the bench, they will send messages by themselves. Therefore, other messages are sent by the bench. The messages received by the bench are all the messages on the bus.
[0065] In the present invention, the messages received by the bench are all the messages on the bus.
[0066] In the present invention, the mapping of the bench - sent messages includes all - non - mapping and all - mapping.
[0067] In the present invention, all - non - mapping means that when mapping between the bench - sent messages and the messages of the controller under test, no mapping is performed, and the generated mapping relation table does not contain mapping relations.
[0068] In the present invention, all - mapping means that when mapping between the bench - sent messages and the messages of the controller under test, customize the mapping relationship, and automatically realize all the mappings between the bench - sent messages and the messages of the controller under test through macro commands.
[0069] That is, the mapping of the bench - sent messages can be divided into two steps: Step one is all - non - mapping; Step two is all - mapping. For the mapping of the bench - sent messages, configure according to the default mapping relationship in the database.
[0070] In the present invention, the mapping of the bench sending messages includes two parts: all unmapped and all mapped. For both parts, the signal source needs to be set to a constant instead of being grounded. The purpose of setting the signal source to a constant is to facilitate the testing engineer to assign values during testing. If it is set to ground, the testing engineer cannot assign values during testing, which is inconvenient for testing.
[0071] For the first part: all unmapped, at this time the generated signal source is a constant, and there is a link channel between the constant and the signal source. For the second part: all mapped, a signal mapping channel with an input source is generated. When generating the second part, the module name generated in the first part needs to be modified. The purpose of doing this is to avoid overwriting the generation of the first time during the second generation. The input is a message, and the output is the specific message after mapping; the signal source has the same meaning as the above-mentioned grounding and constant; the input source refers to the source of the message; the linked channel refers to the link relationship between the signal value and the signal; the signal mapping channel refers to the corresponding channel between the bus message and the model message; the modification of the module name refers to the name of the bus real-time interface module.
[0072] By selecting the messages sent by the network nodes that are not pre-selected on the CAN board and sending the selected messages through the bench, the automatic sending of messages is realized, avoiding the problem of manually selecting and sending messages, greatly improving the work efficiency and avoiding errors; by dividing the mapping of the bench sending messages into two types: all unmapped and all mapped, the problem of being unable to distinguish whether the signals increase or decrease when the database is updated is solved. At the same time, the problem of being unable to correspond to the bus message when the message in the model is inconsistent with the bus message is solved.
[0073] The storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device.
[0074] A computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program code is carried. Such a propagated data signal may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
[0075] The computer program code for performing the operations of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages - such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected through the Internet using an Internet service provider).
[0076] Correspondingly, the present invention also provides a hardware-in-the-loop simulation model bus signal generation device, including a first selection module, a second selection module, a determination module, and a mapping module. The first selection module is used to select a network node on the HIL test emulator to implement pre-selection of the network node, and the network node is the controller under test; the second selection module is used to select the message sent by the network node not pre-selected on the CAN board and send the selected message through the test bench; the determination module is used to determine the selection of the message received by the test bench on the CAN board; the mapping module is used to establish a mapping between the message sent by the test bench and the message of the controller under test based on the default mapping relationship configured in the database to implement the mapping of the message sent by the test bench.
[0077] In the present invention, the process of selecting a network node on the HIL test emulator to implement pre-selection of the network node specifically includes:
[0078] Select the controller under test connected to the test bench on the HIL test emulator and use the selected controller under test as the network node to implement pre-selection of the network node.
[0079] Network node pre-selection means pre-selecting network nodes. Generally, the physical controller under test connected to the HIL test system (i.e., the test bench) is selected as the network node.
[0080] In the present invention, messages sent by network nodes that are not pre-selected are selected on the CAN board, and the selected messages are sent through the test bench. The specific process includes:
[0081] Select messages sent by network nodes that are not pre-selected in the bus;
[0082] Send the selected messages through the test bench.
[0083] The selection criterion for the test bench to send messages is to select messages sent by network nodes that are not pre-selected. Messages sent by network nodes that are not pre-selected on the bus are sent by the test bench. Using this sending method can avoid missed sending of messages because the pre-selected network nodes are physical controllers under test connected to the test bench, and they will send messages by themselves. Therefore, other messages are sent by the test bench. The messages received by the test bench are all the messages on the bus.
[0084] In the present invention, the messages received by the test bench are all the messages on the bus.
[0085] In the present invention, the mapping of the test bench to send messages includes all non-mapping and all mapping.
[0086] In the present invention, all non-mapping means that when mapping between the messages sent by the test bench and the messages of the controller under test, no mapping is performed, and the generated mapping relation table does not contain mapping relations.
[0087] In the present invention, all mapping means that when mapping between the messages sent by the test bench and the messages of the controller under test, custom mapping relations are defined, and all mappings between the messages sent by the test bench and the messages of the controller under test are automatically realized through macro commands.
[0088] The hardware-in-the-loop simulation model bus signal generation device according to the embodiment of the present invention realizes automatic sending of messages by selecting messages sent by network nodes that are not pre-selected on the CAN board and sending the selected messages through the test bench, avoiding the problem of manually selecting messages to send, greatly improving work efficiency and avoiding errors; by dividing the mapping of the test bench to send messages into two types: all non-mapping and all mapping, the problem of being unable to distinguish whether signals increase or decrease when the database is updated is solved. At the same time, the problem of being unable to correspond to the bus messages when the messages in the model are inconsistent with the bus messages is solved.
[0089] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. Unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0090] It should be noted that in the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
[0091] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.
Claims
1. A hardware-in-the-loop simulation model bus signal generation system is located on a test bench, and the test bench is also used to connect to the controller under test in a HIL test. It is characterized in that: It includes a HIL test host computer, a HIL test emulator, and a CAN board. The HIL test host computer is used to control the HIL test emulator to implement HIL testing. The CAN board is installed on the HIL test emulator to achieve the selection of message sending and receiving; Among them, select the messages sent by the network nodes that are not pre-selected on the CAN board, and send the selected messages through the test bench. The pre-selected network nodes are the controllers under test; Among them, the mapping of the messages sent by the test bench includes two parts: all non-mapping and all mapping, and the signal source needs to be set to a constant for both parts; Among them, "all non-mapping" means that when mapping the messages sent by the test bench and the messages of the controller under test, no mapping is performed, and the generated mapping relation table does not contain mapping relations; "all mapping" means that when mapping the messages sent by the test bench and the messages of the controller under test, customize the mapping relations, and automatically implement all mappings between the messages sent by the test bench and the messages of the controller under test through macro commands.
2. A hardware-in-the-loop simulation model bus signal generation system according to claim 1, characterized in that: The HIL test host computer is connected to the HIL test emulator through an Ethernet interface; The CAN board is embedded on the HIL test emulator through a card slot; The signal communication end of the controller under test is connected to the corresponding communication interface on the HIL test emulator.
3. A hardware-in-the-loop simulation model bus signal generation system according to claim 1, characterized in that: The calibration protocol of the controller under test is the XCP calibration protocol or the CCP calibration protocol.
4. A method for generating bus signals of a hardware-in-the-loop simulation model, implemented based on the hardware-in-the-loop simulation model bus signal generation system according to any one of claims 1 to 3, characterized in that, Specifically, it includes the following steps: Select network nodes on the HIL test emulator to achieve pre-selection of network nodes. The network nodes are the controllers under test; Select the messages sent by the network nodes that are not pre-selected on the CAN board, and send the selected messages through the test bench; Determine the selection of the messages received by the test bench on the CAN board; Based on the default mapping relations configured in the database, establish the mapping between the messages sent by the test bench and the messages of the controller under test to achieve the mapping of the messages sent by the test bench.
5. A method for generating bus signals of a hardware-in-the-loop simulation model according to claim 4, characterized in that, The step of selecting network nodes on the HIL test emulator to achieve pre-selection of network nodes specifically includes: Select the controller under test connected to the test bench on the HIL test emulator, and use the selected controller under test as a network node to achieve pre-selection of network nodes.
6. A method for generating bus signals of a hardware-in-the-loop simulation model according to claim 5, characterized in that, The step of selecting the messages sent by the network nodes that are not pre-selected on the CAN board and sending the selected messages through the test bench specifically includes: Select the messages sent by the network nodes that are not pre-selected in the bus; Send the selected messages through the test bench.
7. A method for generating bus signals of a hardware-in-the-loop simulation model according to claim 4, characterized in that: The messages received by the test bench are all the messages on the bus.
8. A method for generating bus signals of a hardware-in-the-loop simulation model according to claim 4, characterized in that: The mapping of the messages sent by the test bench includes all non-mapping and all mapping.
Citation Information
Patent Citations
Multi-controller joint HIL rack message frame loss fault injection test system and method
CN110928275A