A high PSRR reference circuit for power management chips

Abstract

The present invention seeks to protect a high PSRR reference circuit for a power management chip, including a self-bias pre-adjustment circuit and a reference core circuit. The present invention uses a self-bias pre-adjustment circuit to provide a working power supply for the reference core circuit, thereby improving the power supply rejection ratio of the circuit; uses NPN transistors Q12 and Q13 as input pairs of error amplifiers and connects their emitters to resistors R6, thereby effectively increasing the common-mode input range of the error amplifier and reducing the complexity of the circuit; connects capacitor C1 to the output of the error amplifier to improve the circuit loop stability; and uses a current provided by a PMOS tube M3 working in a subthreshold region to generate a voltage on resistor R2 to compensate for the base-emitter voltage V of the NPN transistor Q9. BE9 The temperature high-order nonlinearity is reduced to obtain a reference voltage with high PSRR and low temperature drift coefficient, thereby realizing a high PSRR reference circuit.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a high PSRR benchmark reference circuit for a power management chip. Background Art

[0002] Portable electronic devices are small in size, powerful in function and highly integrated, which is one of the important trends in the development of electronic devices. They require high-performance power management chips. The reference circuit is one of the core circuits of the power management chip. It provides high-performance bias voltage for the functional modules of the power management chip. Therefore, the reference circuit directly affects the performance characteristics of the power management chip, and thus affects the performance characteristics of portable electronic devices.

[0003] Figure 1 This is a traditional reference circuit schematic diagram, which is mainly composed of amplifier A1, PMOS tube M1, PMOS tube M2, NPN transistor Q1, NPN transistor Q2, NPN transistor Q3, resistor R1 and resistor R2. PMOS tubes M1~M3 have the same channel width-to-length ratio. The emitter area of ​​NPN transistor Q1 is n times the emitter area of ​​NPN transistor Q2. All resistors are made of the same material, so the output voltage of the output terminal VBG of the bandgap reference circuit is Where R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, V T is the thermal voltage, V BE3 is the base-emitter voltage of the NPN transistor Q3. By optimizing the resistance values ​​of resistors R1 and R2 and parameter n, a reference voltage V with zero temperature drift characteristics can be obtained within a certain temperature range. REF . Since V BE3 The traditional reference circuit has a high temperature drift coefficient problem due to temperature nonlinearity. At the same time, the power management chip is a mixed digital-analog circuit. The reference circuit is integrated on the same chip with the digital circuit and the corresponding switch circuit, which are prone to power supply fluctuations. Therefore, the output voltage of the reference circuit is easily affected by power supply noise. Therefore, the application of traditional reference circuits in high-precision power management chip systems is greatly limited. Summary of the invention

[0004] The present invention aims to solve the above problems of the prior art. A high PSRR reference circuit for a power management chip is proposed. The technical solution of the present invention is as follows:

[0005] A high PSRR reference circuit for a power management chip, comprising a self-bias pre-adjustment circuit and a reference core circuit, wherein the signal output terminal of the self-bias pre-adjustment circuit is connected to the signal input terminal of the reference core circuit, the self-bias pre-adjustment circuit provides working power for the reference core circuit through a depletion-type NMOS tube M2, and the reference core circuit uses a current provided by a PMOS tube M3 working in a subthreshold region to generate a voltage compensation NPN transistor Q9 base-emitter voltage V on a resistor R2. BE9 The high-order nonlinearity over temperature is reduced, thereby generating a reference voltage with a high power supply rejection ratio (PSRR) at the output VREF.

[0006] Furthermore, the self-bias pre-adjustment circuit includes: a depletion-type NMOS tube M1, a depletion-type NMOS tube M2, a resistor R1, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, an NPN transistor Q4, an NPN transistor Q5, an NPN transistor Q6 and an NPN transistor Q7, wherein the drain of the depletion-type NMOS tube M1 is connected to the drain of the depletion-type NMOS tube M2 and the external power supply VDD, respectively, and the depletion-type NMOS The source of the depletion-type NMOS tube M1 is connected to one end of the resistor R1, the gate of the depletion-type NMOS tube M1 is respectively connected to the gate of the depletion-type NMOS tube M2, the other end of the resistor R1 and the collector of the NPN transistor Q1, the source of the depletion-type NMOS tube M2 is respectively connected to the source of the PMOS tube M11, the collector of the NPN transistor Q8, the source of the PMOS tube M4, the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube Ms1, the collector of the NPN transistor Q8, the collector of the NPN transistor Q9, the collector of the PMOS tube M10, the collector of the PMOS tube M11, the collector of the NPN transistor Q12, the collector of the PMOS tube M13, the collector of the PMOS tube M14, the collector of the PMOS tube M15, the collector of the PMOS tube M16, the collector of the PMOS tube M17, the collector of the PMOS tube M18, the collector of the PMOS tube M19, the collector of the PMOS tube M20, the collector of the PMOS tube M21, the collector of the PMOS tube M22, the collector of the PMOS tube M23, the collector of the PMOS tube M24, the collector of the PMOS tube M25, the collector of the PMOS tube M26, the collector of the PMOS tube M27, the collector of the PMOS tube M28, the collector of the PMOS tube M29, the collector of the PMOS tube M30, the collector of the PMOS tube M31, the collector of the PMOS tube M32, the collector of the PMOS tube M33, the collector of the PMOS tube M34, the collector of the PMOS tube M35, the collector of the PMOS tube M36, the collector of the PMOS tube The source of the MOS transistor Ms2, the source of the PMOS transistor Ms6, the collector of the NPN transistor Q7 and the base of the NPN transistor Q7 are connected, the emitter of the NPN transistor Q7 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q6, the emitter of the NPN transistor Q6 is connected to the collector of the NPN transistor Q5 and the base of the NPN transistor Q5, the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5, and the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5. The collector of Q4 is connected to the base of NPN transistor Q4, the emitter of NPN transistor Q4 is respectively connected to the collector of NPN transistor Q3 and the base of NPN transistor Q3, the emitter of NPN transistor Q3 is respectively connected to the collector of NPN transistor Q2, the base of NPN transistor Q2 and the base of NPN transistor Q1, and the emitter of NPN transistor Q2 is respectively connected to the emitter of NPN transistor Q1 and the external ground wire GND.

[0007] Further, the benchmark reference core circuit includes: PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube Ms1, PMOS tube Ms2, NMOS tube Ms3, NMOS tube Ms4, PMOS tube Ms5, PMOS tube Ms6, capacitor C1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, NPN transistor Q8, NPN transistor Q9, NPN transistor Q10, NPN transistor Q11, NPN transistor Q12, NPN transistor Q13 and NPN transistor Q14 , wherein the gate of the PMOS tube M11 is respectively connected to the drain of the PMOS tube M4, the gate of the PMOS tube M4, the gate of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube Ms1 and the collector of the NPN transistor Q11, the drain of the PMOS tube M11 is respectively connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14, the drain of the PMOS tube M3 and the gate of the PMOS tube M3, the base of the NPN transistor Q8 is respectively connected to the drain of the PMOS tube Ms2, one end of the capacitor C1, the drain of the PMOS tube M8 and the drain of the NMOS tube M10, the emitter of the NPN transistor Q8 is respectively connected to one end of the resistor R2 and the circuit output The first terminal VREF is connected to the first terminal VREF, the other end of the resistor R2 is respectively connected to the source of the PMOS tube M3, one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is respectively connected to the collector of the NPN transistor Q9, the base of the NPN transistor Q9, the base of the NPN transistor Q10, the base of the NPN transistor Q11 and the base of the NPN transistor Q12, the other end of the resistor R4 is respectively connected to the base of the NPN transistor Q13 and the collector of the NPN transistor Q10, the emitter of the NPN transistor Q10 is connected to one end of the resistor R5, the emitter of the NPN transistor Q12 is respectively connected to the emitter of the NPN transistor Q13 and one end of the resistor R6, and the other end of the resistor R6 is respectively connected to the collector of the NPN transistor Q13 and the collector of the NPN transistor Q10. The PMOS transistor M5 is connected to the emitter of the NPN transistor Q14, the emitter of the NPN transistor Q9, the other end of the resistor R5, the emitter of the NPN transistor Q11, the source of the NMOS transistor M9, the source of the NMOS transistor M10, the other end of the capacitor C1, the source of the NMOS transistor Ms3, the source of the NMOS transistor Ms4 and the external ground line GND; the drain of the PMOS transistor M5 is respectively connected to the collector of the NPN transistor Q12 and the source of the PMOS transistor M7; the gate of the PMOS transistor M7 is respectively connected to the gate of the PMOS transistor M8 and the voltage bias terminal VB; the drain of the PMOS transistor M7 is respectively connected to the drain of the NMOS transistor M9, the gate of the NMOS transistor M9 and the gate of the NMOS transistor M10;The drain of the PMOS tube M6 is respectively connected to the collector of the NPN transistor Q13 and the source of the PMOS tube M8, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms1 and the drain of the NMOS tube Ms3, the gate of the PMOS tube Ms6 is respectively connected to the drain of the PMOS tube Ms6 and the source of the PMOS tube Ms5, the gate of the PMOS tube Ms5 is respectively connected to the drain of the PMOS tube Ms5, the drain of the NMOS tube Ms4, the gate of the NMOS tube Ms4 and the gate of the NMOS tube Ms3.

[0008] Furthermore, in the self-bias pre-adjustment circuit, both the NMOS tube M1 and the NMOS tube M2 are depletion-type NMOS tubes, and the resistor R1 is a current-limiting resistor to prevent the circuit from consuming a large current; when the circuit is started, the depletion-type NMOS tube M1 and the depletion-type NMOS tube M2 are in a conducting state, charging the NPN transistor Q7 branch, and the base-emitter voltage of the NPN transistor Q2 rises, causing the base-emitter voltage of the NPN transistor Q1 to rise, thereby causing the self-bias pre-adjustment circuit to work normally; at the same time, the NPN transistors Q1, Q2, and Q3 , NPN transistor Q4, NPN transistor Q5, NPN transistor Q6, NPN transistor Q7, depletion type NMOS tube M1, depletion type NMOS tube M2 and resistor R1 form a negative feedback loop. When the external power supply VDD has a positive fluctuation voltage increase, the source of the depletion type NMOS tube M2 has a positive fluctuation voltage, and the base-emitter voltage of the transistor connected by the diode rises, the collector current of the transistor increases, the collector is discharged, the collector voltage is reduced, and then the source voltage of the depletion type NMOS tube M2 is suppressed to increase, thereby improving the power supply rejection ratio (PSRR) of the circuit.

[0009] Furthermore, in the reference core circuit, all resistors are made of the same material, all MOS tubes are enhanced MOS tubes, NPN transistor Q12, NPN transistor Q13, resistor R6, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9 and NMOS tube M10 constitute an error amplifier, wherein NPN transistor Q12 and NPN transistor Q13 are used as differential input pairs to increase the common mode input range of the error amplifier, resistor R6 is used to connect the emitter of the differential input pair to reduce the complexity of the circuit, and capacitor C1 is connected to the output end of the error amplifier to improve the circuit loop stability. The gain of the error amplifier is much greater than 1, forcing the in-phase input end and the inverting input end of the error amplifier to have the same voltage, the emitter area of ​​the NPN transistor Q10 is α times that of the NPN transistor Q9, the resistor R3 is exactly the same as the resistor R4, and the current flowing through the resistor R3 is the same as the current of the resistor R4. The NPN transistor Q9 is exactly the same as the NPN transistor Q11. The emitter area of ​​the NPN transistor Q14 is β times that of the NPN transistor Q9. The PMOS transistor M4 is exactly the same as the PMOS transistor M11. The drain current I3 of the PMOS transistor M3 is negligibly small relative to the collector current of the NPN transistor Q14. The NPN transistors Q9, Q10, Q11 and Q14 have the same collector current. The PMOS transistor M3 works in the subthreshold region and its drain current I3 = Among them, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, η is the subthreshold slope factor, (W / L)3 is the channel width-to-length ratio of the PMOS tube M3, V THp is the threshold voltage of the PMOS tube, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, V T is the thermovoltage and is equal to kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. Hole mobility μ p With temperature T has μ p =μ p0 (T / T0) -n , PMOS threshold voltage V THp With temperature T |V THp |=|V TH0 |-b(T-T0), where T0 is the reference temperature, μ p0 is the air attack mobility at the reference temperature T0, n is the process-related temperature coefficient, V TH0 is the threshold voltage at the reference temperature T0, and b is the temperature coefficient of the threshold voltage. Therefore, the drain current I3 of the PMOS tube M3 has a high-order temperature nonlinearity.

[0010] Furthermore, the voltage V at the output terminal VREF of the high PSRR reference circuit is REF =V BE9 +(R3+2R2)(lnα)V T / R5+I3R2, where V BE9 is the base-emitter voltage of NPN transistor Q9, and R2 is the resistance value of resistor R2. Factor (R3+2R2)(lnα)V T / R5 can effectively compensate V BE9 The temperature first-order characteristic, factor I3R2 can effectively compensate for V BE9 The high-order nonlinearity of temperature is reduced to obtain a high-performance reference voltage.

[0011] The advantages and beneficial effects of the present invention are as follows:

[0012] The present invention provides a high PSRR reference circuit for a power management chip, adopts a self-bias pre-adjustment technology that forms a negative feedback loop with depletion-type NMOS tubes M1-M2 and NPN transistors Q1-Q7, and provides a working power supply for a reference core circuit, thereby improving the power supply rejection ratio PSRR of the circuit, adopts NPN transistors Q12 and NPN transistors Q13 as input pairs of error amplifiers, increases the common-mode input range of the error amplifier, adopts a resistor R6 to connect the emitters of the differential input pairs of tubes, reduces the complexity of the circuit, connects a capacitor C1 to the output end of the error amplifier, and improves the stability of the circuit loop; adopts a current provided by a PMOS tube M3 working in a subthreshold region The voltage generated on the resistor R2 compensates the base-emitter voltage V of the NPN transistor Q9 BE9 The temperature high-order nonlinearity is reduced to obtain a high PSRR reference voltage, thereby realizing a high PSRR reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a traditional benchmark reference circuit schematic;

[0014] Figure 2 A high PSRR reference circuit schematic diagram for a power management chip is provided for a preferred embodiment of the present invention;

[0015] Figure 3 A temperature characteristic simulation curve diagram of a high PSRR reference circuit for a power management chip is provided for a preferred embodiment of the present invention.

[0016] Figure 4 A power supply rejection ratio (PSRR) simulation curve diagram of a high PSRR benchmark reference circuit for a power management chip according to a preferred embodiment of the present invention is provided. DETAILED DESCRIPTION

[0017] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0018] The technical solution of the present invention to solve the above technical problems is:

[0019] The embodiment of the present application adopts a self-bias pre-adjustment technology that forms a negative feedback loop with depletion-type NMOS tubes M1-M2 and NPN transistors Q1-Q7, and provides a working power supply for the reference core circuit, thereby improving the power supply rejection ratio PSRR of the circuit, adopting NPN transistors Q12 and NPN transistors Q13 as input pairs of transistors of the error amplifier, increasing the common-mode input range of the error amplifier, adopting resistor R6 to connect the emitter of the differential input pair of transistors, reducing the complexity of the circuit, and connecting capacitor C1 to the output terminal of the error amplifier to improve the stability of the circuit loop; adopting the voltage generated on the resistor R2 by the current provided by the PMOS tube M3 working in the subthreshold region to compensate the base-emitter voltage V of the NPN transistor Q9 BE9 The temperature high-order nonlinearity is reduced to obtain a high PSRR reference voltage, thereby realizing a high PSRR reference circuit.

[0020] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0021] Example

[0022] A high PSRR reference circuit for power management chips, such as Figure 2 As shown, it includes a self-bias pre-adjustment circuit 1 and a reference core circuit 2;

[0023] Among them, the signal output end of the self-bias pre-adjustment circuit 1 is connected to the signal input end of the reference core circuit 2, the self-bias pre-adjustment circuit 1 provides a working power supply for the reference core circuit 2, and the reference core circuit 2 generates a reference voltage with a high power supply rejection ratio (PSRR) at the output end VREF.

[0024] As a preferred technical solution, Figure 2As shown, the self-bias pre-adjustment circuit 1 includes: a depletion-type NMOS tube M1, a depletion-type NMOS tube M2, a resistor R1, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, an NPN transistor Q4, an NPN transistor Q5, an NPN transistor Q6 and an NPN transistor Q7, wherein the drain of the depletion-type NMOS tube M1 is connected to the drain of the depletion-type NMOS tube M2 and the external power supply VDD respectively, and the depletion-type NMOS tube The source of M1 is connected to one end of the resistor R1, the gate of the depletion-type NMOS tube M1 is respectively connected to the gate of the depletion-type NMOS tube M2, the other end of the resistor R1 and the collector of the NPN transistor Q1, the source of the depletion-type NMOS tube M2 is respectively connected to the source of the PMOS tube M11, the collector of the NPN transistor Q8, the source of the PMOS tube M4, the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube Ms1, the collector of the NPN transistor Q8, the collector of the NPN transistor Q9, the collector of the PMOS tube M10, the collector of the PMOS tube M11, the collector of the PMOS tube M12, the collector of the PMOS tube M13, the collector of the PMOS tube M14, the collector of the PMOS tube M15, the collector of the PMOS tube M16, the collector of the PMOS tube M17, The source of the MOS transistor Ms2, the source of the PMOS transistor Ms6, the collector of the NPN transistor Q7 and the base of the NPN transistor Q7 are connected, the emitter of the NPN transistor Q7 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q6, the emitter of the NPN transistor Q6 is connected to the collector of the NPN transistor Q5 and the base of the NPN transistor Q5, the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5, and the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5. The collector of Q4 is connected to the base of NPN transistor Q4, the emitter of NPN transistor Q4 is respectively connected to the collector of NPN transistor Q3 and the base of NPN transistor Q3, the emitter of NPN transistor Q3 is respectively connected to the collector of NPN transistor Q2, the base of NPN transistor Q2 and the base of NPN transistor Q1, and the emitter of NPN transistor Q2 is respectively connected to the emitter of NPN transistor Q1 and the external ground wire GND.

[0025] The reference core circuit 2 includes: PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube Ms1, PMOS tube Ms2, NMOS tube Ms3, NMOS tube Ms4, PMOS tube Ms5, PMOS tube Ms6, capacitor C1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, NPN transistor Q8, NPN transistor Q9, NPN transistor Q10, NPN transistor Q11, NPN transistor Q12, NPN transistor Q13 and NPN transistor Q14, wherein The gate of the PMOS tube M11 is respectively connected to the drain of the PMOS tube M4, the gate of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube Ms1 and the collector of the NPN transistor Q11; the drain of the PMOS tube M11 is respectively connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14, the drain of the PMOS tube M3 and the gate of the PMOS tube M3; the base of the NPN transistor Q8 is respectively connected to the drain of the PMOS tube Ms2, one end of the capacitor C1, the drain of the PMOS tube M8 and the drain of the NMOS tube M10; the emitter of the NPN transistor Q8 is respectively connected to one end of the resistor R2 and the circuit output terminal V REF is connected, the other end of the resistor R2 is respectively connected to the source of the PMOS tube M3, one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is respectively connected to the collector of the NPN transistor Q9, the base of the NPN transistor Q9, the base of the NPN transistor Q10, the base of the NPN transistor Q11 and the base of the NPN transistor Q12, the other end of the resistor R4 is respectively connected to the base of the NPN transistor Q13 and the collector of the NPN transistor Q10, the emitter of the NPN transistor Q10 is connected to one end of the resistor R5, the emitter of the NPN transistor Q12 is respectively connected to the emitter of the NPN transistor Q13 and one end of the resistor R6, and the other end of the resistor R6 is respectively connected to The emitter of NPN transistor Q14, the emitter of NPN transistor Q9, the other end of resistor R5, the emitter of NPN transistor Q11, the source of NMOS tube M9, the source of NMOS tube M10, the other end of capacitor C1, the source of NMOS tube Ms3, the source of NMOS tube Ms4 and the external ground line GND are connected, the drain of PMOS tube M5 is respectively connected to the collector of NPN transistor Q12 and the source of PMOS tube M7, the gate of PMOS tube M7 is respectively connected to the gate of PMOS tube M8 and voltage bias terminal VB, the drain of PMOS tube M7 is respectively connected to the drain of NMOS tube M9, the gate of NMOS tube M9 and the gate of NMOS tube M10,The drain of the PMOS tube M6 is respectively connected to the collector of the NPN transistor Q13 and the source of the PMOS tube M8, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms1 and the drain of the NMOS tube Ms3, the gate of the PMOS tube Ms6 is respectively connected to the drain of the PMOS tube Ms6 and the source of the PMOS tube Ms5, the gate of the PMOS tube Ms5 is respectively connected to the drain of the PMOS tube Ms5, the drain of the NMOS tube Ms4, the gate of the NMOS tube Ms4 and the gate of the NMOS tube Ms3.

[0026] In the self-bias pre-adjustment circuit 1, both the NMOS tube M1 and the NMOS tube M2 are depletion-type NMOS tubes, and the resistor R1 is a current-limiting resistor to prevent the circuit from consuming a large current; when the circuit is started, the depletion-type NMOS tube M1 and the depletion-type NMOS tube M2 are in a conducting state, charging the NPN transistor Q7 branch, and the base-emitter voltage of the NPN transistor Q2 rises, so that the base-emitter voltage of the NPN transistor Q1 rises, thereby making the self-bias pre-adjustment circuit 1 work normally; at the same time, the NPN transistors Q1, Q2, Q3, and Q7 are charged. PN transistor Q4, NPN transistor Q5, NPN transistor Q6, NPN transistor Q7, depletion-type NMOS tube M1, depletion-type NMOS tube M2 and resistor R1 form a negative feedback loop. When the external power supply VDD has a positive fluctuation voltage increase, the source of the depletion-type NMOS tube M2 has a positive fluctuation voltage, and the base-emitter voltage of the transistor connected by the diode rises, the collector current of the transistor increases, the collector is discharged, and the collector voltage is reduced, thereby suppressing the increase of the source voltage of the depletion-type NMOS tube M2, thereby improving the power supply rejection ratio (PSRR) of the circuit.

[0027] In the reference core circuit 2, all resistors are made of the same material, all MOS tubes are enhanced MOS tubes, NPN transistor Q12, NPN transistor Q13, resistor R6, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9 and NMOS tube M10 constitute an error amplifier, wherein NPN transistor Q12 and NPN transistor Q13 are used as differential input pairs to increase the common-mode input range of the error amplifier, resistor R6 is used to connect the emitter of the differential input pair to reduce the complexity of the circuit, and capacitor C1 is connected to the output end of the error amplifier to improve the circuit loop stability. The gain of the error amplifier is much greater than 1, forcing the in-phase input end and the inverting input end of the error amplifier to have the same voltage, the emitter area of ​​the NPN transistor Q10 is α times that of the NPN transistor Q9, and the resistor R3 is exactly the same as the resistor R4, then the current I flowing through the resistor R3 R3 The current I R4 have

[0028]

[0029] Where R5 is the resistance of resistor R5, V T is the thermal voltage and is equal to kT / q, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. NPN transistor Q9 is exactly the same as NPN transistor Q11, the emitter area of ​​NPN transistor Q14 is β times that of NPN transistor Q9, PMOS tube M4 is exactly the same as PMOS tube M11, the drain current I3 of PMOS tube M3 is negligibly small relative to the collector current of NPN transistor Q14, NPN transistor Q9, NPN transistor Q10, NPN transistor Q11 and NPN transistor Q14 have the same collector current, then the gate-source voltage V of PMOS tube M3 is GS3 have

[0030]

[0031] Where R3 is the resistance value of resistor R3. |V GS3 | is smaller than the absolute value of the threshold voltage of the PMOS tube, and the PMOS tube M3 works in the subthreshold region, then the drain current I3 of the PMOS tube M3 is

[0032]

[0033] In the formula, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, η is the subthreshold slope factor, (W / L)3 is the channel width-to-length ratio of the PMOS tube M3, V THp is the threshold voltage of the PMOS tube. Hole mobility μ p With temperature T has μ p =μ p0 (T / T0) -n , PMOS threshold voltage V THp With temperature T |V THp |=|V TH0 |-b(T-T0), where T0 is the reference temperature, μ p0 is the air attack mobility at the reference temperature T0, n is the process-related temperature coefficient, V TH0 is the threshold voltage at reference temperature T0, and b is the temperature coefficient of the threshold voltage. Therefore, the drain current I3 of the PMOS tube M3 has high-order temperature nonlinearity. Then, the voltage V REF have

[0034]

[0035] Where V BE9 is the base-emitter voltage of NPN transistor Q9, and R2 is the resistance value of resistor R2. Factor (R3+2R2)(lnα)V T / R5 can effectively compensate V BE9 The temperature first-order characteristic, factor I3R2 can effectively compensate for V BE9 The high-order nonlinearity of temperature is reduced to obtain a high-performance reference voltage.

[0036] Figure 3 This is a temperature characteristic simulation curve of a high PSRR reference circuit for a power management chip of the present invention, where the horizontal axis is the temperature T and the vertical axis is the output voltage waveform. The simulation results show that in the range of -40 to 125°C, the output voltage V REF The temperature coefficient is 2.57ppm / ℃.

[0037] Figure 4 This is a power supply rejection ratio (PSRR) simulation curve of a high PSRR reference circuit for a power management chip of the present invention, where the horizontal axis is the frequency f and the vertical axis is the PSRR. The simulation results show that the output voltage V REF The PSRRs at frequencies of 10Hz, 1kHz, 100kHz, 1MHz, and 100MHz are -131dB, -128dB, -92dB, -77dB, and -57dB respectively.

[0038] In the above embodiment of the present application, a high PSRR reference circuit for a power management chip includes a self-bias pre-adjustment circuit and a reference reference core circuit. The embodiment of the present application adopts a self-bias pre-adjustment technology that forms a negative feedback loop with depletion-type NMOS tubes M1-M2 and NPN transistors Q1-Q7 and provides a working power supply for the reference reference core circuit, thereby improving the power supply rejection ratio PSRR of the circuit, using NPN transistors Q12 and NPN transistors Q13 as input pairs of error amplifiers to increase the common-mode input range of the error amplifier, using resistor R6 to connect the emitter of the differential input pair of tubes to reduce the complexity of the circuit, and connecting capacitor C1 to the output end of the error amplifier to improve the stability of the circuit loop; using the current provided by the PMOS tube M3 working in the subthreshold region to generate a voltage on the resistor R2 to compensate the base-emitter voltage V of the NPN transistor Q9 BE9 The temperature high-order nonlinearity is reduced to obtain a high PSRR reference voltage, thereby realizing a high PSRR reference circuit.

[0039] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0040] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0041] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high PSRR reference circuit for a power management chip, characterized in that: include: A self-bias pre-adjustment circuit (1) and a reference core circuit (2), wherein the signal output end of the self-bias pre-adjustment circuit (1) is connected to the signal input end of the reference core circuit (2), the self-bias pre-adjustment circuit (1) provides working power to the reference core circuit (2) through a depletion-type NMOS tube M2, and the reference core circuit (2) uses a current provided by a PMOS tube M3 working in a subthreshold region to generate a voltage compensation NPN transistor Q9 base-emitter voltage V on a resistor R2 BE9 The high-order nonlinearity of temperature can generate a reference voltage with high power supply rejection ratio PSRR at the output terminal VREF of the circuit; The self-bias pre-adjustment circuit (1) comprises: a depletion-type NMOS tube M1, a depletion-type NMOS tube M2, a resistor R1, an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, an NPN transistor Q4, an NPN transistor Q5, an NPN transistor Q6 and an NPN transistor Q7, wherein the drain of the depletion-type NMOS tube M1 is respectively connected to the drain of the depletion-type NMOS tube M2 and an external power supply VDD, and the depletion-type NMOS tube M The source of the depletion-type NMOS tube M1 is connected to one end of the resistor R1, the gate of the depletion-type NMOS tube M1 is respectively connected to the gate of the depletion-type NMOS tube M2, the other end of the resistor R1 and the collector of the NPN transistor Q1, the source of the depletion-type NMOS tube M2 is respectively connected to the source of the PMOS tube M11, the collector of the NPN transistor Q8, the source of the PMOS tube M4, the source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube Ms1, the collector of the NPN transistor Q8, the collector of the NPN transistor Q9, the collector of the PMOS tube M10, the collector of the PMOS tube M11, the collector of the PMOS tube M12, the collector of the PMOS tube M13, the collector of the PMOS tube M14, the collector of the PMOS tube M15, the collector of the PMOS tube M16, the collector of the PMOS tube M17, the collector of the PMOS tube M18, the collector of the PMOS tube M19, the collector of the PMOS tube M20, the collector of the PMOS tube M21, the collector of the PMOS tube M22, the collector of the PMOS tube M23, the collector of the PMOS tube M24, the collector of the PMOS tube M25, the collector of the PMOS tube M26, the collector of the PMOS tube M27, the collector of the PMOS tube M28, the collector of the PMOS tube M29, the collector of the PMOS tube M30, the collector of the PMOS tube M31, the collector of the PMOS tube M32 The source of the OS transistor Ms2, the source of the PMOS transistor Ms6, the collector of the NPN transistor Q7 and the base of the NPN transistor Q7 are connected, the emitter of the NPN transistor Q7 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q6, the emitter of the NPN transistor Q6 is connected to the collector of the NPN transistor Q5 and the base of the NPN transistor Q5, the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5, the emitter of the NPN transistor Q5 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q5, the emitter of the NPN transistor Q6 ... 4 is connected to the collector of NPN transistor Q4 and the base of NPN transistor Q4, the emitter of NPN transistor Q4 is respectively connected to the collector of NPN transistor Q3 and the base of NPN transistor Q3, the emitter of NPN transistor Q3 is respectively connected to the collector of NPN transistor Q2, the base of NPN transistor Q2 and the base of NPN transistor Q1, the emitter of NPN transistor Q2 is respectively connected to the emitter of NPN transistor Q1 and the external ground wire GND; The benchmark reference core circuit (2) comprises: PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube Ms1, PMOS tube Ms2, NMOS tube Ms3, NMOS tube Ms4, PMOS tube Ms5, PMOS tube Ms6, capacitor C1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, NPN transistor Q8, NPN transistor Q9, NPN transistor Q10, NPN transistor Q11, NPN transistor Q12, NPN transistor Q13 and NPN transistor Q14, wherein The gate of the PMOS tube M11 is respectively connected to the drain of the PMOS tube M4, the gate of the PMOS tube M4, the gate of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube Ms1 and the collector of the NPN transistor Q11, the drain of the PMOS tube M11 is respectively connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14, the drain of the PMOS tube M3 and the gate of the PMOS tube M3, the base of the NPN transistor Q8 is respectively connected to the drain of the PMOS tube Ms2, one end of the capacitor C1, the drain of the PMOS tube M8 and the drain of the NMOS tube M10, the emitter of the NPN transistor Q8 is respectively connected to one end of the resistor R2 and the circuit output end VREF is connected, the other end of the resistor R2 is respectively connected to the source of the PMOS tube M3, one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is respectively connected to the collector of the NPN transistor Q9, the base of the NPN transistor Q9, the base of the NPN transistor Q10, the base of the NPN transistor Q11 and the base of the NPN transistor Q12, the other end of the resistor R4 is respectively connected to the base of the NPN transistor Q13 and the collector of the NPN transistor Q10, the emitter of the NPN transistor Q10 is connected to one end of the resistor R5, the emitter of the NPN transistor Q12 is respectively connected to the emitter of the NPN transistor Q13 and one end of the resistor R6, and the other end of the resistor R6 is respectively connected to The emitter of NPN transistor Q14, the emitter of NPN transistor Q9, the other end of resistor R5, the emitter of NPN transistor Q11, the source of NMOS tube M9, the source of NMOS tube M10, the other end of capacitor C1, the source of NMOS tube Ms3, the source of NMOS tube Ms4 and the external ground line GND are connected, the drain of PMOS tube M5 is respectively connected to the collector of NPN transistor Q12 and the source of PMOS tube M7, the gate of PMOS tube M7 is respectively connected to the gate of PMOS tube M8 and voltage bias terminal VB, the drain of PMOS tube M7 is respectively connected to the drain of NMOS tube M9, the gate of NMOS tube M9 and the gate of NMOS tube M10,The drain of the PMOS tube M6 is respectively connected to the collector of the NPN transistor Q13 and the source of the PMOS tube M8, the gate of the PMOS tube Ms2 is respectively connected to the drain of the PMOS tube Ms1 and the drain of the NMOS tube Ms3, the gate of the PMOS tube Ms6 is respectively connected to the drain of the PMOS tube Ms6 and the source of the PMOS tube Ms5, the gate of the PMOS tube Ms5 is respectively connected to the drain of the PMOS tube Ms5, the drain of the NMOS tube Ms4, the gate of the NMOS tube Ms4 and the gate of the NMOS tube Ms3; In the self-bias pre-adjustment circuit (1), both the NMOS tube M1 and the NMOS tube M2 are depletion-type NMOS tubes, and the resistor R1 is a current-limiting resistor; when the circuit is started, the depletion-type NMOS tube M1 and the depletion-type NMOS tube M2 are in a conducting state, charging the NPN transistor Q7 branch, and the base-emitter voltage of the NPN transistor Q2 rises, causing the base-emitter voltage of the NPN transistor Q1 to rise, thereby causing the self-bias pre-adjustment circuit (1) to work normally; at the same time, the NPN transistors Q1, Q2, Q3, and Q7 are charged. Transistor Q4, NPN transistor Q5, NPN transistor Q6, NPN transistor Q7, depletion-type NMOS tube M1, depletion-type NMOS tube M2 and resistor R1 form a negative feedback loop. When the external power supply VDD has a positive fluctuation voltage increase, the source of the depletion-type NMOS tube M2 has a positive fluctuation voltage, and the base-emitter voltage of the transistor connected by the diode rises, the collector current of the transistor increases, the collector is discharged, and the collector voltage is reduced, thereby suppressing the increase of the source voltage of the depletion-type NMOS tube M2, thereby improving the power supply rejection ratio PSRR of the circuit; In the reference core circuit (2), all resistors are made of the same material, all MOS tubes are enhanced MOS tubes, NPN transistor Q12, NPN transistor Q13, resistor R6, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9 and NMOS tube M10 constitute an error amplifier, wherein NPN transistor Q12 and NPN transistor Q13 are used as differential input pair tubes to increase the common mode input range of the error amplifier, resistor R6 is used to connect the emitter of the differential input pair tubes to reduce the complexity of the circuit, and capacitor C1 is connected to the output end of the error amplifier to improve the circuit loop stability; the gain of the error amplifier is much greater than 1, forcing the non-inverting input end and the inverting input end of the error amplifier to have the same voltage, the emitter area of ​​the NPN transistor Q10 is α times that of the NPN transistor Q9, the resistor R3 is exactly the same as the resistor R4, and the current flowing through the resistor R3 is the same as the current flowing through the resistor R4; In the benchmark reference core circuit (2), the NPN transistor Q9 is completely identical to the NPN transistor Q11, the emitter area of ​​the NPN transistor Q14 is β times that of the NPN transistor Q9, the PMOS transistor M4 is completely identical to the PMOS transistor M11, the drain current I3 of the PMOS transistor M3 is negligibly small relative to the collector current of the NPN transistor Q14, the NPN transistor Q9, the NPN transistor Q10, the NPN transistor Q11 and the NPN transistor Q14 have the same collector current, the PMOS transistor M3 operates in the subthreshold region and its drain current Among them, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, V T is the thermal voltage and is equal to kT / q, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, η is the subthreshold slope factor, (W / L)3 is the channel width-to-length ratio of the PMOS tube M3, R3 is the resistance value of the resistor R3, R5 is the resistance value of the resistor R5, α is the ratio of the emitter area of ​​the NPN transistor Q10 to the NPN transistor Q9, V THp is the threshold voltage of the PMOS tube; the hole mobility μ p With temperature T has μ p =μ p0 (T / T0) -n , PMOS threshold voltage V THp With temperature T |V THp |=|V TH0 |-b(T-T0), where T0 is the reference temperature, μ p0 is the air attack mobility at the reference temperature T0, n is the process-related temperature coefficient, V TH0 is the threshold voltage at the reference temperature T0, and b is the temperature coefficient of the threshold voltage; therefore, the drain current I3 of the PMOS tube M3 has a high-order temperature nonlinearity; The voltage V at the output of the high PSRR reference circuit VREF REF =V BE9 +(R3+2R2)(lnα)V T / R5+I3R2, where V BE9 is the base-emitter voltage of NPN transistor Q9, R3 is the resistance value of resistor R3, R2 is the resistance value of resistor R2, α is the ratio of the emitter area of ​​NPN transistor Q10 to that of NPN transistor Q9, V T is the thermal voltage, R5 is the resistance of resistor R5, I3 is the current of PMOS tube M3, and the factor is (R3+2R2)(lnα)V T / R5 can compensate V BE9 The temperature first-order characteristic, factor I3R2 can compensate for V BE9 The high-order nonlinearity of temperature is reduced to obtain a high-performance reference voltage.

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