Array substrate with reduced feedthrough voltage and manufacturing method thereof

Abstract

The application relates to the technical field of display, and provides an array substrate for reducing Feedthrough voltage and a manufacturing method thereof.The array substrate comprises a glass substrate, a first metal layer plated on the upper surface of the glass substrate and forming spacedly distributed gate electrodes, first CK signal wires, second CK signal wires, third CK signal wires and fourth CK signal wires, an active layer plated on the upper surface of a gate insulation layer, a second metal layer plated on the upper surface of the gate insulation layer and forming spacedly distributed source electrodes, drain electrodes, first signal connecting wires and second signal connecting wires, a conductive layer plated on the upper surface of a passivation layer and also located directly above the drain electrodes, and a pixel electrode plated on the upper surface of the passivation layer.The application has the advantage that the potential of the conductive layer is opposite to the potential of the gate electrodes, the coupling effect of the gate electrodes on the drain electrodes and the coupling effect of the conductive layer on the drain electrodes are counteracted, and the Feedthrough voltage is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to an array substrate for reducing Feedthrough voltage and a manufacturing method thereof. BACKGROUND

[0002] For TFT-LCD display, the side of TFT connected with pixel electrode is called drain, and the capacitance formed between drain and gate metal is called parasitic capacitance C gd . The gate of TFT device is connected with horizontally distributed gate line, for controlling the opening and closing of TFT device; the source of TFT device is connected with vertically distributed data line, for writing data voltage which is wanted to be displayed into TFT device; when TFT is opened, the source and drain are conducted, and data voltage enters into drain and then reaches liquid crystal capacitor Cst through pixel electrode, for adjusting the transmittance of liquid crystal; when TFT is closed, the source and drain are cut off, and data voltage of source cannot enter into drain. The data voltage of source is periodically positive and negative, which is the positive and negative deflection voltage of liquid crystal.

[0003] In combination Figure 1 With Figure 2 , at the moment when TFT is closed, the gate voltage V g drops from high level V high to low level V low . Due to the existence of parasitic capacitance C gd , the instantaneous change of V g will be coupled to drain, resulting in the drop of drain voltage. Since TFT device has been closed at this moment, the voltage difference between pixel electrode and drain will cause the jump of voltage of pixel electrode, and this jump ΔV is called Feedthrough voltage. Figure 2 In the waveform diagram, V g is gate voltage, V d is ideal drain voltage, is actual common electrode voltage, i.e. the center point of actual positive and negative deflection voltage, V p (t) is actual pixel electrode voltage, V com is ideal common electrode voltage for keeping the voltage of liquid crystal in positive and negative state, V offset is the deviation of ideal common electrode voltage from actual common electrode voltage, T f is the switching period of TFT device, Vlc V com is the region where pixel electrode voltage is greater than the current ideal common electrode voltage, V lc V comis a region where the pixel electrode voltage is less than the common electrode voltage in the ideal state.

[0004] As shown in Figure 2 Due to the existence of the Feedthrough voltage, the ideal state of the common electrode V com deviates from the center position of the actual provided positive and negative polarity deflection voltage, that is, the ideal state of the common electrode voltage changes, but the actual provided positive and negative polarity deflection voltage remains unchanged, which results in that the liquid crystal in the positive and negative polarity states has different voltages at both ends, so that the deflection angles of the liquid crystal in the positive and negative polarity states are different, and thus the light transmittance of the array substrate is different, causing flicker of the picture of the liquid crystal display. Therefore, reducing the Feedthrough voltage is a problem to be solved at present. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an array substrate for reducing the Feedthrough voltage and a manufacturing method thereof. By arranging a conductive layer above the drain electrode, the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are mutually offset, so as to reduce the Feedthrough voltage.

[0006] The present application is implemented as follows:

[0007] An array substrate for reducing the Feedthrough voltage

[0008] a glass substrate;

[0009] a first metal layer plated on the upper surface of the glass substrate, forming spaced gate electrodes, first, second, third and fourth CK signal lines, the potential of the first CK signal line being opposite to the potential of the third CK signal line, the potential of the second CK signal line being opposite to the potential of the fourth CK signal line, the gate electrodes being divided into first and second rows of gate electrodes;

[0010] a gate insulating layer plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with first, second, third and fourth holes in the pixel display area, the first row of gate electrodes being exposed to the first hole, the second row of gate electrodes being exposed to the second hole, the first CK signal line being exposed to the third hole, and the second CK signal line being exposed to the fourth hole;

[0011] an active layer plated on the upper surface of the gate insulating layer, the active layer being located directly above the gate electrodes and in the pixel display area;

[0012] A second metal layer is plated on the upper surface of the gate insulation layer, forming source electrodes, drain electrodes, first signal connection lines and second signal connection lines which are distributed at intervals, the source electrodes are connected to the left end of the active layer, the drain electrodes are connected to the right end of the active layer, the source electrodes and the drain electrodes are both located in the pixel display area, the right end of the first signal connection line passes through the first hole and is connected to the first row of gate electrodes, the left end of the first signal connection line passes through the third hole and is connected to the first CK signal line, the right end of the second signal connection line passes through the second hole and is connected to the second row of gate electrodes, and the left end of the second signal connection line passes through the fourth hole and is connected to the second CK signal line.

[0013] A passivation layer is plated on the upper surface of the gate insulation layer, the active layer and the second metal layer, the passivation layer is provided with a fifth hole and a sixth hole outside the pixel display area, and is provided with a seventh hole in the pixel display area, the fifth hole and the sixth hole both penetrate the gate insulation layer, the third CK signal line is exposed to the fifth hole, the fourth CK signal line is exposed to the sixth hole, and the drain electrode is exposed to the seventh hole.

[0014] A conductive layer is plated on the upper surface of the passivation layer and is located directly above the drain electrode, the conductive layer is divided into a first row of conductive layers and a second row of conductive layers, a third signal connection line and a fourth signal connection line are also plated on the upper surface of the passivation layer, the first row of conductive layers is connected to the right end of the third signal connection line, the left end of the third signal connection line passes through the fifth hole and is connected to the third CK signal line, the second row of conductive layers is connected to the right end of the fourth signal connection line, and the left end of the fourth signal connection line passes through the sixth hole and is connected to the fourth CK signal line.

[0015] A pixel electrode is plated on the upper surface of the passivation layer, and a lead wire of the pixel electrode passes through the seventh hole and is connected to the drain electrode.

[0016] Further comprising:

[0017] The second metal layer also forms TP lines which are distributed at intervals;

[0018] An outer insulation layer is plated on the upper surface of the pixel electrode, the conductive layer and the passivation layer, the outer insulation layer is provided with an eighth hole in the pixel display area, the eighth hole penetrates the passivation layer, and the TP line is exposed to the eighth hole;

[0019] A common electrode is plated on the upper surface of the outer insulation layer, and a lead wire of the common electrode also passes through the eighth hole and is connected to the TP line.

[0020] Further, the signal timing phase of the first CK signal trace is earlier than that of the second signal trace by a quarter of a period, and the signal timing phase of the third CK signal trace is earlier than that of the fourth CK signal trace by a quarter of a period.

[0021] Further, a driving IC is further included, which is connected with the first, second, third and fourth CK signal traces.

[0022] Further, the first metal layer is any one of a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure, and the second metal layer is a MO / AL / MO three-layer structure or a Ti / AL / Ti three-layer structure.

[0023] Further, the gate insulation layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is SiO2, and the outer insulation layer is SiOx, SiNO or SiNx.

[0024] Further, the active layer is IGZO, and the conductive layer, pixel electrode and common electrode are all ITO.

[0025] A manufacturing method of an array substrate for reducing Feedthrough voltage, comprising the following steps:

[0026] S1, plating a first metal layer on the upper surface of a glass substrate to form spaced gate electrodes, first, second, third and fourth CK signal traces, the potential of the first CK signal trace being opposite to that of the third CK signal trace, and the potential of the second CK signal trace being opposite to that of the fourth CK signal trace, the gate electrodes being divided into first and second rows of gate electrodes;

[0027] S2, plating a gate insulation layer on the upper surface of the glass substrate and the first metal layer, the gate insulation layer being provided with first, second, third and fourth holes outside the pixel display area, the first row of gate electrodes being exposed from the first hole, the second row of gate electrodes being exposed from the second hole, the first CK signal trace being exposed from the third hole, and the second CK signal trace being exposed from the fourth hole;

[0028] S3, plating an active layer on the upper surface of the gate insulation layer, the active layer being located directly above the gate electrodes and also within the pixel display area;

[0029] S4, plating a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, a first signal connection line and a second signal connection line which are distributed at intervals, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, the source electrode and the drain electrode both being located in the pixel display area, the right end of the first signal connection line being connected to the first row of gate electrodes through the first hole, the left end of the first signal connection line being connected to the first CK signal line through the third hole, the right end of the second signal connection line being connected to the second row of gate electrodes through the second hole, and the left end of the second signal connection line being connected to the second CK signal line through the fourth hole;

[0030] S5, plating a passivation layer on the upper surface of the gate insulating layer, the active layer and the second metal layer, the passivation layer being provided with a fifth hole and a sixth hole outside the pixel display area and a seventh hole inside the pixel display area;

[0031] The fifth hole, the sixth hole and the seventh hole are etched at the same time, the third CK signal line is exposed by continuing to etch the gate insulating layer downward after etching the passivation layer at the position of the fifth hole, the fourth CK signal line is exposed by continuing to etch the gate insulating layer downward after etching the passivation layer at the position of the sixth hole, and the outer metal layer of the drain electrode is etched after etching the passivation layer at the position of the seventh hole;

[0032] S6, plating a conductive layer, a third signal connection line, a fourth signal connection line and a pixel electrode on the upper surface of the passivation layer, the conductive layer being located directly above the drain electrode, the conductive layer being divided into a first row of conductive layers and a second row of conductive layers, the first row of conductive layers being connected to the right end of the third signal connection line, the left end of the third signal connection line being connected to the third CK signal line through the fifth hole, the second row of conductive layers being connected to the right end of the fourth signal connection line, the left end of the fourth signal connection line being connected to the fourth CK signal line through the sixth hole, and the lead wire of the pixel electrode being connected to the drain electrode through the seventh hole.

[0033] Further, the following steps are further included:

[0034] In the S4, the second metal layer also forms a TP line which is distributed at intervals;

[0035] S7, plating an outer insulating layer on the upper surface of the pixel electrode, the conductive layer and the passivation layer, the outer insulating layer being provided with an eighth hole in the pixel display area, the eighth hole penetrating the passivation layer, and the TP line being exposed to the eighth hole;

[0036] S8, plating a common electrode on the upper surface of the outer insulating layer, a lead of the common electrode passing through the eighth hole and connecting with the TP trace.

[0037] Further, in the S5, the etching method of the fifth hole, the sixth hole and the seventh hole is replaced by: etching the fifth hole, the sixth hole and the seventh hole simultaneously on the passivation layer until the fifth hole and the sixth hole expose the gate insulating layer and the seventh hole exposes the drain, then stopping etching the seventh hole, and then continuing etching the fifth hole and the sixth hole simultaneously until the third CK signal trace is exposed in the fifth hole and the fourth CK signal trace is exposed in the sixth hole.

[0038] The advantages of the present application are: 1. The conductive layer is arranged above the drain, a supplementary capacitance is formed between the conductive layer and the drain, the signal of the first row of gate is provided by the first CK signal trace, the signal of the second row of gate is provided by the second CK signal trace, the signal of the first row of conductive layer is provided by the third CK signal trace, the signal of the second row of conductive layer is provided by the fourth CK signal trace, the potential of the conductive layer is opposite to that of the gate, the coupling effect of the gate to the drain and the coupling effect of the conductive layer to the drain are counteracted, the voltage difference between the pixel electrode and the drain is reduced, thus the Feedthrough voltage is reduced and the picture flicker of the liquid crystal display is reduced; when the size of the supplementary capacitance is equal to that of the parasitic capacitance, the Feedthrough voltage is eliminated and the picture display stability of the liquid crystal display is improved. 2. Under the control of the first CK signal trace, the second CK signal trace, the third CK signal trace and the fourth CK signal trace, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are opened and closed in turn, the first row of pixels and the second row of pixels of the display screen are set with brightness in turn, and the liquid crystal display screen is displayed stably row by row. 3. The conductive layer is arranged at a position close to the contact between the drain and the active layer, the field strength at this position is larger, thus the Schottky barrier formed by the contact between the semiconductor of the active layer and the metal wire of the drain can be reduced, the contact resistance can be reduced, and thus the on-state current is increased. 4. ITO has good conductivity and light transmittance, the conductive layer of the array substrate and the pixel electrode of the present application are both made of ITO, so the conductive layer and the pixel electrode can be formed in the same process, thus the substrate structure can be simplified and the production capacity can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0040] Figure 1 is a schematic diagram of the parasitic capacitance between the gate and the drain of the TFT device in the background art.

[0041] Figure 2The ideal common electrode V is caused by the existence of the Feedthrough voltage in the background technology. com Schematic diagram of point deviation.

[0042] Figure 3 This is a simplified design diagram of an array substrate for reducing feedthrough voltage according to the present invention.

[0043] Figure 4 yes Figure 3 FIG. 1 is a circuit diagram of the first row of TFT devices on the array substrate.

[0044] Figure 5 yes Figure 3 FIG. 1 is a circuit diagram of the second row of TFT devices on the array substrate.

[0045] Figure 6 This is a timing diagram of the first CK signal routing, the second CK signal routing, the third CK signal routing, and the fourth CK signal routing in the present invention.

[0046] Figure 7 It is a top view schematic diagram of an array substrate for reducing feedthrough voltage according to the present invention.

[0047] Figure 8.1 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure One .

[0048] Figure 8.2 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure Two .

[0049] Figure 8.3 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure Three .

[0050] Figure 8.4 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure Four .

[0051] Figure 8.5 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure Five .

[0052] Figure 8.6 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage. Figure Six .

[0053] Figure 8.7 The present invention is a process for manufacturing an array substrate for reducing feedthrough voltage.Figure Seven .

[0054] Figure 8.8 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0055] Figure 8.9 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0056] Figure 8.10 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0057] Figure 8.11 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0058] Figure 8.12 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0059] Figure 8.13 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0060] Figure 8.14 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0061] Figure 8.15 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0062] Figure 8.16 is a manufacturing flowchart of the array substrate of the present application for reducing Feedthrough voltage.

[0063] Reference numerals: glass substrate 1; pixel display area 11;

[0064] gate 2; first row gate 21; second row gate 22;

[0065] first CK signal wire 31; second CK signal wire 32; third CK signal wire 33; fourth CK signal wire 34;

[0066] gate insulation layer 4; first hole 41; second hole 42; third hole 43; fourth hole 44;

[0067] active layer 5;

[0068] source 6;

[0069] drain 7;

[0070] First signal connection line 81; second signal connection line 82; third signal connection line 83; fourth signal connection line 84;

[0071] Passivation layer 9; fifth hole 91; sixth hole 92; seventh hole 93;

[0072] Conductive layer 10; first row of conductive layers 101; second row of conductive layers 102;

[0073] Pixel electrode 20;

[0074] TP trace 30;

[0075] Outer insulating layer 40; eighth hole 401;

[0076] Common electrode 50. DETAILED DESCRIPTION

[0077] The array substrate for reducing Feedthrough voltage and the manufacturing method thereof provided by the embodiment of the present application solve the defect of flickering of the liquid crystal display picture caused by the existence of Feedthrough voltage in the background art, and achieve the technical effects of reducing Feedthrough voltage and stabilizing the liquid crystal display picture.

[0078] The technical solution in the embodiment of the present application is as follows to solve the above-mentioned defects:

[0079] The main improvement of the present application is that after the passivation layer is plated, a conductive layer is plated above the drain electrode, and the conductive layer and the drain electrode form a complementary capacitor C 补充 The potential of the conductive layer is always opposite to the potential of the gate of the TFT array substrate at any time, and there is a parasitic capacitor C gd between the drain electrode and the gate of the TFT device. Thus, the coupling effect of the gate on the drain electrode and the coupling effect of the conductive layer on the drain electrode are offset to each other, so as to reduce the voltage difference between the pixel electrode and the drain electrode, reduce the voltage jump of the pixel electrode, and achieve the purpose of reducing Feedthrough voltage. The signal of the first row of gate electrodes is provided by the first CK signal trace, the signal of the second row of gate electrodes is provided by the second CK signal trace, the signal of the first row of conductive layers is provided by the third CK signal trace, and the signal of the second row of conductive layers is provided by the fourth CK signal trace; when the complementary capacitor C 补充 is consistent with the parasitic capacitor C gd , the Feedthrough voltage caused by the signal change of the gate can be eliminated. The complementary capacitor C 补充 can be consistent with the parasitic capacitor C gd by adjusting the opposite area and the film distance between the conductive layer and the drain electrode.

[0080] Under the control of the first CK signal wire, the second CK signal wire, the third CK signal wire and the fourth CK signal wire, the first row TFT device and the second row TFT device of the liquid crystal display screen are opened and closed in sequence, so that the first row pixel and the second row pixel of the display screen are set in brightness in sequence, and the liquid crystal display screen is stably displayed row by row.

[0081] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments.

[0082] Referring to Figures 1 to 8.16 , the preferred embodiments of the present application.

[0083] An array substrate for reducing Feedthrough voltage, comprising:

[0084] A glass substrate 1;

[0085] A first metal layer is plated on the upper surface of the glass substrate 1, forming a gate 2, a first CK signal wire 31 (CK1), a second CK signal wire 32 (CK2), a third CK signal wire 33 (CK3) and a fourth CK signal wire 34 (CK4) which are distributed at intervals, the potential of the first CK signal wire 31 is opposite to the potential of the third CK signal wire 33, the potential of the second CK signal wire 32 is opposite to the potential of the fourth CK signal wire 34, and the gate 2 is divided into a first row gate 21 and a second row gate 22;

[0086] A gate insulating layer 4 is plated on the upper surface of the glass substrate 1 and the first metal layer, the gate insulating layer 4 is provided with a first hole 41, a second hole 42, a third hole 43 and a fourth hole 44 on the surface of the pixel display area 11, the first row gate 21 is exposed to the first hole 41, the second row gate 22 is exposed to the second hole 42, the first CK signal wire 31 is exposed to the third hole 43, and the second CK signal wire 32 is exposed to the fourth hole 44;

[0087] An active layer 5 is plated on the upper surface of the gate 2 insulating layer, the active layer 5 is located directly above the gate 2 and also in the pixel display area 11;

[0088] A second metal layer is plated on the upper surface of the gate insulation layer 4, forming the source electrode 6, the drain electrode 7, the first signal connecting line 81 and the second signal connecting line 82 which are distributed at intervals, the source electrode 6 is connected with the left end of the active layer 5, the drain electrode 7 is connected with the right end of the active layer 5, the source electrode 6 and the drain electrode 7 are both located in the pixel display area 11, the right end of the first signal connecting line 81 is connected with the first row gate electrode 21 through the first hole 41, the left end of the first signal connecting line 81 is connected with the first CK signal line 31 through the third hole 43, the right end of the second signal connecting line 82 is connected with the second row gate electrode 22 through the second hole 42, the left end of the second signal connecting line 82 is connected with the second CK signal line 32 through the fourth hole 44;

[0089] A passivation layer 9 is plated on the upper surface of the gate insulation layer 4, the active layer 5 and the second metal layer, the passivation layer 9 is provided with the fifth hole 91 and the sixth hole 92 which are located outside the pixel display area 11, and the seventh hole 93 which is located inside the pixel display area 11, the fifth hole 91 and the sixth hole 92 both penetrate the gate insulation layer 4, the third CK signal line 33 is exposed from the fifth hole 91, the fourth CK signal line 34 is exposed from the sixth hole 92, and the drain electrode 7 is exposed from the seventh hole 93;

[0090] A conductive layer 10 is plated on the upper surface of the passivation layer 9 and is located directly above the drain electrode 7, the conductive layer 10 is divided into the first row conductive layer 101 and the second row conductive layer 102, the third signal connecting line 83 and the fourth signal connecting line 84 are also plated on the upper surface of the passivation layer 9, the first row conductive layer 101 is connected with the right end of the third signal connecting line 83, the left end of the third signal connecting line 83 is connected with the third CK signal line 33 through the fifth hole 91, the second row conductive layer 102 is connected with the right end of the fourth signal connecting line 84, and the left end of the fourth signal connecting line 84 is connected with the fourth CK signal line 34 through the sixth hole 92;

[0091] A pixel electrode 20 is plated on the upper surface of the passivation layer 9, the lead wire of the pixel electrode 20 is connected with the drain electrode 7 through the seventh hole 93.

[0092] In the present application, the conductive layer 10 is arranged above the drain 7, a complementary capacitor is formed between the conductive layer 10 and the drain 7, the signal of the first row of gate 21 is provided by the first CK signal line 31, the signal of the second row of gate 22 is provided by the second CK signal line 32, the signal of the first row of conductive layer 101 is provided by the third CK signal line 33, and the signal of the second row of conductive layer 102 is provided by the fourth CK signal line 34. In the same row of TFT devices, the potential of the conductive layer 10 is opposite to the potential of the gate 2, the coupling effect of the gate 2 on the drain 7 and the coupling effect of the conductive layer 10 on the drain 7 are offset to each other, the voltage difference generated between the pixel electrode 20 and the drain 7 is reduced, thereby reducing the Feedthrough voltage, and when the size of the complementary capacitor is equal to that of the parasitic capacitor, the Feedthrough voltage is eliminated. Effectively prevent the V com point of the common electrode 50 in the ideal state from deviating from the center position of the positive and negative polarity deflection voltage actually provided; keep the two end voltage values of the liquid crystal in the positive and negative polarity states the same, so that the deflection angles of the liquid crystal in the positive and negative polarity states are the same, thereby the light transmittance of the array substrate is the same, and the picture of the liquid crystal display is stable.

[0093] Under the control of the first CK signal line 31, the second CK signal line 32, the third CK signal line 33 and the fourth CK signal line 34, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are opened and closed in turn, so that the first row of pixels and the second row of pixels of the display screen are set to have brightness in turn, and the liquid crystal display screen is stably displayed row by row.

[0094] The conductive layer 10 is arranged at a position close to the contact between the drain 7 and the active layer 5, and the field strength at this position is larger, so that the Schottky barrier formed by the contact between the semiconductor of the active layer 5 and the metal wire of the drain 7 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

[0095] Further comprising: the second metal layer also forms the TP line 30 which is distributed at intervals;

[0096] The outer insulating layer 40 is plated on the upper surfaces of the pixel electrode 20, the conductive layer 10 and the passivation layer 9, the eighth hole 401 is formed in the pixel display area 11 in the plane of the outer insulating layer 40, the eighth hole 401 penetrates the passivation layer 9, and the TP line 30 is exposed to the eighth hole 401;

[0097] The common electrode 50 is plated on the upper surface of the outer insulating layer 40, the lead of the common electrode 50 also passes through the eighth hole 401 and is connected with the TP line 30. One end of the liquid crystal Cst of the liquid crystal display is connected with the pixel electrode 20, and the other end is connected with the common electrode 50. The full name of the TP line is Touch Panel Senser Line; the TP line 30 provides a voltage signal for the common electrode 50.

[0098] The signal timing phase of the first CK signal line 31 is earlier than that of the second signal line by a quarter of a cycle, and the signal timing phase of the third CK signal line 33 is earlier than that of the fourth CK signal line 34 by a quarter of a cycle. When the first CK signal line 31 drives the gate 2 of the first row of TFT devices to be high, the source 6 and the drain 7 of the first row of TFT devices are turned on, and the data voltage signal is written to the pixel electrode 20. After a quarter of a cycle, the second CK signal line 32 drives the gate 2 of the second row of TFT devices to be high, the source 6 and the drain 7 of the second row of TFT devices are turned on, and the data voltage signal is written to the pixel electrode 20. When the first CK signal line 31 is high, the third CK signal line 33 is low, and when the first CK signal line 31 is low, the third CK signal line 33 is high. Similarly, the potential of the second CK signal line 32 is opposite to that of the fourth CK signal line 34. Under the control of the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34, the array substrate causes the display screen to be sequentially lit from top to bottom or from bottom to top by row by row of pixels. For example, when the first CK signal line 31 is 10V, the third CK signal line 33 is -15V; when the first CK signal line 31 is -15V, the third CK signal line 33 is 10V.

[0099] The drive IC is also connected to the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34. The drive IC is used to give different timing signals to the first CK signal line 31, the second CK signal line 32, the third CK signal line 33, and the fourth CK signal line 34.

[0100] The first metal layer is any one of a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, or an AL / Ti double-layer structure, and the second metal layer is a MO / AL / MO three-layer structure or a Ti / AL / Ti three-layer structure.

[0101] The gate insulating layer 4 is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, the passivation layer 9 is SiO2, and the outer insulating layer 40 is SiOx, SiNO, or SiNx.

[0102] The active layer 5 is IGZO, and the conductive layer 10, the pixel electrode 20, and the common electrode 50 are all ITO. The third signal connection line 83 and the fourth signal connection line 84 are also ITO.

[0103] The working principle of the array substrate of the present application for reducing the Feedthrough voltage:

[0104] The present embodiment is described by taking the design of single-side level transmission 4CK as an example (note that the circuit design of the present application is not limited to single-side level transmission 4CK, but can also be double-side level transmission), and the timing diagram is shown in Figure 6 , Figure 4 is Figure 3 the circuit diagram corresponding to all pixel TFTs in the first row in Figure 5 is Figure 3 the circuit diagram corresponding to all pixel TFTs in the second row in Briefly, the display of a picture is realized by sequentially lighting one row after another from top to bottom or from bottom to top. The lighting of a pixel requires that the gate 2 corresponding to the TFT device of the pixel in the row is at a high potential, then the TFT device is turned on, and the data signal can be written into the pixel electrode 20, thereby controlling the twist of the liquid crystal and lighting the pixel. Taking the display of the first row of pixels as an example, when the first CK signal wire 31 is at a high potential and the third CK signal wire 33 is at a low potential, the high potential of the first CK signal wire 31 is transmitted to the first row of gates 21, the TFT device of the first row is turned on, the signal of the pixel electrode 20 is written in, and the low potential of the third CK signal wire 33 is transmitted to the conductive layer 10 of the first row; when the first CK signal wire 31 is switched to a low potential and the third CK signal wire 33 is switched to a high potential, the gate 2 is switched from a high potential to a low potential, and the parasitic capacitance formed by the gate 2 and the drain 7 will have a coupling effect, thereby pulling down the voltage of the drain 7. However, since the third CK signal wire 33 is switched from a low potential to a high potential at this time, i.e., the conductive layer 10 of the first row is switched from a low potential to a high potential, the complementary capacitance formed by the conductive layer 10 and the drain 7 will also have a coupling effect, thereby pulling up the voltage of the drain 7, so the voltage of the drain 7 will not change due to the jump of the gate 2, that is, the voltage of the pixel electrode 20 will not change. Note that the design requires that the size of C 补充 and C gs are equal, and the purpose of this design is to make the two Feedthrough voltages of the drain 7 increase and decrease and equal in size. By analogy, the TFT device of each row can avoid the Feedthrough voltage caused by the jump of the gate 2.

[0105] From a microscopic perspective, it is actually the migration of charges between the drain 7 and the pixel electrode 20 that causes the amount of charge stored on the pixel electrode 20 to change, thereby causing the voltage to change. After the pixel electrode 20 is charged, the potential between the drain 7 and the pixel electrode 20 is equal, and no electron migration occurs between them. However, since the gate 2 voltage switches from a high potential to a low potential at this moment, this change will be coupled to the drain 7 through the parasitic capacitance formed by the gate 2 and the drain 7. At this time, a voltage difference will be generated between the drain 7 and the pixel electrode 20, causing charge migration between the drain 7 and the pixel electrode 20, thereby causing the pixel electrode 20 to change. The starting point for the present invention to solve this problem is to add a conductive layer 10, which forms a supplementary capacitor C with the drain 7. 补充 Then, opposite potential signals are given to the first row gate 21 and the first row conductive layer 101 through the first CK signal line 31 and the third CK signal line 33, and opposite potential signals are given to the second row gate 22 and the second row conductive layer 102 through the second CK signal line 32 and the fourth CK signal line 34, respectively. This offsets the coupling effect of the parasitic capacitance and the supplementary capacitance, and also improves the working performance of the device.

[0106] A method for manufacturing an array substrate for reducing feedthrough voltage comprises the following steps:

[0107] S1. See Figure 8.1 A first metal layer is plated on the upper surface of the glass substrate 1 to form a gate 2, a first CK signal line 31, a second CK signal line 32, a third CK signal line 33, and a fourth CK signal line 34 that are spaced apart. The potential of the first CK signal line 31 is opposite to that of the third CK signal line 33, and the potential of the second CK signal line 32 is opposite to that of the fourth CK signal line 34. The gate 2 is divided into a first row of gates 21 and a second row of gates 22.

[0108] Gate 2 is used to turn on and off TFT device, the first CK signal line 31 is used to transmit the first row gate 21 signal, the second CK signal line 32 is used to transmit the second row gate 22 signal, the third CK signal line 33 is used to transmit the first row conductive layer 101 signal, the fourth CK signal line 34 is used to transmit the second row conductive layer 102 signal; the material of the first metal layer can be selected from MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure (MO as the top layer), AL / Ti double-layer structure (Ti as the top layer) and the like, and PVD film forming. The resistance of AL is small and is used for conduction (which can be replaced by Cu), which can reduce the impedance and reduce the power consumption; secondly, the expansion coefficients of MO or Ti are small, which can inhibit the deformation of AL in high temperature process, and can also prevent the oxidation of AL.

[0109] S2, refer to Figures 8.2 to 8.4 The gate insulation layer 4 is plated on the upper surface of the glass substrate 1 and the first metal layer, and the gate insulation layer 4 is provided with a first hole 41, a second hole 42, a third hole 43 and a fourth hole 44 outside the pixel display area 11, the first row gate 21 is exposed to the first hole 41, the second row gate 22 is exposed to the second hole 42, the first CK signal line 31 is exposed to the third hole 43, and the second CK signal line 32 is exposed to the fourth hole 44.

[0110] The gate insulation layer 4 acts as an insulating medium and also as a capacitive medium between the gate 2 and the active layer 5, and the material is a single layer of SiOx or a double layer of SiNx / SiOx, which is formed by CVD. Considering the current requirements of TFT device, which are fast response and low power consumption, these are achieved by reducing the size of TFT device, and in order to realize the miniaturization of the device, the gate insulation layer 4 needs to select a suitable high-K material (such as HfO2), but considering that there are many defects in the interface of HfO2, if it is directly in contact with the active layer 5 or the gate 2 metal, it may affect the stability of the device, so the interface of SiOx or SiNx (SiNx can only be used as a contact film layer with the gate metal layer, if it is used as a contact surface with IGZO, the residual H in the SiNx film layer will destroy the characteristics of IGZO) can be considered as a contact surface, such as a three-layer structure of SiOx / HfO2 / SiOx as a GI insulating layer, in order to ensure the advantages of high-K material, the thickness of HfO2 in the three-layer structure needs to be larger than that of SiOx.

[0111] The first hole 41, the second hole 42, the third hole 43 and the fourth hole 44 are etched in the gate insulation layer 4 in a dry etching manner.

[0112] S3, refer to Figure 8.5, coating an active layer 5 on the upper surface of the gate insulating layer 4, wherein the active layer 5 is located directly above the gate 2 and also within the pixel display area 11;

[0113] The material of the active layer 5 is a metal oxide semiconductor such as IGZO, formed by PVD, and etched by wet etching.

[0114] S4, Figures 8.6 to 8.8 , a second metal layer is plated on the upper surface of the gate insulating layer 4 to form a source electrode 6, a drain electrode 7, a first signal connection line 81 and a second signal connection line 82 that are spaced apart. The source electrode 6 is connected to the left end of the active layer 5, and the drain electrode 7 is connected to the right end of the active layer 5. The source electrode 6 and the drain electrode 7 are both located within the pixel display area 11. The right end of the first signal connection line 81 passes through the first hole 41 and is connected to the first row gate 21. The left end of the first signal connection line 81 passes through the third hole 43 and is connected to the first CK signal line 31. The right end of the second signal connection line 82 passes through the second hole 42 and is connected to the second row gate 22. The left end of the second signal connection line 82 passes through the fourth hole 44 and is connected to the second CK signal line 32.

[0115] The second metal layer can be constructed using a stack of MO / AL / MO or Ti / AL / Ti, using PVD deposition and acid wet etching. AL has low electrical resistance and is used for conductivity (Cu can be substituted), reducing impedance and power consumption. Furthermore, the low coefficient of expansion of the outer metal, MO or Ti, suppresses deformation of the AL during high-temperature processes and prevents oxidation.

[0116] S5. See Figures 8.9 to 8.11 , a passivation layer 9 is plated on the upper surfaces of the gate insulating layer 4, the active layer 5, and the second metal layer, the passivation layer 9 is provided with a fifth hole 91 and a sixth hole 92 outside the pixel display area 11, and a seventh hole 93 is provided inside the pixel display area 11;

[0117] The fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched simultaneously. At the position of the fifth hole 91, after etching the passivation layer 9, the gate insulation layer 4 is etched downward until the third CK signal line 33 is exposed. At the position of the sixth hole 92, after etching the passivation layer 9, the gate insulation layer 4 is etched downward until the fourth CK signal line 34 is exposed. At the position of the seventh hole 93, after etching the passivation layer 9, the outer metal of the drain 7 is etched. Since the fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched simultaneously, the depth of etching the outer metal of the drain 7 at the position of the seventh hole 93 is equal to the depth of etching the gate insulation layer 4 at the fifth hole 91.

[0118] The advantage of etching the fifth hole 91, the sixth hole 92 and the seventh hole 93 simultaneously is that one photomask is saved; the disadvantage is that the MO or Ti of the drain 7 may be lost, and the Al may be exposed to the air and oxidized, resulting in problems such as large contact resistance.

[0119] Since the position of the drain 7 is higher than the position of the third CK signal line 33, when the fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched simultaneously, the fifth hole 91 and the sixth hole 92 only reach the upper surface of the gate insulation layer 4 when the seventh hole 93 reaches the upper surface of the drain 7; when the fifth hole 91 and the sixth hole 92 continue to etch downward to reach the upper surfaces of the third CK signal line 33 and the fourth CK signal line 34 respectively, the seventh hole 93 also needs to continue to etch downward to the same depth, which will cause the outer protective metal MO or Ti of the MO / AL / MO three-layer structure or the Ti / AL / Ti three-layer structure of the drain 7 to be missing, and the AL may be exposed to the air and oxidized, resulting in a large contact resistance.

[0120] The passivation layer 9 is made of SiO2, formed using CVD. The fifth hole 91 provides a connection between the third CK signal trace 33 and the first row of conductive layer 101. The sixth hole 92 provides a connection between the fourth CK signal trace 34 and the second row of conductive layer 102. The seventh hole 93 provides a connection between the pixel electrode 20 and the drain electrode 7.

[0121] S6. See Figures 8.12 to 8.14 A conductive layer 10, a third signal connection line 83, a fourth signal connection line 84, and a pixel electrode 20 are plated on the upper surface of the passivation layer 9. The conductive layer 10 is located directly above the drain electrode 7. The conductive layer 10 is divided into a first row of conductive layers 101 and a second row of conductive layers 102. The first row of conductive layers 101 is connected to the right end of the third signal connection line 83. The left end of the third signal connection line 83 passes through the fifth hole 91 and is connected to the third CK signal trace 33. The second row of conductive layers 102 is connected to the right end of the fourth signal connection line 84. The left end of the fourth signal connection line 84 passes through the sixth hole 92 and is connected to the fourth CK signal trace 34. The lead of the pixel electrode 20 passes through the seventh hole 93 and is connected to the drain electrode 7.

[0122] The conductive layer 10 is not covered to the channel of the active layer 56; the material of the conductive layer 10 and the pixel electrode 20 is selected as ITO, mainly because ITO has good conductivity and light transmittance, PVD film forming, acid liquid wet etching. The conductive layer 10 is required to be designed directly above the drain 7, the purpose is that the conductive layer 10 and the drain 7 form a complementary capacitor, and the size of the complementary capacitor is required to be consistent with the size of the parasitic capacitor formed by the gate 2 and the drain 7, which can be achieved by adjusting the size of the conductive layer 10 and the film layer distance.

[0123] Further comprising the following steps:

[0124] Referring to Figure 8.6 In the S4, the second metal layer also forms the TP trace 30 distributed at intervals;

[0125] S7, referring to Figure 8.15 The outer insulation layer 40 is plated on the upper surface of the pixel electrode 20, the conductive layer 10 and the passivation layer 9, the eighth hole 401 is opened in the pixel display area 11 of the outer insulation layer 40, the eighth hole 401 penetrates the passivation layer 9, and the TP trace 30 is exposed to the eighth hole 401;

[0126] The material of the outer insulation layer 40 can be SiOx, SiNO, SiNx, etc., and CVD film forming. The eighth hole 401 is obtained by dry etching to pass through the outer insulation layer 40 and the passivation layer 9 until the TP trace 30 is exposed, the purpose is to provide the connection between the common electrode 50 and the TP trace 30.

[0127] S8, referring to Figure 8.16 The common electrode 50 is plated on the upper surface of the outer insulation layer 40, and the lead of the common electrode 50 is connected with the TP trace 30 through the eighth hole 401.

[0128] The material of the common electrode 50 is selected as ITO, mainly because ITO has good conductivity and light transmittance, PVD film forming, acid liquid wet etching.

[0129] One end of the liquid crystal Cst of the liquid crystal display is connected with the pixel electrode 20, and the other end is connected with the common electrode 50. The full name of the TP trace 30 is Touch Panel Senser Line; the TP trace 30 provides voltage signal for the common electrode 50.

[0130] In another implementation of the embodiment, in the S5, the etching method of the fifth, sixth and seventh holes 91, 92 and 93 is replaced by: etching the fifth, sixth and seventh holes 91, 92 and 93 simultaneously in the passivation layer 9 until the fifth and sixth holes 91 and 92 expose the gate insulation layer 4 and the seventh hole 93 exposes the drain 7, then stop etching the seventh hole 93, and continue etching the fifth and sixth holes 91 and 92 simultaneously until the third CK signal wire 33 is exposed in the fifth hole 91 and the fourth CK signal wire 34 is exposed in the sixth hole 92. The advantage here is that the drain 7 will not have the problem of AL being oxidized and impedance increasing caused by MO or Ti missing; the disadvantage is that since the sixth and seventh holes 92 and 93 are etched twice, there is one more etching process and one more mask cost.

[0131] Although the specific embodiments of the present application have been described above, it should be understood by those skilled in the art that the specific embodiments described are merely illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and variations made in accordance with the spirit of the present application should be covered by the scope of the claims of the present application.

Claims

1. An array substrate for reducing feedthrough voltage, characterized in that: include: glass substrate; a first metal layer, plated on the upper surface of the glass substrate, forming gates, a first CK signal line, a second CK signal line, a third CK signal line, and a fourth CK signal line that are spaced apart from each other, wherein the potential of the first CK signal line is opposite to that of the third CK signal line, and the potential of the second CK signal line is opposite to that of the fourth CK signal line, and the gates are divided into a first row of gates and a second row of gates; a gate insulating layer plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer having a first hole, a second hole, a third hole, and a fourth hole outside the pixel display area, the first row of gates being exposed through the first hole, the second row of gates being exposed through the second hole, the first CK signal trace being exposed through the third hole, and the second CK signal trace being exposed through the fourth hole; An active layer, plated on the upper surface of the gate insulating layer, the active layer being located directly above the gate and also within the pixel display area; a second metal layer, plated on the upper surface of the gate insulating layer, forming a source electrode, a drain electrode, a first signal connection line, and a second signal connection line that are spaced apart from each other, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, the source electrode and the drain electrode being both located within the pixel display area, the right end of the first signal connection line passing through the first excavated hole to be connected to the first row of gate electrodes, the left end of the first signal connection line passing through the third excavated hole to be connected to the first CK signal line, the right end of the second signal connection line passing through the second excavated hole to be connected to the second row of gate electrodes, and the left end of the second signal connection line passing through the fourth excavated hole to be connected to the second CK signal line; a passivation layer, plated on the upper surfaces of the gate insulating layer, the active layer, and the second metal layer; the passivation layer having a fifth hole and a sixth hole outside the pixel display area, and a seventh hole inside the pixel display area; the fifth hole and the sixth hole both penetrate the gate insulating layer; the third CK signal line is exposed through the fifth hole, the fourth CK signal line is exposed through the sixth hole, and the drain electrode is exposed through the seventh hole; a conductive layer, plated on the upper surface of the passivation layer and also located directly above the drain electrode, the conductive layer being divided into a first row of conductive layers and a second row of conductive layers, a third signal connection line and a fourth signal connection line being further plated on the upper surface of the passivation layer, the first row of conductive layers being connected to the right end of the third signal connection line, the left end of the third signal connection line passing through the fifth hole and connected to the third CK signal line, the second row of conductive layers being connected to the right end of the fourth signal connection line, the left end of the fourth signal connection line passing through the sixth hole and connected to the fourth CK signal line; A pixel electrode is plated on the upper surface of the passivation layer, and a lead of the pixel electrode passes through the seventh hole and is connected to the drain electrode.

2. The array substrate for reducing feedthrough voltage according to claim 1, wherein: Also includes: The second metal layer also forms TP traces distributed at intervals; an outer insulating layer, plated on the upper surfaces of the pixel electrode, the conductive layer, and the passivation layer, wherein the outer insulating layer has an eighth hole formed in the pixel display area, the eighth hole penetrating the passivation layer, and the TP trace is exposed through the eighth hole; A common electrode is plated on the upper surface of the outer insulating layer, and a lead of the common electrode passes through the eighth hole and is connected to the TP trace.

3. The array substrate for reducing feedthrough voltage according to claim 1, wherein: The signal timing phase of the first CK signal line is one quarter cycle earlier than the signal timing phase of the second signal line, and the signal timing phase of the third CK signal line is one quarter cycle earlier than the signal timing phase of the fourth CK signal line.

4. The array substrate for reducing feedthrough voltage according to claim 3, wherein: It also includes a driver IC, which is connected to the first CK signal line, the second CK signal line, the third CK signal line, and the fourth CK signal line.

5. The array substrate for reducing feedthrough voltage according to claim 2, wherein: The first metal layer is any one of a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure, and the second metal layer is a MO / AL / MO three-layer structure or a Ti / AL / Ti three-layer structure.

6. The array substrate for reducing feedthrough voltage according to claim 2, wherein: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is made of SiO2, and the outer insulating layer is made of SiOx, SiNO or SiNx.

7. The array substrate for reducing feedthrough voltage according to claim 2, wherein: The active layer is made of IGZO material, and the conductive layer, pixel electrode and common electrode are all made of ITO material.

8. A method for manufacturing an array substrate for reducing feedthrough voltage, characterized in that: The following steps are involved: S1. Coating a first metal layer on the upper surface of a glass substrate to form gates, a first CK signal line, a second CK signal line, a third CK signal line, and a fourth CK signal line that are spaced apart. The potential of the first CK signal line is opposite to that of the third CK signal line, and the potential of the second CK signal line is opposite to that of the fourth CK signal line. The gates are divided into a first row of gates and a second row of gates. S2. Coating a gate insulating layer on the upper surface of the glass substrate and the first metal layer, the gate insulating layer having a first hole, a second hole, a third hole, and a fourth hole outside the pixel display area, the first row of gates being exposed through the first hole, the second row of gates being exposed through the second hole, the first CK signal trace being exposed through the third hole, and the second CK signal trace being exposed through the fourth hole; S3, coating an active layer on the upper surface of the gate insulating layer, wherein the active layer is located directly above the gate and also within the pixel display area; S4. Plate a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, a first signal connection line, and a second signal connection line that are spaced apart. The source electrode is connected to the left end of the active layer, and the drain electrode is connected to the right end of the active layer. Both the source electrode and the drain electrode are located within the pixel display area. The right end of the first signal connection line passes through the first hole and is connected to the first row of gate electrodes. The left end of the first signal connection line passes through the third hole and is connected to the first CK signal line. The right end of the second signal connection line passes through the second hole and is connected to the second row of gate electrodes. The left end of the second signal connection line passes through the fourth hole and is connected to the second CK signal line. S5, coating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, and the second metal layer, wherein the passivation layer has a fifth hole and a sixth hole outside the pixel display area, and has a seventh hole inside the pixel display area; The fifth, sixth, and seventh excavated holes are etched simultaneously. At the location of the fifth excavated hole, after etching the passivation layer, the gate insulating layer is etched downward until the third CK signal line is exposed. At the location of the sixth excavated hole, after etching the passivation layer, the gate insulating layer is etched downward until the fourth CK signal line is exposed. At the location of the seventh excavated hole, after etching the passivation layer, the outer metal layer of the drain is etched downward. S6. Plate a conductive layer, a third signal connection line, a fourth signal connection line, and a pixel electrode on the upper surface of the passivation layer, wherein the conductive layer is located directly above the drain electrode. The conductive layer is divided into a first row of conductive layers and a second row of conductive layers. The first row of conductive layers is connected to the right end of the third signal connection line, and the left end of the third signal connection line passes through the fifth hole and is connected to the third CK signal line. The second row of conductive layers is connected to the right end of the fourth signal connection line, and the left end of the fourth signal connection line passes through the sixth hole and is connected to the fourth CK signal line. The lead of the pixel electrode passes through the seventh hole and is connected to the drain electrode.

9. The method for manufacturing an array substrate for reducing feedthrough voltage according to claim 8, wherein: The following steps are also included: In the step S4, the second metal layer further forms TP traces distributed at intervals; S7, coating an outer insulating layer on the upper surfaces of the pixel electrode, the conductive layer, and the passivation layer, wherein an eighth hole is formed in the outer insulating layer within the pixel display area, the eighth hole penetrating the passivation layer, and the TP trace is exposed through the eighth hole; S8. Plating a common electrode on the upper surface of the outer insulating layer, and connecting the lead of the common electrode through the eighth hole to the TP line.

10. The method for manufacturing an array substrate for reducing feedthrough voltage according to claim 9, wherein: In S5, the etching method of the fifth hole, the sixth hole and the seventh hole is replaced by: first, the fifth hole, the sixth hole and the seventh hole are etched in the passivation layer at the same time until the fifth hole and the sixth hole expose the gate insulation layer and the seventh hole exposes the drain, then the etching of the seventh hole is stopped, and then the etching of the fifth hole and the sixth hole is continued at the same time until the third CK signal line is exposed in the fifth hole and the fourth CK signal line is exposed in the sixth hole.

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