A power transistor

Abstract

The application relates to a power transistor, comprising an insulating substrate; an insulating dielectric layer with an opening above the insulating substrate; a first semiconductor layer formed by epitaxial growth from the dielectric layer opening area; a channel buffer layer above the first semiconductor layer; a barrier layer above the channel buffer layer; a gate, a source and a drain above the barrier layer; wherein a part of the first semiconductor layer below the source is doped to form a conductive field plate, the field plate is coupled to the source through an electrical connection structure, and the side edge of the field plate is between the gate side edge adjacent to the same side and the drain side edge adjacent to the same side. The application also provides related electronic devices and a method for preparing the power transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a power transistor comprising an insulating substrate. BACKGROUND

[0002] III-V semiconductors such as GaN power circuits have great potential to replace silicon power circuits due to their high frequency, low resistance, and low capacitance characteristics. The commercialization of GaN devices has been preliminarily verified and is entering a rapid growth stage. Currently, many GaN power device processes use conductive (111) silicon as a substrate material. This is mainly because silicon-based GaN is lower in cost than SiC-based GaN, and better in heat dissipation characteristics than sapphire-based GaN, which is a compromise between price and performance.

[0003] However, silicon-based GaN has many problems. First, the lattice mismatch between the silicon substrate and the GaN epitaxial layer in silicon-based GaN reaches 16%, which is greater than the mismatch with SiC and sapphire. This results in a larger defect density in silicon-based GaN, which affects device performance. Second, the thermal mismatch rate of Si and GaN is also the highest among the three, reaching 60%. This can cause non-uniformity in the growth of silicon-based GaN. Finally, there is a conductive path between the conductive silicon substrate and the crystalline layer AlN or buffer layer, which can cause the breakdown voltage of silicon-based epitaxy to be lower than the other two (under the same buffer layer thickness).

[0004] In order to alleviate the above problems in Si-based GaN, the following methods are commonly used.

[0005] For lattice mismatch: use buffer layer epitaxial material matching optimization to reduce the defect density of the epitaxial layer, but the effect is limited; use selective epitaxy or lateral epitaxy (Epitaxy lateral overgrowth), that is, by blocking part of the substrate area with a dielectric mask, the epitaxial defect growth is turned around and does not reach the top of the epitaxial layer.

[0006] For thermal mismatch: use a combination of different materials (AlN / AlGaN / GaN or superlattice, etc.) to optimize the compression stress, tensile stress cycle during growth, and to alleviate the wafer warping caused by thermal adaptation; replace a large part of the Si substrate, such as using a ceramic substrate with a similar thermal expansion coefficient to GaN.

[0007] For substrate leakage or breakdown voltage reduction: increase the thickness of the buffer layer, but this will increase the cost and risk of increasing defects; remove the Si substrate in the drain part.

[0008] It can be seen that there are many technical difficulties in silicon-based GaN. A major technical obstacle in realizing power devices by using sapphire-based GaN epitaxy is that sapphire is an insulating substrate, and the back surface of the device lacks grounding function, which leads to the problem of dynamic resistance (Dynamic Ron) or current collapse of sapphire-based GaN devices.

[0009] Figure 1 The figure shows the schematic diagram of the current of the power device changing with the voltage. As shown in the figure, R DS_on is the on-resistance of the existing power device in static state, R' DS_on is the on-resistance of the existing power device under stress in dynamic state, which is greater than R DS_on . Due to the influence of high-voltage electric field on the distribution of electrons, the off-state voltage stress of the power device will cause the on-state resistance of the device to increase, which can be several times or more. Therefore, the existing power device has too large dynamic resistance under high-frequency working state, and thus is not suitable for power circuits that need to work under high-frequency state. SUMMARY

[0010] In view of the technical problems existing in the prior art, the present application provides a power transistor, which comprises an insulating substrate; an insulating medium layer with an opening located above the insulating substrate; a first semiconductor layer formed by epitaxial growth from the medium layer opening area; a channel buffer layer located above the first semiconductor layer; a barrier layer located above the channel buffer layer; a gate, a source and a drain located above the barrier layer; wherein a part of the first semiconductor layer located below the source is doped to form a conductive field plate, the field plate is coupled to the source through an electrical connection structure, and the side edge of the field plate is located between the gate side edge adjacent to the same side and the drain side edge adjacent to the same side.

[0011] In particular, the straight line distance between the side edge of the field plate and the point closest to the side edge of the drain adjacent to the same side is less than or equal to the straight line distance between the side edge of the drain adjacent to the same side and the side edge of the gate adjacent to the same side.

[0012] In particular, the side edge of the field plate is located at the middle position between the side edge of the drain adjacent to the same side and the side edge of the gate adjacent to the same side.

[0013] In particular, the distance between the side edge of the field plate and the vertical edge of the drain adjacent to the same side is greater than the thickness of the channel buffer layer.

[0014] In particular, the power transistor further comprises an isolation structure located below the drain and between the drain and the insulating medium layer.

[0015] In particular, the isolation structure comprises a metallic material or an insulating dielectric material, and / or the isolation structure comprises a solid or hollow structure.

[0016] In particular, the power transistor further comprises a seed layer above the insulating substrate and a base buffer layer above the seed layer; wherein the insulating dielectric layer is above the base buffer layer.

[0017] In particular, the power transistor further comprises a diffusion barrier layer around the field plate, and the channel buffer layer is above the upper surface of the diffusion barrier layer.

[0018] In particular, the insulating substrate comprises at least one of SiC, Al2O3, GaN, diamond material.

[0019] In particular, the first semiconductor layer and / or the channel buffer layer comprises GaN or AlGaN or AlN.

[0020] In particular, the field plate has a doping concentration of at least 10 17 .

[0021] In particular, an AlN layer is further included between the channel buffer layer or the base buffer layer.

[0022] The application also provides an electronic device comprising the power transistor as claimed in any one of the preceding claims.

[0023] The application also provides a method for manufacturing a power transistor, comprising: forming an insulating dielectric layer above an insulating substrate; patterning the insulating dielectric layer to form a plurality of openings; epitaxially growing a first semiconductor layer in the opening regions and simultaneously doping the first semiconductor layer to form a conductive field plate; stopping the doping of the first semiconductor layer before the epitaxially grown first semiconductor layers in adjacent opening regions are connected to each other; epitaxially growing a channel buffer layer on the first semiconductor layer; forming a barrier layer above the channel buffer layer; forming a conductive structure above the conductive field plate, the conductive structure penetrating through the barrier layer and the channel buffer layer and being electrically connected to the conductive field plate; forming a source, a drain and a gate above the barrier layer, wherein the source is electrically connected to the corresponding conductive structure.

[0024] In particular, the method further comprises, after forming the conductive field plate, forming a diffusion barrier layer around the conductive field plate and continuing epitaxial growth to form an undoped first semiconductor layer between adjacent conductive field plates.

[0025] In particular, the method further comprises forming a seed layer over the insulating substrate before forming the insulating dielectric layer; forming a base buffer layer over the seed layer; and forming the insulating dielectric layer over the base buffer layer.

[0026] In particular, the method further comprises forming an isolation structure over the first semiconductor layer between adjacent field plates, the isolation structure penetrating through the barrier layer and the channel buffer layer and contacting the insulating dielectric layer; and forming the drain over the isolation structure.

[0027] In particular, a straight line distance between a closest point between a side edge of the insulating field plate and a side edge of a drain adjacent to the side edge of the insulating field plate is less than or equal to a straight line distance between the drain adjacent to the side edge of the insulating field plate and a gate adjacent to the drain. BRIEF DESCRIPTION OF DRAWINGS

[0028] Hereinafter, preferred embodiments of the present application will be described in detail with reference to the accompanying drawings. In the following description, same drawing reference numerals are used for same elements even in different drawings.

[0029] Figure 1 A performance diagram of a conventional power transistor on an insulating substrate is shown;

[0030] Figure 2 A structure diagram of a power device according to an embodiment of the present application is shown;

[0031] Figure 3 A structure diagram of a power transistor according to another embodiment of the present application is shown;

[0032] Figure 4 A structure diagram of a power transistor according to an embodiment of the present application is shown;

[0033] Figure 5 A-C show structure diagrams of a power transistor according to different embodiments of the present application;

[0034] Figure 6 A structure diagram of a power transistor according to yet another embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0036] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description, illustrating certain embodiments of the present application. In the drawings, similar symbols

[0037] To solve the problem of excessive dynamic resistance of power devices on insulating substrates as introduced above, the present application provides the following power transistor structure.

[0038] Figure 2 Fig. 1 shows a schematic diagram of a power device structure according to an embodiment of the present application.

[0039] According to an embodiment, the power device can include a substrate 200, which can be an insulating or semi-insulating substrate such as sapphire, diamond, SiC, GaN, Ga2O3, AlN, Al2O3, etc.

[0040] According to an embodiment, the power device can further include an insulating dielectric layer 210 such as SiN or SiO2 above the substrate 200.

[0041] According to an embodiment, the dielectric layer 210 can include a plurality of openings, and the power device can further include a III-V semiconductor layer 220 such as GaN or AlGaN or AlN epitaxially grown in the regions with openings. The following description will take GaN as an example.

[0042] According to different embodiments, the GaN layer 220 corresponding to the opening regions of the dielectric layer and its adjacent parts can be heavily doped as N-type or P-type to form conductive field plates. And the doping concentration is relatively high, for example, 10 17 The above. According to an embodiment, the regions between adjacent conductive field plates through undoped GaN are electrically isolated from each other.

[0043] Optionally, according to one embodiment, the power device can further include a diffusion barrier layer 230 around the conductive field plate. The diffusion barrier layer 230 can be made of, for example, AlN, SiC, etc. The thickness of the diffusion barrier layer 230 can be in the range of a few nanometers to a few hundred nanometers, depending on the application. The diffusion barrier layer 230 can be used to prevent the diffusion of impurities from the conductive field plate into the subsequently grown epitaxial material. The presence of unintentionally doped impurities in the GaN layer 220, except in the field plate region, can directly affect the breakdown voltage of the power device. Therefore, the diffusion barrier layer 230 around the conductive field plate can effectively prevent the problem caused by the unintentionally doped impurities. In addition, the diffusion barrier layer 230 above the conductive field plate can help to expand the critical thickness of the channel buffer layer 240.

[0044] According to one embodiment, the power device can further include a channel buffer layer 240, for example, an epitaxially grown intrinsic GaN layer, above the GaN layer 220. According to one embodiment, an AlN layer (not shown) can be provided in the middle of the channel buffer layer 240 to increase the thickness of the channel buffer layer 240.

[0045] According to one embodiment, the power device can further include a barrier layer 250 above the channel buffer layer 240.

[0046] According to one embodiment, a gate (G), a source (S), and a drain (D) can be provided on the barrier layer 250. The heterojunction interface between the channel buffer layer 240 and the barrier layer 250 forms an electron potential well, in which a two-dimensional electron gas is formed, thereby forming a conductive channel between the buffer layer and the barrier layer, which directs the migration of electrons from the source to the drain.

[0047] According to one embodiment, the source of the power device is electrically connected to the conductive field plate in the corresponding GaN layer 220 below the source. For example Figure 2 As shown, an electrical connection structure 260 is provided below the source, which penetrates the barrier layer 250 and the channel buffer layer 240, and directly contacts the conductive field plate below the source. According to one embodiment, the source can or can not be aligned with the corresponding opening of the insulating medium layer 210, as long as the source is electrically connected to the conductive field plate through the electrical connection structure 260. Through such a structure, a voltage can be applied to the field plate. Therefore, the field plate with the same potential as the source can disperse the electric field between the adjacent drain and gate, thereby reducing the dynamic resistance of the power transistor. At the same time, the distance between the field plate and the adjacent drain also needs to meet certain restrictions to reduce the leakage current and prevent the breakdown voltage of the power transistor from being pulled down.

[0048] Figure 3 As shown is a schematic diagram of a power transistor structure according to another embodiment of the present application. It is similar to the structure shown inFigure 2 The power device shown differs in that it includes a seed layer 302 above the substrate 300, which can include AlN.

[0049] According to one embodiment, the power device can also include a base buffer layer 304 above the seed layer 302, which can include, for example, GaN, AlGaN, AlN. An insulating dielectric layer 310 is formed above the base buffer layer 304. According to one embodiment, an AlN layer (not shown) can be included in the middle of the base buffer layer 304 to increase the thickness of the base buffer layer 304.

[0050] Figure 3 The power device shown has the benefit of providing lower leakage current and higher breakdown voltage.

[0051] Figure 4 A structure diagram of a power transistor according to one embodiment of the present application is shown. The gate s is electrically connected to the field plate 4201 through the electrical connection structure 460 that penetrates the barrier layer 450 and the channel buffer layer 440.

[0052] As shown, AA', BB', CC' are the side edges of the gate s that are adjacent to the same side of the field plate 4201 (BB') and the same side of the drain D (CC'), respectively. According to one embodiment, in order to disperse the electric field between the drain and the gate to reduce the dynamic resistance, the edge BB' of the field plate can be placed between AA' and CC', for example, at the middle between AA' and CC'. At the same time, the edge BB' of the field plate cannot be too close to the edge CC' of the drain, because too close a distance will reduce the breakdown voltage between the gate and the drain.

[0053] According to one embodiment, for example, the thickness T of the channel epitaxial layer 440 above the field plate can be 1-5 microns, and the distance between AA' and CC' can be 5-20 microns (for example, for a 650V GaN device). The distance between BB' and CC' is greater than the distance T, and the length of the field plate can be 0.1-200 microns, for example, 20 microns. According to one embodiment, the distance between the plates can be the sum of the length of the drain and twice the distance between BB' and CC'.

[0054] According to one embodiment, Figure 4D is the point on the edge of the field plate closest to the drain on the same side, E is the point on the edge of the drain closest to the field plate, F is the point on the edge of the source closest to the drain on the same side, the straight line distance between EF should be less than the distance between AA' and CC', and under this precondition, the straight line distance between EF should be as large as possible. Of course, the specific value needs to be designed according to the electric field distribution, involves the specific parameters of the structure and material combination of the device, and is related to the gate-drain bias under different working conditions.

[0055] Figure 5 A-C show partial structure diagrams of power transistors according to different embodiments of the present application. According to different embodiments, the shape of the conductive field plate can be controlled by controlling the parameters of epitaxial growth. Figure 5 A shows a conductive field plate with a substantially rectangular side cross section, Figure 5 B shows a conductive field plate with a substantially trapezoidal side cross section, Figure 5 C shows a conductive field plate with a substantially triangular side cross section. Regardless of the shape of the conductive field plate generated by epitaxy, the edge thereof needs to satisfy the positional relationship with the adjacent gate and drain as described above. To some extent, the shape of the edge of the field plate with a triangular or trapezoidal side interface close to the edge of the drain is a hypotenuse, which is more likely to satisfy the requirement of the distance between the side edge of the adjacent field plate, the side edge of the drain and the side edge of the gate on the same side.

[0056] Figure 6 A power transistor structure diagram according to still another embodiment of the present application is shown. In the power transistor, an isolation structure 670 of the epitaxial layer of the tunnel barrier layer 650 and the channel buffer layer 640 can be included below the drain. Further, the isolation structure 670 can be in contact with the conductive field plate in the GaN layer 620, for example. The isolation structure 670 can include a metal or an insulating dielectric material, and can be a solid structure or a hollow structure. The isolation structure 670 can remove the high defect density area at the lateral junction of the non-conductive field plate part of the GaN layer 620 selected for epitaxy, so as to avoid the adverse effects thereof.

[0057] According to one embodiment of the present application, a method for preparing a power device is also provided, which comprises

[0058] Optionally, a seed layer is formed on the insulating substrate.

[0059] Optionally, a base buffer layer is formed on the seed layer.

[0060] An insulating dielectric layer is formed above the insulating substrate (directly or on the base buffer layer). According to one embodiment, the dielectric layer can be completed in-situ after the growth of the base buffer layer in the same vacuum environment, or can be completed in two steps ex-situ by another process.

[0061] The insulating dielectric layer is patterned to form a plurality of opening regions.

[0062] An epitaxial growth is performed in the opening regions to form a first semiconductor layer, and a re-doping is performed on the first semiconductor layer while forming the first semiconductor layer in the opening regions and in the vicinity of the opening regions to form a conductive field plate, for example, with a doping concentration reaching 1018cm-3. 17 According to one embodiment, the epitaxial growth described above can be a selective area growth (SAG), i.e. the epitaxial growth of the first semiconductor layer only occurs in the opening regions not covered by the insulating dielectric layer, while no epitaxial growth occurs in the regions covered by the insulating dielectric layer. According to one embodiment, when the epitaxial growth of the first semiconductor layer in the opening regions exceeds the opening regions, a lateral overgrowth can be controlled by the process to cover at least part of the insulating dielectric layer. According to one embodiment, the doping needs to be stopped before the first semiconductor layers epitaxially grown in the adjacent opening regions merge together, i.e. the length of the re-doped region or field plate needs to be controlled. According to one embodiment, the first semiconductor layer can include GaN or other III-V semiconductor.

[0063] Optionally, a diffusion barrier layer is formed around the conductive field plate.

[0064] After the doping is finished, the epitaxial growth based on the opening regions is continued to join the first semiconductor layers to each other. It can be seen that the first semiconductor layers between the conductive field plates are undoped intrinsic semiconductor.

[0065] A channel buffer layer is grown over the first semiconductor layer, wherein the first semiconductor layer and the channel buffer layer can include the same III-V semiconductor material, and the channel buffer layer is an intrinsic semiconductor layer.

[0066] A barrier layer is formed on the channel buffer layer, and optionally a top GaN layer can also be formed on the barrier layer.

[0067] An electrical connection structure is formed through the barrier layer, the channel buffer layer and coupled or electrically connected to the field plate, which can include a conductive material, such as metal. According to one embodiment, the electrical connection structure can be achieved by an etching process, in some cases the etching can not be able to stop exactly at the interface between the channel buffer layer and the field plate, thus allowing the electrical connection structure to moderately penetrate into the field plate.

[0068] Optionally, an isolation structure is formed through the barrier layer, the channel buffer layer and in contact with the insulating dielectric layer, which can include a conductive or insulating material, and can include a solid or hollow structure.

[0069] A gate, a source and a drain are formed on the barrier layer, the source is coupled to the electrical connection structure by metallization, and the drain can be in contact with the isolation structure.

[0070] The power transistor disclosed in the present application can solve the problem of dynamic resistance of GaN devices on insulating substrates due to the lack of conductive substrates. Thus, the application of insulating substrate GaN in power devices can be developed, and various difficulties faced in Si-based GaN can be avoided. Even if a substrate material with both insulating and conductive types, such as SiC, is used, the structure can be used to achieve a similar breakdown voltage level on an insulating substrate with a thinner channel buffer layer than required for a similar conductive substrate, thereby reducing the cost of the product.

[0071] The above examples are only used to illustrate the present application, and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions shall belong to the scope disclosed in the present application.

Claims

1. A power transistor, comprising: Insulating substrate; An insulating dielectric layer with an opening located above the insulating substrate; A first semiconductor layer is epitaxially grown from the opening region of the dielectric layer; A channel buffer layer located above the first semiconductor layer; A barrier layer located above the channel buffer layer; as well as The gate, source, and drain are located above the barrier layer; A portion of the first semiconductor layer located below the source electrode is doped to form a conductive field plate. The field plate is coupled to the source electrode through an electrical connection structure, and the side edge of the field plate is located between the adjacent gate side edge and the adjacent drain side edge on the same side.

2. The power transistor of claim 1, wherein the straight-line distance between the nearest point between the side edge of the field plate and the adjacent drain side edge on the same side is less than or equal to the straight-line distance between the adjacent drain side edge on the same side and the adjacent gate side edge on the same side.

3. The power transistor of claim 2, wherein the side edge of the field plate is located at the midline position between the adjacent drain side edge and the adjacent gate side edge on the same side.

4. The power transistor of claim 1, wherein the distance between the field plate side edge along the vertical long line and the adjacent drain side edge along the vertical long line is greater than the thickness of the channel buffer layer.

5. The power transistor of claim 1 or 2, further comprising an isolation structure located below the drain and between the drain and the insulating dielectric layer.

6. The power transistor of claim 5, wherein the isolation structure comprises a metallic material or an insulating dielectric material, and / or the isolation structure comprises a solid or hollow structure.

7. The power transistor of claim 1, further comprising a seed layer above the insulating substrate and a base buffer layer above the seed layer; wherein the insulating dielectric layer is located above the base buffer layer.

8. The power transistor of claim 1, further comprising a diffusion barrier layer located around the field plate, the channel buffer layer being located above the upper surface of the diffusion barrier layer.

9. The power transistor of claim 1, wherein the insulating substrate comprises at least one of SiC, Al2O3, GaN, and diamond.

10. The power transistor of claim 1, wherein the first semiconductor layer and / or the channel buffer layer comprises GaN, AlGaN, or AlN.

11. The power transistor of claim 1, wherein the doping concentration of the field plate is at least 10. 17 .

12. The power transistor of claim 1, wherein an AlN layer is further included in the middle of the channel buffer layer.

13. The power transistor of claim 7, wherein an AlN layer is further included in the middle of the base buffer layer.

14. An electronic device comprising a power transistor as described in any one of claims 1-13.

15. A method for fabricating a power transistor, comprising: An insulating dielectric layer is formed above an insulating substrate; The insulating dielectric layer is patterned to form multiple openings; An epitaxial growth of a first semiconductor layer is performed in the opening region, and the first semiconductor layer is simultaneously doped to form a conductive field plate. Doping of the first semiconductor layer is stopped before the first semiconductor layers epitaxially grown in adjacent opening regions are connected to each other. A channel buffer layer is epitaxially grown on the first semiconductor layer; A barrier layer is formed above the channel buffer layer; A conductive structure is formed above the conductive field plate, penetrating the barrier layer and the channel buffer layer and electrically connected to the conductive field plate; A source, a drain, and a gate are formed above the barrier layer, wherein the source is electrically connected to a corresponding conductive structure.

16. The method of claim 15, further comprising: After the conductive field plate is formed, a diffusion barrier layer is formed around the conductive field plate, and epitaxy continues to form an undoped first semiconductor layer between adjacent conductive field plates.

17. The method of claim 15, further comprising: Before forming the insulating dielectric layer, a seed layer is formed above the insulating substrate; A basic buffer layer is formed above the seed crystal layer; The insulating dielectric layer is formed on top of the base buffer layer.

18. The method of claim 15, further comprising: An isolation structure is formed above the first semiconductor layer between adjacent conductive field plates, penetrating the barrier layer and the channel buffer layer and contacting the insulating dielectric layer; The drain electrode is formed above the isolation structure.

19. The method of claim 15, wherein the straight-line distance between the nearest point between the side edge of the conductive field plate and the side edge of the adjacent drain on the same side is less than or equal to the straight-line distance between the side edges of the adjacent drain on the same side and the adjacent gate on the same side.

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