A self-calibration method applied to a Fibonacci capacitor array

Abstract

The present invention relates to a self-calibration method applied to a Fibonacci capacitor array. The method includes: arranging the main DAC capacitor array in a layout with the ratio arrangement of the Fibonacci sequence; quantifying the error voltage of the main DAC capacitor array, and using the obtained digitized error voltage as a non-linear calibration term; and storing the non-linear calibration term in a data register; when performing self-calibration on the main DAC capacitor array, obtaining the non-linear calibration term from the data register, loading it into the calibration DAC, and then compensating it back to the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array, completing the self-calibration of the main DAC capacitor array. This method can reduce the capacitance mismatch error caused by the parasitic capacitance and the process manufacturing error, and greatly correct the error caused by the mismatch between adjacent capacitors in the capacitor array.

Description

Technical Field

[0001] The present invention relates to a self - calibration method applied to a Fibonacci capacitor array, belonging to the technical field of integrated circuits. Background Art

[0002] As a bridge connecting analog signals and digital signals, analog - to - digital converters have developed rapidly in the field of integrated circuits and the information industry. The charge - redistribution successive - approximation register analog - to - digital converter (SAR ADC for short, with the English meaning of successive approximation register Analog - to - Digital Converter) has been widely used due to its comprehensive advantages of medium conversion speed, low power consumption, and low cost. Generally, in terms of structure, a SAR ADC is composed of a gate - voltage bootstrap, a digital - to - analog converter (DAC), a comparator, digital logic control, and other related analog circuits.

[0003] The Fibonacci sequence is a sequence of natural numbers, but its general term formula is expressed by irrational numbers. Moreover, when the number of terms tends to infinity, the ratio of the previous term to the next term gets closer and closer to the golden ratio (or the decimal part of the ratio of the next term to the previous term gets closer and closer to 0.618).

[0004] As one of the key units of a charge - redistribution SAR ADC, the accuracy of the DAC using a Fibonacci capacitor array directly determines the accuracy of the entire digital - to - analog converter. Under actual process manufacturing, due to the parasitic resistors, parasitic capacitors generated by various devices and layout wiring, as well as the inevitable errors in the process, the proportional relationship between adjacent capacitors of the DAC does not satisfy the golden ratio of the Fibonacci sequence, greatly reducing the overall accuracy of the ADC.

[0005] The weights of the high - order capacitors in a binary capacitor array are all the sum of the weights of all the subsequent low - order capacitors, while the weights of the high - order capacitors using non - binary capacitor weights are lower than the sum of the weights of all the subsequent low - order capacitors, that is, it has a weight redundancy compensation technology, indicating that if an error occurs in the determination of the first digital code, the previous misoperation can be corrected in the subsequent comparison and conversion, and the correct output result can still be obtained, with more redundancy, and can cope with larger mismatch situations. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the present invention provides a self - calibration method applied to a Fibonacci capacitor array, which can perform self - calibration on the capacitor array, reduce the capacitance mismatch error caused by parasitic capacitance and process manufacturing errors, and greatly correct the error caused by the mismatch of adjacent capacitors in the capacitor array.

[0007] Term Explanation:

[0008] 1. Error voltage: The difference between the voltage value obtained on the upper plate of the capacitor and the ideal voltage value.

[0009] 2. Residual voltage: The voltage value obtained on the upper plate of the capacitor.

[0010] The technical solution of the present invention is as follows:

[0011] A self - calibration method applied to a Fibonacci capacitor array, the self - calibration method includes:

[0012] The main DAC capacitor array is arranged in a layout with the ratio of the Fibonacci sequence; the error voltage of each capacitor in the main DAC capacitor array is quantified to obtain a digital error voltage and a residual voltage, and the digital error voltage is stored in the data register as a non - linear calibration term;

[0013] When self - calibrating the main DAC capacitor array, the non - linear calibration term is obtained from the data register and loaded into the calibration DAC, and then fed back to the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array, completing the self - calibration of the main DAC capacitor array.

[0014] The principle of self - calibration is to subtract the error voltage V o from the output voltage V, precisely eliminating the non - linearity caused by capacitor mismatch. The digital control circuit controls the capacitor switches during the calibration period and stores the non - linear correction term in the data register. When measuring, the data is taken out and fed back through the calibration DAC to the C o,error capacitor, that is, subtracting this voltage from the output voltage of the main DAC to complete the elimination of the error voltage. add On the capacitor, that is, subtracting this voltage from the output voltage of the main DAC to complete the elimination of the error voltage.

[0015] According to the preference of the present invention, the expression of the error voltage V o,error is as follows:

[0016] Assume that under an N - bit weighted DAC, considering the changes caused by process errors, the capacitance value C n of each bit weight satisfies: C n = F n *C*(1 + ε n ), n = 1, 2, 3,..., N; F n is the general term formula of the Fibonacci sequence, ε n represents the capacitance value deviation of the n - th capacitor, and C represents the unit capacitor;

[0017] Then the unit capacitor composed of the capacitor array

[0018] To obtain the accurate unit capacitance C, we can derive from the above formula The purpose is to ensure that the ratio of the capacitance value of the entire capacitor array to the number of capacitors is the capacitance of a unit capacitor, so that the capacitance deviation can be eliminated through calibration. Therefore, in the design, the terms other than C in the right equation can be designed to be 0;

[0019] The main DAC capacitor array includes a capacitor array composed of N-bit capacitors. The lower plate of each capacitor is connected to V ref phase, and the upper plate is used as the output voltage V o , then the output voltage V o and the corresponding digital input code D i The relationship is:

[0020]

[0021] D i is used to offset the process error of the i-th capacitor C i , D i represents the binary digital input code. For example, for a full-scale voltage of 15V, when the input D i =0000, the output is 0V; when the input D i =1100, the output is 12V.

[0022] Under the ideal DAC, that is, when the capacitance value of the unit capacitor has no deviation, assuming ε i =0, then we get

[0023] V o,ideal represents the output voltage without capacitance deviation;

[0024] Therefore,

[0025] The error voltage caused by the N-th capacitor Then the error voltage

[0026] represents the error voltage caused by the i-th capacitor.

[0027] According to the preference of the present invention, when quantifying the error voltage, starting from the lowest-bit capacitor, it is carried out in ascending order. The specific process is as follows:

[0028] Step 1: Connect the upper plate of the capacitor array to GND, switch the lower plate of the lowest-bit capacitor C1 to V ref , connect the lower plates of the remaining capacitors to GND. At this time, the sampled charge Q1 on the capacitor array is:

[0029] Q1 = -V ref F1(1 + ε1)C;

[0030] Step 2: Start calibration from the second lowest capacitor C2. Disconnect the upper plate of the Fibonacci capacitor array from GND, and define the potential of the upper plate as V n , connect the lower plate of the second lowest capacitor to V ref , connect the lower plates of capacitors other than the second lowest capacitor to GND. At this time, the sampled charge Q2 on the capacitor array, and according to the Fibonacci sequence F2 = F1 = 1, it can be obtained that: Q2 = V ref (ε2 - ε1)C,

[0031] At this time,

[0032] C total represents the capacitance value of the total capacitance of the capacitor array, V2 represents the output voltage value of the upper plate when calibrating from the second lowest capacitor C2; V3 represents the output voltage value of the upper plate when calibrating from the lowest capacitor C3; V N represents the output voltage value of the upper plate when calibrating the Nth capacitor; V ε1 represents the error voltage caused by the lowest capacitor; V ε2 represents the error voltage caused by the second lowest capacitor;

[0033] Similarly, equations (I)-(III) can be obtained:

[0034]

[0035]

[0036]

[0037] Use the error voltage caused by the Nth capacitor to represent V i , V i represents the output voltage value of the upper plate when calibrating the ith capacitor; equations (IV)-(VII) can be obtained:

[0038]

[0039]

[0040]

[0041]

[0042] Specifically, for the ideal error in the capacitor array, that is, adding all the errors as much as possible to minimize, then it satisfies:

[0043]

[0044] Thus,

[0045]

[0046]

[0047]

[0048]

[0049] Extrapolating to the Nth digit, we get:

[0050] wherein, S N = 2F N + F N-1 - 1;

[0051]

[0052] and n ≥ 3;

[0053] Thus, the error voltage and the relationship between the remaining voltage V i are obtained. If the error voltage of the ith capacitor is required, at this time, the remaining voltage V n is the voltage value obtained at the upper plate of the capacitor when the lower plate of the ith capacitor is connected to Verf and the lower plates of all capacitors except the ith capacitor are grounded. After digitizing all the error voltages, they are stored in the data register and then converted into an analog voltage by the calibration DAC and compensated into the main DAC capacitor array.

[0054] According to the preferred embodiment of the present invention, the calibration period of the self - calibration method starts from the non - linearity caused by the lowest - order capacitor C1 in the measured capacitor array and is realized by the successive conversion of sampling the reference voltage V ref for all capacitors except the lowest - order capacitor. Specifically:

[0055] Adopt the conversion method from the lower - order capacitor to the higher - order capacitor.

[0056] When converting the lower - order capacitor, load the calibration code of the lower - order capacitor into the calibration DAC, and then back - compensate it into the main DAC capacitor array so that the analog signal generated at the output end of the calibration DAC cancels the error voltage generated by the main DAC capacitor array.

[0057] When converting the second - lowest - order capacitor, keep the DAC state after the lower - order conversion is completed; and so on to the highest - order capacitor until the conversion period ends.

[0058] A self - calibration device applied to a Fibonacci capacitor array. The self - calibration device includes a main DAC capacitor array, a voltage comparator, a digital control circuit, a data register, and a calibration DAC. The output of the main DAC capacitor array is connected to the input terminal of the voltage comparator, and the voltage comparator is used to determine the magnitude of the output voltage of the upper plate of the main DAC capacitor array.

[0059] The digital control circuit is used to control the switching sequence of the lower - plate switches of the main DAC capacitor array and control the enable in the data register. The data register is used to store non - linear calibration terms, that is, digital codes. When calibrating the main DAC capacitor array, the calibration terms are passed to the calibration DAC. The calibration DAC is used to convert the non - linear calibration terms into analog voltage values when calibrating the main DAC capacitor array. The analog voltage values are used as compensation voltages and fed back to the main DAC capacitor array.

[0060] The beneficial effects of the present invention are as follows:

[0061] The improvement of the accuracy of successive - approximation ADCs is mainly limited by the parasitics and mismatches caused by the too - large area of DAC capacitors and the parasitics of the traces. Using the DAC capacitor array structure of the Fibonacci sequence can improve the influence of parasitics and mismatches. The present invention proposes a self - calibration method applied to a Fibonacci capacitor array. By means of compensation voltages, the problem of the proportional imbalance caused by the mismatch of adjacent - bit capacitors is greatly corrected, effectively improving the accuracy. Description of the Drawings

[0062] Figure 1 is a schematic diagram of a self - calibration method applied to a Fibonacci capacitor array;

[0063] Figure 2 is a schematic diagram of obtaining the output terminal of the capacitor array of the present invention;

[0064] Figure 3 is a schematic diagram of sampling the lowest - order capacitor of the capacitor array of the present invention;

[0065] Figure 4 is a schematic diagram of sampling the N - th - order capacitor of the capacitor array of the present invention;

[0066] Figure 5 is a schematic diagram of the overall structure of the self - calibration device applied to a Fibonacci capacitor array provided by the present invention. Detailed Embodiments

[0067] The present invention will be further described below in conjunction with embodiments and the accompanying drawings of the specification, but not limited thereto.

[0068] Embodiment 1

[0069] A self - calibration method applied to a Fibonacci capacitor array, as Figure 1As shown, the self - calibration method includes:

[0070] (1) Design the main DAC module: The main DAC capacitor array is arranged in a layout with the ratio of the Fibonacci sequence; that is, the main DAC capacitor array is arranged in a layout with the ratio of the Fibonacci sequence.

[0071] (2) Design the calibration module: Quantify the error voltage of each capacitor in the main DAC capacitor array to obtain the digitized error voltage and the remaining voltage. The digitized error voltage is used as the non - linear calibration term; and store the non - linear calibration term in the data register;

[0072] Set under an N - bit weighted DAC, considering the changes caused by process errors, the capacitance value C of each bit weight n satisfies: C n = F n *C*(1 + ε n ), n = 1, 2, 3, …, N; F n is the general term formula of the Fibonacci sequence, ε n represents the capacitance value deviation of the nth capacitor, and C represents the unit capacitance;

[0073] Then the unit capacitance composed of the capacitor array

[0074] In order to obtain an accurate unit capacitance C, we can get from the above formula The purpose is to ensure that the ratio of the capacitance value to the number of capacitors in the entire capacitor array is the capacitance of a unit capacitor, so that the capacitance deviation can be eliminated through calibration. Therefore, in the design, the terms other than C on the right - hand side of the equation can be designed to be 0;

[0075] Such as Figure 2 shown, the main DAC capacitor array includes a capacitor array composed of N - bit capacitors. The lower plate of each capacitor is connected to V ref , and the upper plate is used as the output voltage V o . Then the output voltage V o and the corresponding digital input code D i The relationship is:

[0076]

[0077] D i is used to offset the process error of the ith capacitor C i . D i represents the binary digital input code. For example, for a full - scale voltage of 15V, when the input D i = 0000, the output is 0V; when the input D i = 1100, the output is 12V.

[0078] In an ideal DAC, that is, when the capacitance values of the unit capacitors have no deviation, assuming ε i = 0, then we get

[0079] V o,ideal which represents the output voltage in the case of no capacitance deviation;

[0080] Therefore,

[0081] the error voltage caused by the Nth capacitor then the error voltage represents the error voltage caused by the ith capacitor.

[0082] When quantifying the error voltage, starting from the lowest - order capacitor, it is carried out in ascending order. The specific process is as follows:

[0083] Step 1: As Figure 3 shown, connect the upper plate of the capacitor array to GND, switch the lower plate of the lowest - order capacitor C1 to V ref , and connect the lower plates of the remaining capacitors to GND. At this time, the sampled charge Q1 on the capacitor array is:

[0084] Q1 = -V ref F1(1 + ε1)C;

[0085] Step 2: As Figure 4 shown, start calibrating from the second - lowest - order capacitor C2. Disconnect the upper plate of the Fibonacci capacitor array from GND, and define the potential of the upper plate as V n , connect the lower plate of the second - lowest - order capacitor to V ref , and connect the lower plates of the capacitors other than the second - lowest - order capacitor to GND. At this time, the sampled charge Q2 on the capacitor array, and according to the Fibonacci sequence F2 = F1 = 1, we get: Q2 = V ref (ε2 - ε1)C,

[0086] At this time,

[0087] C total represents the capacitance value of the total capacitance of the capacitor array, V2 represents the output voltage value of the upper plate when calibrating from the second - lowest - order capacitor C2; V3 represents the output voltage value of the upper plate when calibrating from the lowest - order capacitor C3; V N represents the output voltage value of the upper plate when calibrating the Nth capacitor, V ε1 represents the error voltage caused by the lowest - order capacitor; V ε2 represents the error voltage caused by the second - lowest - order capacitor;

[0088] Similarly, we can get

[0089]

[0090]

[0091] Use the error voltage caused by the capacitor at the Nth position to represent V i , it can be obtained that:

[0092]

[0093]

[0094]

[0095]

[0096] Specifically, for the ideal error in the capacitor array, that is, adding all the errors as much as possible to minimize, then it satisfies:

[0097]

[0098] Thus, it can be obtained

[0099]

[0100]

[0101]

[0102]

[0103] From this, it is deduced to the Nth position, and it can be obtained that:

[0104] Among them, S N = 2F N + F N-1 - 1;

[0105]

[0106] and n ≥ 3;

[0107] Thus, the relationship between the error voltage and the remaining voltage is obtained. If the error voltage of the capacitor at the ith position is required, at this time, the remaining voltage V n is the voltage value obtained at the upper plate of the capacitor when the lower plate of the ith capacitor is connected to Verf and the lower plates of all capacitors except the ith capacitor are grounded; after digitizing all the error voltages, they are all stored in the data register, and then converted into an analog voltage through the calibration DAC and compensated into the main DAC capacitor array.

[0108] (3) Perform self - calibration: When performing self - calibration on the main DAC capacitor array, obtain the non - linear calibration terms from the data register, load them into the calibration DAC, and then back - compensate them to the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array, completing the self - calibration of the main DAC capacitor array. After the calibration mode ends, the ADC enters the normal conversion mode.

[0109] The principle of self - calibration is to subtract the error voltage V o from the output voltage V o,error , precisely eliminating the non - linearity caused by capacitance mismatch. As shown in Figure 5 , the digital control circuit controls the capacitor switches during the calibration period and stores the non - linear correction terms in the data register. When measuring, the data is retrieved and fed back through the calibration DAC to the C add capacitor, that is, subtracting this voltage from the output voltage of the main DAC to complete the elimination of the error voltage.

[0110] The calibration period of the self - calibration method starts from the non - linearity caused by the lowest - order capacitor C1 in the measured capacitor array, and realizes the successive approximation conversion by sampling the reference voltage V ref for all capacitors except the lowest - order capacitor. Specifically:

[0111] Adopt the method of converting from the lower - order capacitor to the higher - order capacitor.

[0112] When converting the lower - order capacitor, load the calibration code of the lower - order capacitor into the calibration DAC, and then back - compensate it to the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array;

[0113] When converting the second - lowest - order capacitor, keep the DAC state after the lower - order conversion is completed; and so on until the highest - order capacitor, until the conversion period ends.

[0114] Embodiment 2

[0115] A self - calibration device applied to a Fibonacci capacitor array. The self - calibration device includes a main DAC capacitor array, a voltage comparator, a digital control circuit, a data register, and a calibration DAC. The output of the main DAC capacitor array is connected to the input end of the voltage comparator. The voltage comparator is used to determine the magnitude of the output voltage of the upper plate of the main DAC capacitor array. Specifically, the voltage comparator compares the output voltage of the upper plate of the Fibonacci capacitor array with 0. If it is greater than 0, the output result of the comparator is 1; otherwise, the output result is 0.

[0116] The digital control circuit is used to control the switching sequence of the switches on the lower plate of the main DAC capacitor array and control the enable in the data register; the data register is used to store the non-linear calibration items, which are digital codes, and when calibrating the main DAC capacitor array, the calibration items are transmitted to the calibration DAC; the calibration DAC is used to convert the non-linear calibration items into analog voltage values when calibrating the main DAC capacitor array, and the analog voltage values are used as compensation voltages and fed back to the main DAC capacitor array.

Claims

1. A self - calibration method applied to a Fibonacci capacitor array, characterized in that, The self - calibration method includes: The main DAC capacitor array adopts a ratio arrangement layout of the Fibonacci sequence; the error voltage of each capacitor in the main DAC capacitor array is quantized to obtain a digitized error voltage and a residual voltage, and the digitized error voltage is stored in the data register as a non-linear calibration term; wherein, the error voltage represents the error voltage caused by the i-th capacitor, D i is used to cancel the process error of the i-th capacitor C i , D i represents the binary digital input code; when performing error voltage quantization, starting from the lowest-bit capacitor, it is carried out sequentially from low to high, and the specific process is as follows: Step 1: Connect the upper plate of the capacitor array to GND, switch the lower plate of the lowest-order capacitor C1 to V ref , connect the lower plates of the remaining capacitors to GND. At this time, the sampled charge Q1 on the capacitor array is: Q1 = -V ref F1(1 + ε1)C; Step 2: Start calibration from the second lowest capacitor C2. Disconnect the upper plate of the Fibonacci capacitor array from GND, and define the potential of the upper plate as V n , connect the lower plate of the second lowest capacitor to V ref , connect the lower plates of capacitors other than the second lowest capacitor to GND. At this time, sample the charge Q2 on the capacitor array, and according to the Fibonacci sequence F2 = F1 = 1, it can be obtained that: Q2 = V ref (ε2 - ε1)C, At this time, C total represents the capacitance value of the total capacitance of the capacitor array, V2 represents the output voltage value of the upper plate when calibrating the second-lowest capacitor C2; V3 represents the output voltage value of the upper plate when calibrating the lowest capacitor C3; V N represents the output voltage value of the upper plate when calibrating the Nth capacitor; V ε1 represents the error voltage caused by the lowest capacitor; V ε2 represents the error voltage caused by the second-lowest capacitor; Similarly, equations (I) - (III) are obtained: Use the error voltage caused by the capacitor at the Nth bit to represent V i , V i represents the output voltage value of the upper plate during the calibration of the capacitor at the ith bit; the following equations (IV) - (VII) are obtained: Specifically, for the ideal errors in the capacitor array, that is, adding all the errors to minimize them, the following is satisfied: Thus obtained From this, it is extended to N bits to obtain: Among them, S N = 2F N + F N-1 - 1; and n≥3; Thus, an error voltage is obtained and the relationship with the remaining voltage V i is obtained. Then, all the error voltages are digitized and stored in the data register, and then converted into an analog voltage through a calibration DAC and compensated to the main DAC capacitor array; When self - calibrating the main DAC capacitor array, the non - linear calibration term is obtained from the data register and loaded into the calibration DAC, and then back - filled into the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array, completing the self - calibration of the main DAC capacitor array.

2. The self - calibration method applied to a Fibonacci capacitor array according to claim 1, wherein Error voltage V o,error has the following expression: Set the capacitance value C of each bit weight under an N-bit weighted DAC n Satisfy: C n = F n * C * (1 + ε n ), n = 1, 2, 3, …, N; F n Is the general term formula of the Fibonacci sequence, ε n Represents the capacitance value deviation of the nth capacitor, and C represents the unit capacitor; The unit capacitance composed of a capacitor array The main DAC capacitor array includes a capacitor array composed of N-bit capacitors. The lower plate of each capacitor is connected to V ref phase, and the upper plate serves as the output voltage V o . Then the output voltage V o and the corresponding digital input code D i The relationship is: D i for offsetting the ith capacitor C i process error, D i represents a binary digital input code; Under an ideal DAC, assuming ε i = 0, then we get V o,ideal which represents the output voltage without capacitance deviation; Therefore, Error voltage caused by the Nth capacitor The error voltage represents the error voltage caused by the ith capacitor.

3. The self - calibration method applied to a Fibonacci capacitor array according to claim 1, characterized in that, The calibration period of the self-calibration method starts from the non-linearity caused by the lowest-bit capacitance in the measured capacitance array, and is realized by performing a bit-by-bit conversion through sampling all capacitances except the lowest-bit capacitance with the reference voltage V ref as follows: Adopt the method of converting from the low - order capacitor to the high - order capacitor. When converting the low - order capacitor, the calibration code of the low - order capacitor is loaded into the calibration DAC, and then back - filled into the main DAC capacitor array, so that the analog signal generated at the output end of the calibration DAC cancels out the error voltage generated by the main DAC capacitor array; When converting the second - low - order capacitor, keep the DAC state after the low - order conversion is completed; and so on to the highest order until the conversion cycle ends.

4. A self-calibration device applying the self-calibration method according to claim 1, characterized in that The self - calibration device includes a main DAC capacitor array, a voltage comparator, a digital control circuit, a data register, and a calibration DAC. The output of the main DAC capacitor array is connected to the input end of the voltage comparator, and the voltage comparator is used to determine the magnitude of the output voltage of the upper plate of the main DAC capacitor array; The digital control circuit is used to control the switching sequence of the lower - plate switches of the main DAC capacitor array and control the enable in the data register; The data register is used to store the non - linear calibration term, which is a digital code. When calibrating the main DAC capacitor array, the calibration term is passed to the calibration DAC; the calibration DAC is used to convert the non - linear calibration term into an analog voltage value when calibrating the main DAC capacitor array, and the analog voltage value is used as a compensation voltage and back - filled into the main DAC capacitor array.

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