Power supply circuit

Abstract

Various embodiments of the present disclosure generally relate to power supply circuits. According to one embodiment, a power supply circuit includes: a first transistor device including a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first gate and the third gate being controlled by a closed regulation loop, and the second gate and the fourth gate being controlled by a sampled reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. FR2111782, filed on November 5, 2021, entitled “Circuit d'alimentation”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This description generally relates to power supply circuits. Background Art

[0004] Many applications require low-noise power supplies. This is the case, for example, with sensors, particularly image sensors. In these applications, the impact of noise injected by the power supply and component electronic noise is significant, as sensor pixels often cannot suppress noise sufficiently to achieve the desired image quality.

[0005] For such noise-sensitive applications, it is therefore desirable for the power supply to have a very good power supply rejection ratio (PSRR), of the order of 50 dB, and over a wide frequency range, e.g. up to 10 MHz for image sensors.

[0006] In existing solutions, the PSRR is insufficient or the performance is limited in terms of frequency and noise. Summary of the Invention

[0007] One embodiment provides a power supply circuit comprising: a first transistor device including a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The first gate and the third gate are controlled by a closed regulation loop, and the second gate and the fourth gate are controlled by a sampled reference voltage; and the second transistor device is capable of powering at least one load.

[0008] One embodiment provides a method for powering a load, the method comprising: controlling a first gate of a first transistor device with a closed regulation loop; controlling a second gate of the first device with a sampled reference voltage, the first gate being associated with a first transconductance and the second gate being associated with a transconductance greater than the first transconductance; controlling a third gate of a second transistor device with the closed regulation loop; and controlling a fourth gate of the second transistor device with the sampled reference voltage, the third gate being associated with a second transconductance and the fourth gate being associated with a transconductance greater than the second transconductance; the second transistor device being configured to power at least one load when the controlling step is performed.

[0009] According to one embodiment, the closed regulation loop is formed by an operational amplifier having as non-inverting input the voltage to be followed and as inverting input the voltage present at the source of the first transistor device; and the first gate and the third gate are coupled to the output of the operational amplifier.

[0010] According to an embodiment, the first gate of the first transistor device and the third gate of the second transistor device are back gates.

[0011] According to one embodiment, the reference voltage is generated by another closed regulation loop comprising a transistor having a front gate coupled to an output of the operational amplifier; the transistors of the first transistor device and the second transistor device are matched together with the transistors of the another closed regulation loop.

[0012] According to one embodiment, the further closed regulating transistor comprises a back gate; and the voltage applied by the amplifier to the first gate of the first transistor device is equal to the voltage applied to the aforementioned back gate of the further closed regulating transistor.

[0013] According to one embodiment, the first transistor device includes a first transistor having a first gate and a second transistor having a second gate, the source of the first transistor is connected to the source of the second transistor, and the drain of the first transistor is connected to the drain of the second transistor; and the second transistor device includes a third transistor having a third gate and a fourth transistor having a fourth gate, the source of the third transistor is connected to the source of the fourth transistor, and the drain of the third transistor is connected to the drain of the fourth transistor.

[0014] According to an embodiment, the width of the second transistor is greater than the width of the first transistor and / or the width of the third transistor is smaller than the width of the fourth transistor.

[0015] According to one embodiment, the circuit comprises a plurality of other second transistor devices whose third gates are connected to each other; each second device is configured to supply power to a different load.

[0016] According to one embodiment, the second transistor devices each include a source, the sources being coupled together.

[0017] According to an embodiment, the width of the second transistor device is k times the width of the first transistor device, k being equal to or greater than 5, for example equal to or greater than 150.

[0018] According to one embodiment, the width W2 of the transistor MLOOP2 is greater than the width W1 of the transistor MLOOP1 , and the proportionality factor Mw=W2 / W1 is equal to or greater than 5, for example, in the range of 10 to 20.

[0019] According to one embodiment, sampling of the reference voltage for controlling the second gate is implemented by a first capacitor having an electrode receiving the reference voltage via a first switch; and sampling of the reference voltage for controlling the fourth gate is implemented by a second capacitor having an electrode receiving the reference voltage via a second switch.

[0020] One embodiment provides an image sensor including: a power supply circuit; and one or more pixels powered by the power supply circuit.

[0021] One embodiment provides an image sensor comprising: a power supply circuit; and pixel columns, each pixel column being powered by one of the second transistor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above features and advantages and other aspects will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0023] Figure 1 An example of a closed-loop power supply circuit for powering a pixel array is schematically shown;

[0024] Figure 2 An example of an open-loop power supply circuit for powering a pixel array is schematically shown;

[0025] Figure 3 An image sensor according to an embodiment of the present specification is schematically shown, the image sensor including a power supply circuit for supplying power to a pixel array;

[0026] Figure 4 Schematically shows another embodiment according to the present specification Figure 3 A closed bias loop;

[0027] Figure 5 Schematically illustrates a power supply circuit for supplying power to a pixel array of an image sensor according to another embodiment of the present specification; and

[0028] Figure 6 The figure schematically shows a power supply circuit for supplying power to a pixel array of an image sensor according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In the various figures, similar features are denoted by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0030] For clarity, only the steps and elements that are helpful for understanding the embodiments described herein are described and illustrated in detail.

[0031] Unless otherwise specified, when two elements are referred to as being connected together, it means they are directly connected without any intermediate elements (except conductors), and when two elements are referred to as being coupled together, it means the two elements may be connected or coupled via one or more other elements.

[0032] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers (such as terms "front", "back", "upper", "lower", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "upper" and "lower", etc.) or referring to orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figures.

[0033] Unless otherwise specified, "about," "approximately," "substantially," and "on the order of" mean within 10%, preferably within 5%.

[0034] Figure 1 An example of a closed-loop power supply circuit 10 for powering a pixel array 20 (pixel array) is schematically shown. Generally, in the drawings of this specification, the pixel array 20 is represented by a current source corresponding to the bias current used to read the pixels. This current source is arranged in parallel with a capacitive element Cvrtsf, which represents the sum of the capacitive elements of the pixels.

[0035] according to Figure 1 In the example of , the power supply circuit 10 includes a transistor 102 for powering the pixel array 20. The gate of the transistor 102 is coupled to the output of the operational amplifier 106. The drain of the transistor 102 is connected to the power supply rail of the voltage VDD. The source of the transistor 102 is connected to the pixel array 20. The source is further coupled to the inverting input of the operational amplifier 106 to form a closed loop. The operational amplifier 106 is configured to receive a reference voltage VREF delivered by the voltage generator 112 at its non-inverting input. The voltage VREF is a set point voltage and corresponds to the desired value of the power supply of the pixel. In particular, the reference voltage VREF can be considered to be noise-free and can be decoupled from the power supply, for example by sampling from a capacitive element. The reference voltage VREF is, for example, positive and in the range of 1.4V to 2.8V.

[0036] In operation, the closed loop formed by operational amplifier 106 applies a voltage to the gate of transistor 102 so that the voltage VRTSF delivered to pixel 20 tends toward VREF.

[0037] Although this example of a power supply circuit is capable of actively regulating the power supply voltage VRTSF, it has certain disadvantages. For example, due to the strong capacitance Cvrtsf of the pixel, active correction (such as PSRR) may be frequency limited to ensure stability. Noise originating from the operational amplifier 106 may further appear at its output and therefore appear on the power supply voltage VRTSF. In the case of shuttering and / or reading the array row by row, this may lead to row noise in the pixel array 20. Such a power supply circuit may also require decoupling capacitor elements to be provided outside the power supply circuit. Such external decoupling capacitor elements increase the time constant and may represent a separation of internal and external grounding, which may have an adverse effect on decoupling. It also causes inductive effects due to its implantation.

[0038] Figure 2 There is schematically shown an example of an open loop power supply circuit 200 that powers the pixel array 20. The power supply circuit 200 is passive because closed loop correction is not enabled.

[0039] Figure 2 Power supply circuit 200 includes transistor 102 and voltage generator 112, similar to power supply circuit 10. In power supply circuit 200, the gate of transistor 102 is coupled to the electrode of sampling capacitor Csmp, which is referenced to ground, and is coupled to the output of operational amplifier 203 via switch 202 controlled by switch signal SMP. The output of operational amplifier 203 is further coupled to the gate of transistor 206. The drain of transistor 206 is coupled to the power supply rail of voltage VDD. The source of transistor 206 is coupled to both current source 212 and the inverting input of operational amplifier 106 to form a closed loop. Operational amplifier 203 receives reference voltage VREF at its non-inverting input.

[0040] When switch 202 is set to an open state, the voltage present at the gate level of transistor 206 is sampled and held by capacitor Csmp on the gate of transistor 102. The source of transistor 102 follows the voltage present at its gate level to deliver supply voltage VRTSF to pixel array 20.

[0041] The advantage of using switch 202 is that it can make the circuit on the pixel power supply side passive. Figure 1In contrast to the example of , the switch 202 further makes it possible that the high capacitance of the pixel Cvrtsf is no longer included in the closed loop and that the frequency limitation due to this capacitance can be avoided. The switch 202 also makes it possible to make the delivery of the voltage VRTSF independent of the closed regulation loop 230 formed by the amplifier 203, the current source 212 and the transistor 206. However, the power supply circuit 200 has certain disadvantages. For example, in certain cases where the voltage VDD is relatively low, the transistor 102 may not be saturated enough, which will limit the PSRR. In order to better saturate the transistor, its width should be increased. In this case, the capacitive divider formed by the gate-drain capacitance element of the transistor 102 and the sampling capacitance element Csmp may limit the attenuation of the power supply noise. The early effect of the transistor 102 is also Figure 2 The example of is limited because the source undergoes a modulation proportional to the drain modulation. In order to obtain better saturation of transistor 102, its voltage VDD can be increased by a charge pump, but this will lead to an increase in power consumption. In addition, when switch 202 is in the off state, the voltage at the gate of transistor 102 is fixed, the insulation of power supply VDD is passive, and is therefore less efficient than a closed loop. Such a power supply circuit may also require a decoupling capacitor element to be provided outside the power supply circuit.

[0042] Figure 3 An image sensor 350 including a power supply circuit 300 according to an embodiment of the present specification is schematically shown. The power supply circuit 300 supplies power to the pixel array 20, for example.

[0043] Figure 3 The power supply circuit 300 includes a closed feedback loop REGULATION LOOP associated with a closed bias loop BIAS LOOP. The loop REGULATION LOOP can define an operating point of the feedback loop REGULATION LOOP by, for example, delivering bias and set point voltages VGVRT and VREF1.

[0044] For example, the closed regulation loop REGULATION LOOP acts on the transistor MVRT, the source of which is coupled to, preferably connected to, the pixel array 20. The drain of the transistor MVRT is coupled to, preferably connected to, the power rail VDD. The transistor MVRT includes a front gate 302 and a back gate 304.

[0045] In general, the terms "back gate" and "front gate" indicate that the back gate and the front gate can independently contribute to the same channel of the transistor with different relative transconductances. The back gate and the front gate can, for example, correspond to technologies using a depleted, preferably fully depleted, semiconductor-on-insulator substrate (fully depleted silicon-on-insulator FDSOI).

[0046] The feedback loop REGULATION LOOP includes a transistor MLOOP, a front gate 308 of the transistor MLOOP coupled to, preferably connected to, the front gate 302 of the transistor MVRT, and a back gate 310 of the transistor MLOOP coupled to, preferably connected to, the back gate 304 of the transistor MVRT and the output of the operational amplifier 106, similar to Figure 1 . Figure 3 A specific embodiment of the operational amplifier 106 is shown.

[0047] According to an example of an embodiment, the back gate 304 is completely arranged in the substrate of the power circuit 300, and the channel of the transistor MVRT is formed in a silicon layer insulated from the substrate by an insulating layer. Therefore, the back gate 304 is electrically insulated from the channel of the transistor MVRT. In addition, the front gate 302 is arranged at the surface of the substrate, for example, and is electrically insulated from the transistor channel by an insulating layer, the thickness of the insulating layer being lower than the insulating layer separating the back gate of the transistor channel. By matching, the back gate 310 and the front gate 308 of the transistor MLOOP can be arranged similarly to the back gate 304 and the front gate 302 of the transistor MVRT, respectively.

[0048] Due to the relative oxide thicknesses of the front and back gates, the capacitance associated with each back gate 304, 310 is less than the capacitance associated with each front gate 302, 308. The transconductance associated with each back gate 304 and 310 is also less than the transconductance associated with each front gate 302 and 308.

[0049] According to one embodiment, the substrate of the power supply circuit 300 is a FDSOI type substrate. In this case, the back gates 304 and 310 can be formed below the insulator layer. In addition, the front gate 302 and / or the front gate 308 can be formed at the surface above the insulator.

[0050] In the power supply circuit 300 , the front gate 302 of the transistor MVRT is coupled, on the one hand, preferably to the electrode of the sampling capacitor Csmp2 referenced to ground, and on the other hand, preferably to the output of the bias loop BIAS LOOP, at the level of a node 324 , via a switch 306 controlled by a switching signal SMP.

[0051] According to one embodiment, the size of transistor MLOOP is smaller than that of transistor MVRT, for example, one hundred times smaller. In practice, the size of transistor MVRT is set to supply power to pixel array 20, while transistor MLOOP is used to generate a voltage applied to the back gate of transistor MVRT. Transistors MLOOP and MVRT and the associated current sources can be particularly matched to each other, that is, the densities of the currents flowing therethrough are the same or substantially the same. Matching between transistors can further mean that the voltages they receive on the drain, source, and gate are similar from one transistor to another and / or that their structures are similar.

[0052] The drain of transistor MLOOP is connected to power rail VDD. The source of transistor MLOOP is coupled, preferably connected, to both current source 312 coupled to ground and the inverting input of operational amplifier 106 to form a closed loop. In contrast, the source of transistor MVRT is not coupled or connected to the closed loop, and is particularly connected to the operational amplifier. Otherwise, the source of transistor MVRT does not supply power to the closed loop. In addition, the source of transistor MLOOP is not coupled or connected to transistor MVRT, nor is it coupled to a load. Therefore, the capacitances at the sources of transistors MLOOP and MVRT are independent of each other, and the capacitance at the source of transistor MLOOP can be configured to be lower than the capacitance at the source of transistor MVRT.

[0053] In an example, the width of transistor device MVRT is k times the width of transistor device MLOOP, where the plurality of k is, for example, equal to or greater than 1, and the source of transistor device MLOOP is configured to have a capacitance that is at least 10*k times smaller than the capacitance of load 20 present at the source of transistor MVRT, and in some cases, at least 100*k times smaller than the capacitance of load 20 present at the source of transistor MVRT.

[0054] An advantage associated with the fact that transistor MVRT sources power the closed loop is that the product gain x bandwidth of the closed loop can be high enough to optimize the PSRR in the desired operating frequency range (e.g., approximately 10 MHz). Furthermore, to ensure closed loop stability, the other elements of the loop should not introduce poles below the product gain x bandwidth of the closed loop. More specifically, the pole formed by the output impedance of amplifier 106 combined with the capacitance of the back gates of device MLOOP and MVRT, and the pole formed by the output impedance of device MLOOP combined with the capacitance at node VRTLOOP, should both have frequencies greater than the product gain x bandwidth of the closed loop. Including the source of transistor MVRT in the closed loop will create a pole at a relatively low frequency due to the load capacitance of load 20. In practice, the load capacitance of load 20 will cause instability of the circuit at the desired PSRR performance, and the product gain x bandwidth will limit the PSRR performance to an insufficient level.

[0055] Another advantage of not connecting the source of transistor MLOOP to load 20 is that transistor MLOOP can be configured to have a relatively low capacitance at its source, rather than the capacitance of the load, which corresponds, for example, to the capacitance of the pixel array. This allows for stability, particularly around the desired operating frequency range of 10 MHz.

[0056] The output voltage of the amplifier 106 applied to the back gate of the device MVRT is, for example, able to correct the PSRR at the output node VRTSF of the power supply circuit, because since the capacitance of the back gate is significantly smaller than the capacitance of the front gate (e.g. only 15%), its bandwidth is higher than the power supply noise from the power supply rail VDD.

[0057] The switch 306 is actuated by sampling the signal SMP and storing the voltage VGVRT on the capacitor Csmp2. In particular, when the switch 306 is set to the off state, the voltage VGVRT is sampled by the capacitor Csmp2 and maintained at the level of the front gates 302 and 308. The source of the transistor MVRT follows the voltage present at the level of the front gate 304 to deliver the power supply voltage VRTSF linked to the voltage VGVRT to the pixel array 20. The source of the transistor MLOOP follows the voltage present at the level of the gate 308 to deliver the voltage VRTLOOP linked to the voltage VGVRT, which is fed back into the loop.

[0058] In operation, the voltage maintained on front gate 308 by capacitor Csmp2 determines the voltage at the source of transistor MLOOP, causing voltage VRTLOOP to mirror voltage VREF1, for example, through matching. Furthermore, the loop formed by operational amplifier 106 applies a voltage to back gate 310 of transistor MLOOP, causing voltage VRTLOOP to approach VREF1, independent of power supply VDD. Thus, power supply noise can be corrected.

[0059] The output of operational amplifier 106 further applies a voltage to backgate 304 of transistor MVRT to correct the voltage induced on frontgate 302. According to one example, feedback to backgate 304 of transistor MVRT and backgate 310 of transistor MLOOP is generated without any resistor divider; the source of transistor MLOOP is, for example, directly connected to the input of operational amplifier 106. In this case, more gain is achieved in the closed loop, which enhances the gain-by-bandwidth product compared to the case where a resistor divider is present. According to an example where there is matching between transistors MLOOP and MVRT, the correction applied by the regulation loop to backgate 310 to correct for power supply noise at node VTRLOOP is the same as the correction applied to the backgate of transistor MVRT to correct for power supply noise at node VRTSF. According to one embodiment, the width of transistor MVRT is k times the width of transistor MLOOP. For example, k is equal to or greater than 5, such as equal to or greater than 150. The size (ie, width) of transistor MVRT is greater than that of transistor MLOOP, and the current provided at the source level of transistor MVRT can be higher than the current provided at the source level of transistor MLOOP. In particular, the current density in these transistors is the same or substantially the same.

[0060] The operational amplifier 106 of the circuit 300 includes, for example, a first differential stage 303. The output of the first differential stage 303 is coupled, for example, connected to the gate of a transistor M2STAGE to form a second amplification stage of the operational amplifier 106. The drain of the transistor M2STAGE is charged by a current source 305, for example, connected to the power supply rail VDD, and is also connected to the back gates of the transistors MVRT and MLOOP.

[0061] In some cases, a capacitor C miller (e.g., a so-called "Miller" compensation capacitance element) couples the drain and gate of transistor M2STAGE. This helps ensure amplifier stability.

[0062] Operational amplifier 106 receives reference voltage VREF1SMP at its non-inverting input. Figure 3 In the example, reference voltage VREF1SMP represents the sampled reference voltage VREF1. According to one embodiment, to obtain reference voltage VREF1SMP, the source of transistor MBIAS is coupled to the electrode of sampling capacitor Csmp1, which is referenced to ground, at node 326 via switch 320. Switch 320 is controlled, for example, by switch signal SMP. Node 326 is further coupled, preferably connected, to the non-inverting input of amplifier 106. According to another embodiment, switch 320 is coupled directly to the output of potentiometer 315, rather than to the source of transistor MBIAS.

[0063] The bias loop BIAS LOOP includes a current source 311 that powers a potentiometer 315 coupled to ground. The output voltage of the potentiometer is a reference voltage VREF. Voltage VREF1 is equal to or approximately equal to VREF. For example, voltage VREF1 is offset relative to voltage VREF by an offset voltage between the inverting input and the non-inverting input of amplifier 203. The output of the potentiometer is coupled, preferably connected, to a reference voltage VREF. Figure 2The non-inverting output of operational amplifier 106 is similar to that of amplifier 203 and is therefore referenced in the same manner. The output of operational amplifier 203 is coupled to, and preferably connected to, the front gate of transistor MBIAS. The inverting input of operational amplifier 203 is coupled to, and preferably connected to, the source of transistor MBIAS and current source 318. Current source 318 is coupled to ground, for example. The drain of transistor MBIAS is powered by power rail VDD. Transistors MBIAS, MLOOP, and MVRT are, for example, matched together and matched to their dedicated current sources so that the average output potential of operational amplifier 106 (i.e., its idle level) corresponds to the back gate potential of transistor MBIAS. In other words, due to the matching between transistors MBIAS and MLOOP, the voltage applied by amplifier 106 to back gate 310 of transistor MLOOP (i.e., its average output level) corresponds to the voltage applied to the back gate of transistor MBIAS in loop BIAS LOOP. According to one embodiment, the voltage applied to the back gate of transistor MBIAS is obtained by connecting the back gate of transistor MBIAS to its front gate. The voltage delivered to the back gate of the transistor MBIAS can also be delivered in different ways. For example, according to an embodiment not shown, the applied voltage originates from a source external to the loop BIAS LOOP.

[0064] The value of the output voltage VREF of the potentiometer 315 is selected so as to target the power supply voltage VRTSF of the pixel array 20. If it is desired to obtain the power supply voltage VTSF at the source level of the transistor MVRT, the voltage VGVRT should take into account the gate-source voltage of the transistor MVRT. The value of the voltage VGVRT obtained at the output of the operational amplifier 203 is the value obtained by increasing the gate-source voltage of the transistor MBIAS relative to the target voltage VRTSF.

[0065] exist Figure 3 In the example shown, operational amplifier 106 driving the back gates of MLOOP and MVRT has an operating portion centered around voltage VGVRT. It is within the ability of those skilled in the art to implement other embodiments to deliver a voltage to the back gate of transistor MBIAS that will determine the operating point at the output of amplifier 106.

[0066] By controlling the voltage at the back gates 304 and 310 , the voltage at the source of the transistor MVRT can be finely and continuously adjusted over time within a wide frequency range.

[0067] By coupling the output of operational amplifier 106 to backgates 304, 310, the noise generated during voltage regulation is advantageously limited by a ratio equal to gmb / (gm+gmb), which is similar for transistors MLOOP and MVRT when they are matched together. The transconductance gmb is specific to each of these transistors and is associated with the backgate. The transconductance gm is specific to each of these transistors and is associated with the frontgate. For a given transistor, the transconductance gmb is less than the transconductance gm, so the ratio is less than 1. In addition, the capacitance of each backgate 304, 310 is much smaller than the capacitance linked to each frontgate 302, 308, making it possible to achieve closed-loop regulation of voltages VRTLOOP and VRTSF over a wide frequency band.

[0068] Figure 3 Another advantage of the power supply circuit 300 is that no external decoupling capacitors are required. In fact, the loop is internally stabilized by the low-value Miller capacitor Cmiller, which enables integration of the Miller capacitor Cmiller within the circuit and allows regulation at high frequencies. The absence of external decoupling capacitors in the power supply circuit can improve performance, reduce costs, and ensure compliance with PSRR specifications within the target frequency band (10 MHz for some image sensor power supplies).

[0069] Despite Figure 3 In the example of FIG. 1 , a single switch and a single capacitor are used to sample and store the voltage VGVRT at both front gate 302, 308 levels, but according to Figure 3 In an embodiment not shown in FIG. 3 , the switch 306 and the capacitor Csmp2 may be replicated for each front gate 304 , 308 .

[0070] Despite Figure 3 In the example shown, the bias voltages VGVRT and VREF are derived from the same bias loop BIAS LOOP, but those skilled in the art can envision closed loops for these voltages. In addition, those skilled in the art can use other methods other than closed loops to generate the voltages VGVRT and / or VREEF1. In view of the different possibilities available to those skilled in the art to implement the voltages VGVRT and / or VEF1, Figure 5 and Figure 6 In FIG, only the supply rails of voltages VGVLT and VREF1 are shown.

[0071] Figure 4 Schematically shows another embodiment according to the present specification Figure 3 In this example, the back gate of transistor MBIAS is coupled to the source of transistor MBIAS.

[0072] Figure 5 A power supply circuit 500 for supplying power to the pixel array 20 of an image sensor 550 according to another embodiment of the present disclosure is schematically shown.

[0073] Figure 5 The power supply circuit 500 is similar to the power supply circuit 300, except that the transistor MLOOP is Figure 5 is replaced by transistors MLOOP1 and MLOOP2, and transistor MVRT is Figure 5 are replaced by transistors MVRT2 and MVRT1.

[0074] The drains of transistors MLOOP1 and MLOOP2 are coupled, preferably connected together, and the sources of transistors MLOOP1 and MLOOP2 are also coupled, preferably connected together. Transistors MLOOP1 and MLOOP2 thus form a dual-gate transistor device. The gate of transistor MLOOP1 is coupled, preferably connected to the output of operational amplifier 106, and the gate of transistor MLOOP2 is coupled, preferably connected to node 324.

[0075] Similarly, the drains of transistors MVRT2 and MVRT1 are coupled, preferably connected together, and the sources of transistors MVRT2 and MVRT1 are also coupled, preferably connected together. Transistors MVRT2 and MVRT1 thus form a dual-gate transistor device. The gate of transistor MVRT1 is coupled, preferably connected, to the output of operational amplifier 106, and the gate of transistor MVRT2 is coupled, preferably connected, to node 324.

[0076] Transistors MLOOP1 , MLOOP2 , MVRT2 , and MVRT1 are, for example, bulk transistors having substrate nodes coupled to, for example, ground.

[0077] In some cases where the lengths of transistors MLOOP1 and MLOOP2 are equal, the width W2 of transistor MLOOP2 is larger than the width W1 of transistor MLOOP by a proportional factor (MLOOP1 / MLOOP2). w=W2 / W1), the proportionality factor being equal to or greater than, for example, 5, or, for example, in the range of 10 to 20. The width of transistor MVRT2 is greater than the width of transistor MVRT1, for example, by the same proportionality factor. According to one example, the size of transistor MVRT2 is N times the size of transistor MLOOP2. According to one example, the size of transistor MVRT1 is a multiple of the size of transistor MLOOP1, preferably N times as much as described above. According to this example, transistor MVRT1 has a width W1*N, and transistor MVRT2 has a width W2*N. The multiple N is, for example, equal to the ratio of the current provided to pixel array 20 to the current provided by current source 312. The multiple N is, for example, proportional to the number of columns to be powered in pixel array 20. In one example, the multiple N is equal to or greater than 100, for example, equal to or greater than 150.

[0078] According to the example where the lengths of the transistors MLOOP1, MLOOP2, MVRT1 or MVRT2 are different, the scaling factor takes into account the respective lengths of the transistors and can be expressed as M WL =(W2 / L2) / (W1 / L1), where L2 and L1 are the lengths of transistors MLOOP2 and MLOOP1 respectively. WL With M W are of the same order of magnitude.

[0079] In particular, transistors MLOOP1, MLOOP2, MVRT2, and MVRT1 and associated current sources are matched for optimal implementation.

[0080] In this configuration, the transconductance associated with the gate of transistor MVRT1 is therefore less than the transconductance associated with the gate of transistor MVRT2. Similarly, the transconductance associated with the gate of transistor MLOOP1 is less than the transconductance associated with the gate of transistor MLOOP2. Through matching, the ratio of the transconductance associated with the gate of transistor MVRT1 to the transconductance associated with the gate of transistor MVRT2 can be the same as the ratio of the transconductance associated with the gate of transistor MLOOP1 to the transconductance associated with the gate of transistor MLOOP2. Therefore, the gate of transistor MLOOP1 has the same effect on the total current conducted by transistors MLOOP and MLOOP2 as back gate 310 of transistor MLOOP. Similarly, the gate of transistor MLOOP2 has the same effect on this total current as front gate 308 of transistor MLOOP. Therefore, the gate of transistor MVRT1 has the same effect on the total current conducted by transistors MVRT2 and MVRT1 as back gate 304 of transistor MVRT, and the gate of transistor MVRT3 has the same effect on this total current as front gate 308 of transistor MVRT4.

[0081] Figure 6FIG2 schematically shows a power supply circuit 600 for supplying power to a pixel array 20 of an image sensor 650 according to another embodiment of the present disclosure.

[0082] The power supply circuit 600 includes an operational amplifier 106, a voltage generator 112, a transistor MLOOP and a current source 312. Figure 1 The left side portion of the power supply circuit 10 is arranged similarly. Figure 6 The pixel array 20 is divided into five parallel columns of pixels 610, 612, 614, 616, and 618. However, the number of columns is not limited and can reach hundreds or even thousands.

[0083] exist Figure 6 In the power supply circuit, Figure 3 The transistor MVRT is distributed among multiple transistors so that a transistor powers each column or a group of columns. Figure 6 The combined width of all transistor MVRTs obtained in is equal to, for example, Figure 3 Furthermore, for example, the switch 306 and the capacitor Csmp are repeated to sample and store the voltage VGVRT on the gate of each transistor MVRT.

[0084] Figure 6 The distribution of transistors MVRT can reduce the current level at each source of transistors MVRT of power circuit 600. This can even out the power supply between each column or group of columns so that all columns see the same voltage while avoiding voltage drops between columns.

[0085] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0086] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A power supply circuit comprising: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; as well as a second transistor device comprising a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance, wherein the second transistor device is configured to provide power to at least one load, wherein the first gate and the third gate are controlled by a closed regulation loop, and the second gate and the fourth gate are controlled by a sampled reference voltage; in: The closed regulation loop includes an operational amplifier having a non-inverting input configured to receive a voltage to be followed and an inverting input configured to receive a voltage present on a source of the first transistor device; and The first gate and the third gate are coupled to an output of the operational amplifier; wherein the first gate of the first transistor device and the third gate of the second transistor device are back gates; The power supply circuit further includes: a ground-referenced sampling capacitor configured to maintain a voltage on the second gate to determine a voltage at a source of the first transistor device; The output of the operational amplifier applies a voltage to the third gate of the first transistor device, so that the voltage to be followed received at the non-inverting input tends to the sampling reference voltage.

2. The circuit of claim 1 , wherein the sampling reference voltage is generated by a further closed regulation loop, the further closed regulation loop comprising an operational amplifier and a fifth transistor, the output of the operational amplifier being coupled to a front gate of the fifth transistor, the inverting input of the operational amplifier being coupled to a source of the fifth transistor; the fifth transistor having a front gate coupled to the output of the operational amplifier; and The transistors of the first and second transistor devices are matched together with the fifth transistor of the further closed regulation loop.

3. The circuit of claim 1 , wherein: The closed regulation loop includes a first operational amplifier having a non-inverting input configured to receive a voltage to be followed and an inverting input configured to receive a voltage present on a source of the first transistor device; and The first gate and the third gate are coupled to an output of the first operational amplifier; The sampling reference voltage is generated by a further closed regulation loop comprising a transistor having a front gate coupled to an output of a second operational amplifier; The transistors of the first transistor device and the second transistor device are matched together with the transistors of the further closed regulation loop; said transistor of said further closed regulation loop comprises a back gate; and The voltage applied by the first operational amplifier to the first gate of the first transistor device is configured to be substantially equal to the voltage applied to the back gate of the transistor of the further closed regulation loop.

4. The circuit of claim 1 , wherein: The first transistor device includes a first transistor having the first gate and a second transistor having the second gate, a source of the first transistor being connected to a source of the second transistor, and a drain of the first transistor being connected to a drain of the second transistor; as well as The second transistor device includes a third transistor having the third gate and a fourth transistor having the fourth gate, the source of the third transistor being connected to the source of the fourth transistor, and the drain of the third transistor being connected to the drain of the fourth transistor. 5 . The circuit according to claim 4 , wherein a width of the second transistor is greater than a width of the first transistor, or a width of the third transistor is smaller than a width of the fourth transistor. 6 . The circuit of claim 1 , further comprising a plurality of second transistor devices having third gates coupled together, wherein each second transistor device in the plurality of second transistor devices is configured to supply power to a different load. 7 . The circuit of claim 6 , wherein sources of each of the plurality of second transistor devices are coupled together. 8 . The circuit of claim 1 , wherein a width of the second transistor device is k times a width of the first transistor device, where k is equal to or greater than 5. 9 . The circuit of claim 1 , wherein the first transistor device comprises a first main conduction node configured to supply power to the closed regulation loop.

10. The circuit of claim 9, wherein the first main conduction node of the second transistor device is configured to supply power to the at least one load, and the first main conduction node of the first transistor device is configured to have a capacitance that is less than a capacitance of the first main conduction node of the second transistor device.

11. The circuit of claim 10, wherein the first main conduction node of the first transistor device is not connected to the second transistor device.

12. The circuit of claim 11 , wherein a width MVRT of the second transistor device is k times the width of the first transistor device, k being equal to or greater than 1, and wherein the first main conductive node of the first transistor device is configured to have a capacitance that is 10*k times smaller than a capacitance of the load (20). 13 . The circuit of claim 12 , wherein the first main conduction node of the first transistor device is configured to have a capacitance 100*k times smaller than the capacitance of the load.

14. An image sensor comprising: The power supply circuit according to claim 8; as well as A plurality of pixel columns, each pixel column of the plurality of pixel columns being powered by a corresponding second transistor device of the plurality of second transistor devices.

15. An image sensor comprising: The power supply circuit according to claim 1; as well as At least one pixel is coupled to the power supply circuit.

16. A load power supply method, comprising: controlling a first gate of a first transistor device using a closed regulation loop; wherein the closed regulation loop comprises an operational amplifier having a non-inverting input and an inverting input, the non-inverting input being configured to receive a voltage to be followed, the inverting input being configured to receive a voltage present on a source of the first transistor device; and the first gate and the third gate being coupled to an output of the operational amplifier; controlling a second gate of the first transistor device with a sampled reference voltage, the first gate being associated with a first transconductance and the second gate being associated with a transconductance greater than the first transconductance; controlling a third gate of the second transistor device using the closed regulation loop; controlling a fourth gate of the second transistor device with the sampled reference voltage, the third gate being associated with a second transconductance, and the fourth gate being associated with a transconductance greater than the second transconductance; as well as providing power to at least one load via the second transistor device; wherein the first gate of the first transistor device and the third gate of the second transistor device are back gates; wherein a voltage at the second gate is maintained by a sampling capacitor referenced to ground to determine a voltage at the source of the first transistor device; The output of the operational amplifier applies a voltage to the third gate of the first transistor device so that the to-be-followed voltage received at the non-inverting input tends to the sampling reference voltage.

17. The method of claim 16, wherein the first gate of the first transistor device and the third gate of the second transistor device are back gates.

18. The method of claim 16, wherein: The first transistor device includes a first transistor having the first gate and a second transistor having the second gate, a source of the first transistor being connected to a source of the second transistor, and a drain of the first transistor being connected to a drain of the second transistor; as well as The second transistor device includes a third transistor having the third gate and a fourth transistor having the fourth gate, the source of the third transistor being connected to the source of the fourth transistor, and the drain of the third transistor being connected to the drain of the fourth transistor.

19. The method of claim 16, wherein: the second transistor device comprises a plurality of second transistor devices; and Providing power to the at least one load includes providing power to a plurality of loads via corresponding second transistor devices of the plurality of second transistor devices.

Images