Storage chip, storage device and access method thereof

Abstract

The present application provides a memory chip, a memory device, and an access method thereof, which can solve the problem that the access performance of the memory decreases when the capacity of a single medium particle increases while the total capacity of the memory device remains unchanged, thereby improving the access rate of the memory. The controller of the memory chip can determine the access mode for accessing the flash memory medium based on the relationship between the number of storage channels and the flash memory medium. If the access mode for accessing the flash memory medium is a wide-mouth mode, such as when the number of storage channels is greater than the number of flash memory media, the controller can merge some or all of the multiple storage channels so that the merged first channel includes at least one associated storage channel, and access the flash memory medium through the merged first channel. After the storage channels are merged, the data line width of the storage channel that can be used by the corresponding flash memory medium can be increased, thereby improving the read and write performance of the memory chip, and further improving the access efficiency of the memory.

Description

Technical Field

[0001] The present application relates to the field of mobile storage technology, and in particular to a storage chip, a storage device and an access method thereof. Background Art

[0002] Currently, NAND flash memory (NAND flash) is used as the primary information cache in consumer solid-state drives (SSDs). With the advancement of process technology and three-dimensional (3D) stacking technology, the density of individual NAND flash die is increasing, increasing the capacity of each die.

[0003] According to the Open NAND Flash Interface (ONFI) and Toggle protocols, the data line width of a single storage channel on a NAND flash interface is currently 8 bits. For a storage device, the number of storage channels coupled to the controller is fixed, for example, 8. Given a fixed total capacity, as the capacity of a single dielectric particle increases, the relative proportion of the data line width of the storage channel that can be used by that single dielectric particle decreases relative to a single dielectric particle with a smaller capacity. For example, when the capacity of a single dielectric particle increases from 64 gigabytes (GB) to 128GB, the data line width of the storage channel that can be used remains 8 bits. Therefore, as the capacity of a single dielectric particle increases, the performance of the direct memory access (DMA) in the NAND flash interface may decrease, leading to a decrease in the memory access rate. Summary of the Invention

[0004] The embodiments of the present application provide a memory chip, a memory device, and an access method thereof, which can solve the problem of decreased memory access performance when the capacity of a single medium particle increases while the total capacity of the storage device remains unchanged, thereby improving the memory access rate.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a memory chip. The memory chip includes a controller and multiple memory channels coupled to the controller. The controller is configured to determine an access mode for accessing a flash memory medium based on the number of the multiple memory channels and the number of flash memory media coupled to the controller via the multiple memory channels. The controller is further configured to, if the access mode is a wide-port mode, merge the multiple memory channels into a first channel and access the flash memory medium via the first channel. The first channel includes at least one associated memory channel, and the bit width of the associated memory channel is N times that of a single memory channel; N is a positive integer greater than or equal to 2.

[0007] That is to say, the controller can merge all the storage channels into one or more associated storage channels. For example, if a memory chip includes 8 storage channels with a bit width of 8 bits, the 8 storage channels can be merged in pairs, that is, merged into 4 associated storage channels with a bit width of 16 bits each; it can also merge some of the storage channels into one or more associated storage channels. For example, if a memory chip includes 8 storage channels with a bit width of 8 bits, 4 of the 8 storage channels can be merged into a 32-bit associated storage channel, and the rest cannot be merged; or 4 of the 8 storage channels can be merged in pairs, that is, merged into 2 associated storage channels with a bit width of 16 bits each, and the rest cannot be merged.

[0008] Based on the memory chip provided in the first aspect, a controller of the memory chip can determine an access mode for accessing the flash memory medium based on the relationship between the number of storage channels and the number of flash memory media. If the access mode is a wide-port mode, that is, if the conditions for the wide-port mode are met, such as when the number of storage channels is greater than the number of flash memory media, the controller can merge some or all of the multiple storage channels so that the merged first channel includes at least one associated storage channel, and access the flash memory medium through the merged first channel. The merging of the storage channels can increase the data line width of the storage channels available to the corresponding flash memory medium, thereby improving the read and write performance of the memory chip and further improving the access efficiency of the memory.

[0009] Optionally, the controller is further configured to access the flash memory medium through multiple storage channels if the access mode is normal mode. That is, if the wide-port mode conditions are not met, such as when the number of storage channels is equal to the number of flash memory media, the storage channels are not merged, and the controller accesses the flash memory media through the existing multiple storage channels. This allows the memory chip to be compatible with more memories, thereby reducing costs.

[0010] Optionally, the number of multiple storage channels coupled to the controller is X, and the number of flash memory media coupled to the controller via the multiple storage channels is Y, where both X and Y are positive integers. If X>Y, the access mode for accessing the flash memory media can be a wide-port mode. In this solution, if X is greater than Y, it indicates that there are idle storage channels in the memory chip. By reusing these idle storage channels, the data line width of the storage channels corresponding to the flash memory media can be increased, thereby improving memory access efficiency.

[0011] Furthermore, the controller can also be configured to access the first flash memory medium through a first associated storage channel. The first associated storage channel can be one of the associated storage channels in the first channel; the first flash memory medium can be one of the flash memory media. The number of storage channels M in the first associated storage channel satisfies the following relationship: M = (P / Q)*X. P is the media capacity of the first flash memory medium; Q is the total media capacity of the flash memory media coupled to the controller via multiple storage channels; and X is the number of multiple storage channels coupled to the controller. In this solution, when the controller merges M of the multiple storage channels into the first associated storage channel, the number of storage channels included in the first associated storage channel for accessing the first flash memory medium can be directly determined using the relationship M = (P / Q)*X. That is, once the number of multiple storage channels coupled to the controller, the media capacity of the first flash memory medium, and the total media capacity of the flash memory media coupled to the controller via multiple storage channels are determined, the number of storage channels included in the first associated storage channel can be determined.

[0012] In one possible design, the controller may include a cache unit and an alignment control unit. The cache unit may include multiple cache spaces, each corresponding to a plurality of storage channels in a memory chip. In this memory chip, the controller may be configured to write data to a first flash memory medium via a first associated storage channel. The cache unit may be configured to split first data into multiple data segments and, in a predetermined order, sequentially and cyclically store the multiple data segments of the first data in M ​​cache spaces corresponding to M storage channels in the first associated storage channel. The alignment control unit may be configured to cyclically retrieve data segments from M cache spaces corresponding to M storage channels in the first associated storage channel in a predetermined order and send them to the M storage channels in the first associated storage channel, thereby writing the first data to the first flash memory medium. In this solution, a coded block (CW data) is stored in the first flash memory medium and data can be transmitted via multiple storage channels in the first associated storage channel. Therefore, to ensure correct and orderly data storage, data alignment is required. During aligned storage, the cache unit splits a CW data (i.e., first data) into multiple data segments, and stores them in cache spaces corresponding to the M storage channels in the first associated storage channels. Furthermore, the alignment control unit sequentially retrieves each data segment of the first data from the cache spaces corresponding to the multiple storage channels in the first associated storage channels, and sends the data segments to the corresponding storage channels in the first associated storage channels, thereby achieving aligned storage of the data. This ensures that when storing data in a flash memory medium via multiple storage channels, orderly storage of the data is ensured, improving the data write efficiency of the memory chip and enhancing the reliability of the memory chip.

[0013] In another possible design, the controller may include a cache unit and an alignment control unit. The cache unit may include multiple cache spaces, each corresponding to a plurality of storage channels in the memory chip. In this memory chip, the controller may be configured to read data from a first flash memory medium via a first associated storage channel. The cache unit may be configured to retrieve second data from M storage channels in the first associated storage channel, cache the data in M ​​cache spaces corresponding to the M storage channels in the first associated storage channel, and transmit decoded data upon receiving a first message from the alignment control unit. The second data is data stored in the first flash memory medium, and the decoded data is the second data retrieved by the cache unit. The alignment control unit may be configured to record the total length of the second data retrieved from the first associated storage channel and, when the total length of the retrieved second data reaches a preset length, transmit a first message to the cache unit. The first message indicates that the retrieved second data can be decoded. In this solution, when data is read from the first flash memory medium, it is transmitted via the M storage channels in the first associated storage channel and stored in the cache spaces corresponding to the M storage channels in the first associated storage channel. Specifically, taking the example of a first associated storage channel including storage channels CH0 and CH1, if second data is returned from storage channel CH0 to the cache unit, the second data is cached in the cache space corresponding to storage channel CH0; if second data is returned from storage channel CH1 to the cache unit, the second data is cached in the cache space corresponding to storage channel CH1. This allows the second data to be successfully decoded when it reaches the size of a CW data, completing the data read operation and improving the reliability of the memory chip.

[0014] Optionally, the controller may further include a decoding unit. The cache unit may also be configured to sequentially and cyclically retrieve second data of a fixed length from the M cache spaces corresponding to the M storage channels in the first associated storage channels in a preset order, and send the second data of the fixed length to the decoding unit. In this optional solution, the decoding unit is configured to decode the second data read from the first flash memory medium. During data decoding, the cache unit sequentially retrieves the data to be decoded from the M cache spaces corresponding to the M storage channels in the first associated storage channels, and sends the data to the decoding unit for decoding, thereby ensuring that the data is read in the correct order for correct decoding, thereby improving the reliability of the memory chip.

[0015] In a second aspect, an embodiment of the present application provides a storage device comprising a plurality of flash memory media and any possible storage chip as described in the first aspect above; the plurality of flash memory media are coupled to a controller via a plurality of storage channels in the storage chip.

[0016] In a third aspect, an embodiment of the present application provides a method for accessing a storage device. The storage device includes a storage chip and multiple flash memory media, wherein the storage chip includes a controller and multiple storage channels coupled to the controller, and the multiple flash memory media are coupled to the controller through multiple storage channels. The method includes: the controller determines an access mode for accessing the flash memory media based on the number of multiple storage channels and the number of flash memory media coupled to the controller through the multiple storage channels. If the access mode is a wide-port mode, the controller merges the multiple storage channels into a first channel and accesses the flash memory media through the first channel. The first channel includes at least one associated storage channel, and the bit width of an associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2.

[0017] Optionally, if the access mode is a normal mode, the controller accesses the flash memory medium through multiple storage channels.

[0018] Optionally, the number of the plurality of storage channels coupled to the controller is X; the number of flash memory media coupled to the controller via the plurality of storage channels is Y; and both X and Y are positive integers. If X>Y, the access mode for accessing the flash memory media is the wide-port mode.

[0019] Furthermore, the controller accessing the flash memory medium through the first channel may include: the controller accessing the first flash memory medium through a first associated storage channel. The first associated storage channel is one of the associated storage channels in the first channel. The first flash memory medium is one of the flash memory media. The number M of storage channels in the first associated storage channel satisfies the following relationship: M = (P / Q) * X; where P is the media capacity of the first flash memory medium; Q is the total media capacity of the flash memory media coupled to the controller through multiple storage channels; and X is the number of multiple storage channels coupled to the controller.

[0020] In one possible design, the controller may include a cache unit and an alignment control unit; the cache unit may include multiple cache spaces, each corresponding to a plurality of storage channels in a memory chip. The controller accessing the first flash memory medium through a first associated storage channel may include: the controller writing data to the first flash memory medium through the first associated storage channel. The cache unit splits the first data into multiple data segments. The cache unit stores the multiple data segments of the first data in a cyclic manner in M ​​cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order. The alignment control unit cyclically obtains the data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order, and sends them to the M storage channels in the first associated storage channel, so that the first data is written to the first flash memory medium of the memory.

[0021] In another possible design, the controller may include a cache unit and an alignment control unit. The cache unit may include X cache spaces, each of which corresponds to one of the X storage channels in the memory chip. The controller accessing the first flash memory medium through a first associated storage channel may include: the controller reading data from the first flash memory medium through the first associated storage channel; the cache unit obtaining second data from M storage channels in the first associated storage channel and caching the data in the M cache spaces corresponding to the M storage channels in the first associated storage channel; the second data is data stored in the first flash memory medium. The alignment control unit records the total length of the second data obtained from the first associated storage channel and, when the total length of the obtained second data reaches a preset length, sends a first message to the cache unit. The first message indicates that the obtained second data can be decoded. After receiving the first message from the alignment control unit, the cache unit sends decoded data. The decoded data is the second data obtained by the cache unit.

[0022] Optionally, the controller may further include a decoding unit. The cache unit sending the decoded data may include the cache unit sequentially and cyclically acquiring second data of a fixed length from M cache spaces corresponding to M storage channels in the first associated storage channels in a preset order. The cache unit then sends the second data of the fixed length to the decoding unit.

[0023] It can be understood that any of the storage devices and storage device access methods provided above can be implemented by the storage chip provided in the first aspect above or be associated with the storage chip provided in the first aspect above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the storage chip provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the system architecture of a memory chip provided in an embodiment of the present application Figure 1 ;

[0025] Figure 2 A schematic diagram of the system architecture of a memory chip provided in an embodiment of the present application Figure 2 ;

[0026] Figure 3 A structural block diagram of a storage device provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the data storage format of a cache unit in a memory chip provided in an embodiment of the present application;

[0028] Figure 5 A flowchart of a method for accessing a storage device provided in an embodiment of the present application;

[0029] Figure 6 This is a flowchart of the interaction when writing data to a storage device provided in an embodiment of the present application;

[0030] Figure 7 This is a flowchart of the interaction when the storage device reads data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solution in this application will be described below with reference to the accompanying drawings.

[0032] In the present application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, ab, ac, bc or abc, where a, b and c can be single or multiple. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second" and so on do not limit the quantity and execution order.

[0033] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0034] Figure 1 A schematic diagram of the system architecture of a memory chip provided in an embodiment of the present application Figure 1 .like Figure 1As shown, a universal flash storage (UFS) memory chip generally includes a flash controller and multiple memory channels coupled to the flash controller. A memory channel can be a flash input / output (flash IO) pin. Typically, a flash controller in a UFS is coupled to four or more memory channels, each of which is coupled to a flash die (i.e., a medium particle) for data transmission on the flash die. If the number of memory channels coupled to the flash controller is fixed and the total memory capacity remains unchanged, if the storage capacity of a single flash die increases, the relative proportion of the data line width of the memory channel that can be used by the flash die decreases relative to that of a smaller capacity flash die. For example, when the capacity of the flash die increases from 64 gigabytes (GB) to 128GB, the data line width of the memory channel that can be used by the flash die remains at 8 bits. Therefore, when the capacity of the flash die increases, the direct memory access (DMA) access performance of the memory chip may decrease, thereby reducing the memory access rate. In addition, if the capacity of a single flash memory medium increases while the total capacity of the memory (or storage device) remains unchanged, the number of flash memory media in the memory will decrease accordingly, resulting in redundant storage channels in the memory chip and a waste of resources.

[0035] Figure 2 A schematic diagram of the system architecture of a memory chip provided in an embodiment of the present application Figure 2 Since the number of storage channels coupled to the flash memory controller is fixed and the total memory capacity remains unchanged, if the storage capacity of a single flash memory medium increases, the number of flash memory media in the memory decreases, resulting in redundant storage channels. Figure 2 ,exist Figure 2 The memory chip shown is Figure 1 In the memory chip shown, the number of flash memory media coupled to the memory chip has been reduced from four to two. Therefore, when there is a one-to-one correspondence between memory channels and flash memory media, there are idle memory channels in the memory chip. When there are idle memory channels, at least two of them can be combined into a single associated memory channel, i.e., a wide-port mode. This can increase the data line width of the memory channels available to the flash memory media, improve the read and write performance of the memory chip, and thereby increase the direct memory access (DMA) bandwidth and memory access rate.

[0036] It should be understood that the wide-port mode described in the embodiments of the present application is a usage scenario in which at least two storage channels are merged into one associated storage channel in a memory chip. The normal mode described in the embodiments of the present application is a usage scenario in which storage channels are not merged in a memory chip. Whether the wide-port mode is used in a memory chip (or storage device) is determined by the number of storage channels in the memory chip and the number of flash memory media coupled to the controller via multiple storage channels.

[0037] Specifically, if the media capacity of each flash memory medium is the same, it can be determined as follows (with Figure 1 Take the memory chip shown as an example):

[0038] If the number of flash media is less than or equal to the number of storage channels / 2, wide-port mode can be used to merge two adjacent storage channels into one storage channel. Figure 1 If the number of flash media in the system changes from 4 to 2, you can Figure 1 CH0 and CH1 are merged into one associated storage channel, and CH2 and CH3 are merged into one associated storage channel. At this time, the data line width of the associated storage channel can be expanded to twice that of a single storage channel, that is, from the original 8 bits to 16 bits.

[0039] If the number of flash media is less than or equal to the number of storage channels / 4, then the wide-port mode can be used to merge the four storage channels into one. Figure 1 If the number of flash media in the system changes from 4 to 1, you can Figure 1 CH0, CH1, CH2 and CH3 are combined into an associated memory channel. At this time, the data line width of the associated memory channel can be expanded to 4 times that of a single memory channel, that is, expanded from the original 8 bits to 32 bits.

[0040] It should be understood that if the number of flash memory media is greater than or equal to the number of storage channels, the wide-port mode is not used, and the data line width of each storage channel remains unchanged at 8 bits.

[0041] Furthermore, when the media capacity of each flash memory medium is different, wide-port mode can be used as long as the number of storage channels exceeds the number of flash memory media. In summary, in a memory chip, assume the number of storage channels is X, and the number of flash memory media coupled to the controller via multiple storage channels is Y. If the number of storage channels is greater than the number of flash memory media, that is, X>Y, then the access mode for accessing the flash memory media in the memory can adopt wide-port mode, that is, idle storage channels can be reused, so that at least two storage channels are merged into one associated storage channel.

[0042] It should be noted that merging storage channels is not limited to merging adjacent storage channels; non-adjacent storage channels can also be merged. By applying the wide-port mode, a memory (or storage device) can maintain the same read and write performance while retaining the same media capacity. If the capacity of a single flash memory medium is increased, the original memory chip (including the controller and multiple storage channels coupled to the controller) can be used, thereby reducing costs.

[0043] Figure 3 This is a structural block diagram of the storage device provided in the embodiment of this application. Please refer to Figure 3 , the storage device provided by the embodiment of the present application includes multiple flash memory media, and Figure 1 or Figure 2 The memory chip shown; wherein multiple flash memory media are coupled to the controller through multiple memory channels in the memory chip.

[0044] according to Figure 1 and Figure 2 , an embodiment of the present application provides a memory chip, the memory chip includes a controller and a plurality of memory channels coupled to the controller; wherein the controller can be Figure 1 or Figure 2 The flash memory controller in the memory channel can be as follows: Figure 1 or Figure 2 The controller is configured to determine an access mode for accessing the flash memory medium based on the number of the plurality of storage channels and the number of flash memory media coupled to the controller via the plurality of storage channels. If the number of storage channels is greater than the number of flash memory media, the access mode for accessing the flash memory medium may be determined to be a wide-port mode.

[0045] If the access mode for accessing the flash memory medium is the wide-port mode, the controller is configured to merge the multiple storage channels into a first channel and access the flash memory medium through the first channel, wherein the first channel includes at least one associated storage channel, and the bit width of each associated storage channel is N times that of a single storage channel, where N is a positive integer greater than or equal to 2.

[0046] Accordingly, if the access mode for accessing the flash memory medium is a normal mode, that is, the multiple storage channels coupled to the controller are used separately and not merged, the controller is used to access the flash memory medium through the original multiple storage channels.

[0047] It should be noted that the controller is configured to determine an access mode for accessing the flash memory medium based on the number of the multiple storage channels and the number of the flash memory media coupled to the controller through the multiple storage channels, and may adopt the following manner:

[0048] (1) Determined based on the general purpose input / output (GPIO) pin value configured on the memory chip.

[0049] When the chip is packaged, the number of flash memory media, the model of each flash memory medium, and the media capacity can be known. According to the number of flash memory media and the number of storage channels, it can be known whether the memory can be accessed in wide-port mode. Therefore, when the chip is packaged, GPIO pins can be reserved on the top layer of the UFS chip for selecting and controlling the access mode for accessing the flash memory media. For example, the value of the GPIO pin can be directly configured on the substrate. For example, when the GPIO is 1, it means that the memory chip can use wide-port mode, and idle storage channels can be reused, and at least two storage channels can be merged into one storage channel for use, thereby increasing the data line width of the storage channel.

[0050] (2) Determined based on the number of storage channels and the number of flash memory media identified.

[0051] Some flash memory media manufacturers support wide-port mode / normal mode switching. After powering on, the flash memory media can initially be in normal mode. During initialization (e.g., romcode), the flash memory media manufacturer's ID can be scanned to obtain the flash memory media model information, inferring the total media capacity of the flash memory media. Then, based on the relationship between the number of flash memory media and the number of storage channels, it can be determined whether wide-port mode needs to be switched to. If wide-port mode is required, a set feature command can be sent to the flash memory media to modify the access mode to wide-port mode. Furthermore, a controller can be used to merge some or all of the multiple storage channels into one or more associated storage channels, thereby expanding the data line width of the storage channels.

[0052] When the controller is used to merge multiple storage channels into a first channel, the number of associated storage channels in the first channel and the number of storage channels in each associated storage channel should be determined. The specific determination method is as follows:

[0053] For example, assume that the total storage capacity of a memory is 1 terabyte (TB), and the number of storage channels coupled to the flash memory controller in the memory is 8. If the memory uses flash media of the same capacity, for example, if the memory uses flash media with a capacity of 128GB, then the memory requires 8 flash media, so one storage channel and one flash media have a one-to-one correspondence. If the memory uses flash media with a capacity of 256GB, then the memory requires 4 flash media. According to the rule that one storage channel serves one flash media, 4 storage channels in the memory may be idle, so every two storage channels can be merged into one associated storage channel. Correspondingly, if the memory uses flash media with a capacity of 512GB, then the memory requires 2 flash media, so every four storage channels can be merged into one associated storage channel.

[0054] Similarly, if the memory uses flash memory media of different capacities, for example, if the memory uses four 128GB flash memory media and one 512GB flash memory media, the four storage channels can be merged into one associated storage channel for use by the 512GB flash memory media. If the memory uses two 128GB flash memory media, one 256GB flash memory media, and one 512GB flash memory media, two storage channels can be merged into one associated storage channel for use by the 256GB flash memory media, and four storage channels can be merged into one associated storage channel for use by the 512GB flash memory media.

[0055] In summary, if the first channel includes a first associated storage channel, the first associated storage channel can be used to access a first flash medium in the flash media coupled to the controller via multiple storage channels. That is, the controller can be used to access the first flash medium via the first associated storage channel. The number M of storage channels in the first associated storage channel can be determined according to the following relationship: M = (P / Q) * X; where P is the media capacity of the first flash medium; Q is the total media capacity of the flash media coupled to the controller via multiple storage channels; and X is the number of multiple storage channels coupled to the controller.

[0056] When the access mode for accessing the flash memory medium is the wide-port mode, the controller is configured to merge multiple storage channels into a first channel. For example, the first channel includes a first associated storage channel. That is, the controller may merge M storage channels from the multiple storage channels into the first associated storage channel. Specifically, the merging may be performed in the following manner:

[0057] First, a memory channel can include the DQ, DQS, CE, ALE, CLE, WEN, and RE input and output pins. CE is the chip enable (CE) pin, which can also serve as the chip select pin; ALE is the address latch enable pin; CLE is the command latch enable (CLE) pin; DQ is the data input / output pin; DQS is the bidirectional data strobe (DQS) pin; WEN is the write enable (WEN) pin; and RE is the read enable (RE) pin. It should be noted that when the ALE pin is high, address data can be transmitted; when the CLE pin is high, command data can be transmitted; and when both ALE and CLE are low, data can be transmitted.

[0058] In wide port mode, that is, when the controller determines that the access mode for accessing the flash media is wide port mode, refer to Figure 3 Each storage channel includes a programmable timing generator (PTG) and a physical layer. The PTG is used to generate data transmission timing, and the physical layer is used for data transmission. Specifically, input and output pins such as DQ, DQS, CE, ALE, CLE, WEN, and RE are coupled to the physical layer of the storage channel. Assuming that the controller merges storage channels CH0 and CH1 into a first associated storage channel (taking the data bit width of CH0 and CH1 as 8 bits), the controller controls CH1 to disable the four signal input and output pins CLE, ALE, WEN, and CE, and only enable the DQS and DQ signal input and output pins on CH1, so that CH1 is used only to transmit the upper 8 bits or lower 8 bits of data. This completes the merger of CH0 and CH1 into an associated storage channel, namely the first associated storage channel.

[0059] For example, assuming that a memory chip includes at least four memory channels, namely, memory channel CH0, memory channel CH1, memory channel CH2, and memory channel CH3, when a controller merges the four memory channels CH0, CH1, CH2, and CH3 into a first associated memory channel (taking the data bit width of CH0, CH1, CH2, and CH3 as 8 bits), the controller controls CH1, CH2, and CH3 to disable the four signal input and output pins CLE, ALE, WEN, and CE, and only enables the DQS and DQ signal input and output pins on CH1, CH2, and CH3. This allows CH1 to transmit only the upper 8th to 15th bits of data, CH2 to transmit only the 16th to 23rd bits of data, and CH3 to transmit only the 24th to 31st bits of data. At this point, the operation of merging CH0, CH1, CH2, and CH3 into the first associated memory channel is considered complete.

[0060] The above is a specific method for the controller to merge M storage channels from the plurality of storage channels into a first associated storage channel. It should be understood that the first channel includes at least one associated storage channel, so the method for merging other associated storage channels is similar to the method for merging the first associated storage channel, and will not be repeated here.

[0061] Accordingly, the controller accessing the flash memory medium through the first channel may include the controller accessing the first flash memory medium through the first associated storage channel. That is, after the controller merges at least two of the multiple storage channels into the first associated storage channel, the controller can access the first flash memory medium through the first associated storage channel. The following describes how to access the first flash memory medium through the first associated storage channel in wide-port mode.

[0062] In normal mode, one encoded codeword (CW) corresponds to only one storage channel. However, in wide-port mode, one encoded CW needs to correspond to two or more storage channels. Therefore, to facilitate decoding using low-density parity check codes (LDPC), data alignment is required. To achieve this, the controller includes an alignment control unit.

[0063] according to Figure 3The controller may include an encoder, a decoder, a codeword buffer, and an alignment controller. The encoder encodes the data to be stored into CW data; the decoder decodes the CW data read from the flash memory medium to restore the data; the codeword buffer (hereinafter referred to as the buffer) buffers the CW data; and the alignment controller aligns and maintains the order of the CW data in wide-port mode.

[0064] It should be understood that the controller determining the access mode for accessing the flash memory medium and the controller merging at least two storage channels from the multiple storage channels into the first associated storage channel can be implemented by the alignment control unit in the controller.

[0065] In the controller of the memory chip, a cache unit includes multiple cache spaces, each of which corresponds one-to-one to the multiple memory channels in the memory chip. That is, the cache unit is provided with multiple cache areas (i.e., cache spaces), each of which is used to cache transmission data from one memory channel in the memory chip. In wide-port mode, since two or more memory channels in the memory chip are combined into a first associated memory channel for accessing the first flash memory medium, a single encoded CW data item must correspond to two or more memory channels. That is, a single CW data item must be cached in two or more cache spaces in the cache unit, each of which corresponds to two or more memory channels in the first associated memory channel.

[0066] In a memory chip, a controller accesses a first flash memory medium through a first associated storage channel, which may include write operations and read operations. Specifically, the controller can be used to write data to the first flash memory medium through the first associated storage channel; the controller can also be used to read data from the first flash memory medium through the first associated storage channel.

[0067] The following is an explanation of how the controller writes data to the first flash memory medium through the first associated storage channel.

[0068] When the controller is used to write data to the first flash memory medium through the first associated storage channel, the cache unit is used to split the first data (i.e., one CW data) into multiple data segments, and store the multiple data segments of the first data in a circular manner in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order.

[0069] For example, Figure 4A schematic diagram of the data storage format of the cache unit in the memory chip provided in an embodiment of the present application. Figure 4 The figure shows two cache spaces in a cache unit corresponding to storage channels CH0 and CH1 respectively. If storage channels CH0 and CH1 are combined into the first associated storage channel, the cache unit will split a CW data into multiple 16-bit data segments (taking the data line width of storage channels CH0 and CH1 as 8 bits as an example), that is, Figure 4 The 16-bit data segments D0, D1, D2, D3, D4, D5, etc. are stored in the buffer memory of the buffer unit. Assuming that the preset order of the data segments is D0, D1, D2, D3, D4, D5, etc., when storing CW data, the data segments D0, D2, D4, D6, D8, etc. can be stored in the buffer memory corresponding to the storage channel CH0 in the buffer memory unit according to the preset order; and the data segments D1, D3, D5, D7, D9, etc. can be stored in the buffer memory corresponding to the storage channel CH1 in the buffer memory unit.

[0070] Similarly, assuming a memory chip incorporates four memory channels, CH0, CH1, CH2, and CH3, a CW data segment must correspond to memory channels CH0, CH1, CH2, and CH3. When the CW data is cached in the cache unit, the cache unit still splits the CW data into multiple 16-bit data segments (assuming the data line width of each memory channel is 8 bits), such as D0, D1, D2, D3, D4, D5, and so on. Assuming that the preset order of data is D0, D1, D2, D3, D4, D5..., therefore, when storing CW data, according to the preset order, the data segments D0, D4, D8... can be stored in the cache space corresponding to the storage channel CH0 in the cache unit; the data segments D1, D5, D9... can be stored in the cache space corresponding to the storage channel CH1 in the cache unit; the data segments D2, D6, D10... can be stored in the cache space corresponding to the storage channel CH1 in the cache unit; and the data segments D3, D7, D11... can be stored in the cache space corresponding to the storage channel CH1 in the cache unit.

[0071] It should be understood that the length of each data segment after a CW data is split is related to the data line width of each storage channel in the first associated storage channel. When transmitting data, a storage channel can transmit different data on the rising and falling edges of a clock cycle. That is, the length of data that can be transmitted by a storage channel in a clock cycle is twice the data line width of the storage channel. Therefore, when CW data is split into multiple data segments, the length of each data segment can be twice the data line width of the corresponding storage channel. Assuming the data line width of a storage channel is 8 bits, a data segment of CW data transmitted through the storage channel can be 16 bits.

[0072] Accordingly, assuming that the data line widths of the various storage channels of the first associated storage channel are inconsistent, when a CW data is split, the CW data can be split into multiple data segments of inconsistent lengths, and the length of each data segment is determined by the data line width of the storage channel that transmits the data segment.

[0073] When the controller is used to write data to the first flash memory medium through the first associated storage channel, the alignment control unit is used to cyclically obtain data segments in M ​​cache spaces corresponding to M storage channels in the first associated storage channel in a preset order, and send them to the M storage channels in the first associated storage channel respectively, so that the first data is written to the first flash memory medium.

[0074] by Figure 4 Taking the data storage format of the cache unit in the memory chip shown as an example, when the controller in the memory chip writes data to the first flash memory medium via the first associated storage channel, the alignment control unit alternately reads 16-bit data segments from the cache space corresponding to storage channels CH0 and CH1, and sends them to storage channels CH0 and CH1, respectively, so that the corresponding data is written to the first flash memory medium. In other words, the alignment control unit sequentially reads data segments D0, D2, D4, etc. from the cache space corresponding to storage channel CH0 and sends them to storage channel CH0; the alignment control unit sequentially reads data segments D1, D3, D5, etc. from the cache space corresponding to storage channel CH1 and sends them to storage channel CH1.

[0075] Similarly, assuming that the first associated storage channel includes storage channel CH0, storage channel CH1, storage channel CH2, and storage channel CH3, when the controller in the memory chip writes data to the first flash memory medium through the first associated storage channel, the alignment control unit can sequentially obtain corresponding data segments from the cache spaces corresponding to storage channels CH0, CH1, CH2, and CH3 in a preset order, and send them to storage channels CH0, CH1, CH2, and CH3, respectively, so that the corresponding data is written to the first flash memory medium. That is to say, the alignment control unit sequentially reads data segments such as D0, D4, D8, etc. from the cache space corresponding to the storage channel CH0, and sends them to the storage channel CH0; the alignment control unit sequentially reads data segments such as D1, D5, D9, etc. from the cache space corresponding to the storage channel CH1, and sends them to the storage channel CH1; the alignment control unit sequentially reads data segments such as D2, D6, D10, etc. from the cache space corresponding to the storage channel CH2, and sends them to the storage channel CH2; the alignment control unit sequentially reads data segments such as D3, D7, D11, etc. from the cache space corresponding to the storage channel CH3, and sends them to the storage channel CH3.

[0076] The following is an illustration of a controller for reading data from a first flash memory medium via a first associated storage channel.

[0077] When the controller is used to read data from the first flash memory medium through the first associated storage channel, the cache unit is used to obtain second data from M storage channels in the first associated storage channel respectively, and cache them in M ​​cache spaces corresponding to the M storage channels in the first associated storage channel respectively; the second data is the data stored in the first flash memory medium.

[0078] Similar to how the controller writes data to the first flash memory medium via the first associated storage channel, assuming that the first associated storage channel includes storage channel CH0 and storage channel CH1, data obtained by the cache unit via storage channel CH0 is stored in the cache space corresponding to storage channel CH0, and data obtained by the cache unit via storage channel CH1 is stored in the cache space corresponding to storage channel CH1. Assuming that the first associated storage channel includes storage channels CH0, CH1, CH2, and CH3, similarly, data obtained by the cache unit via storage channel CH0 is stored in the cache space corresponding to storage channel CH0, data obtained by the cache unit via storage channel CH1 is stored in the cache space corresponding to storage channel CH1, data obtained by the cache unit via storage channel CH2 is stored in the cache space corresponding to storage channel CH2, and data obtained by the cache unit via storage channel CH3 is stored in the cache space corresponding to storage channel CH3.

[0079] When the controller reads data from the first flash memory medium via the first associated storage channel, the alignment control unit is configured to record the total length of the second data retrieved from the first associated storage channel and, when the total length of the retrieved second data reaches a preset length, send a first message to the cache unit. The first message indicates that the retrieved second data can be decoded. The cache unit is also configured to send decoded data. The decoded data is the second data retrieved by the cache unit. That is, when the cache unit retrieves data from the first flash memory medium via the first associated storage channel, the alignment control unit records the total length of the second data retrieved from the first associated storage channel. If the total length of the retrieved second data reaches a preset length, such as the length of one CW data (4KB), the decoder unit can decode the retrieved CW data (i.e., the second data), and the alignment control unit notifies the cache unit to send the decoded data. This ensures that the second data can be successfully decoded when it reaches the size of one CW data, completing the data read operation and ensuring correct data transmission, thereby improving the reliability of the memory chip.

[0080] Furthermore, when the cache unit transmits decoded data, it is further configured to, in a predetermined order, sequentially and cyclically retrieve fixed-length second data from the M cache spaces corresponding to the M storage channels in the first associated storage channel, and transmit the fixed-length second data to the decoding unit. This ensures that the decoded data transmitted to the decoding unit is in the correct order, resulting in accurate data. This improves the read and write performance of the memory chip, ensures data transmission accuracy while increasing read and write efficiency, and enhances the reliability of the memory chip.

[0081] by Figure 4 Taking the data storage format of the cache unit in the memory chip shown in the figure as an example, the cache unit sequentially and cyclically retrieves fixed-length second data from the two cache spaces corresponding to the two storage channels (CH0 and CH1) in the first associated storage channel in a predetermined order. The fixed-length second data is the length of data that can be transmitted in a single clock cycle of each storage channel (here, 16 bits is used as an example). The cache unit first reads data D0 from the cache space corresponding to storage channel CH0, then reads data D1 from the cache space corresponding to storage channel CH1, then reads data D2 from the cache space corresponding to storage channel CH0, and finally reads data D3 from the cache space corresponding to storage channel CH1, and so on.

[0082] Similarly, if the first associated storage channel includes four storage channels (CH0, CH1, CH2 and CH3), the decoding unit can read in the following order: read data D0, D1, D2, D3... etc. from the cache space corresponding to the storage channel CH0, the cache space corresponding to the storage channel CH1, the cache space corresponding to the storage channel CH2 and the cache space corresponding to the storage channel CH3 in sequence.

[0083] When the data of one coding block (ie, the length of one CW data) is read, the decoding unit may decode the received second data to complete data recovery.

[0084] The above is an explanation of how to access the first flash memory medium through the first associated storage channel in wide port mode. Different from wide port mode, in normal mode, please refer to Figure 3 , each storage channel is in an independent state, and the input and output pins of each storage channel are in an enabled state, that is, the DQ, DQS, RE, CE, ALE, CLE, and WEN pins are all enabled. If normal mode is used to read and write data in this memory chip, the first flash memory medium can be accessed through storage channel CH0, and the second flash memory medium can be accessed through storage channel CH1. The alignment control unit in the controller in this memory chip can be used only for instruction distribution, for example, distributing instructions to corresponding storage channels, such as storage channels CH0 and CH1.

[0085] It should be understood that the embodiment of the present application only describes how to access the first flash memory medium through the first associated storage channel. Accessing the corresponding flash memory medium through other associated storage channels in the first channel is similar and will not be repeated here.

[0086] Please refer to Figure 5 An embodiment of the present application also provides a method for accessing a storage device, wherein the storage device includes a storage chip and multiple flash memory media, wherein the storage chip includes a controller and multiple storage channels coupled to the controller, and the multiple flash memory media are coupled to the controller through the multiple storage channels.

[0087] The method comprises the following steps:

[0088] S501 : A controller determines an access mode for accessing a flash memory medium based on the number of multiple storage channels and the number of flash memory media coupled to the controller through the multiple storage channels.

[0089] The number of multiple storage channels coupled to the controller is X; the number of flash memory media coupled to the controller via the multiple storage channels is Y; both X and Y are positive integers. If X>Y, the access mode for accessing the flash memory media is wide-port mode.

[0090] In the above Figure 3 The memory chip shown illustrates how the controller determines the access mode for accessing the flash memory medium, which will not be described in detail here.

[0091] S502: If the access mode for accessing the flash memory medium is the wide-port mode, the controller merges the multiple storage channels into a first channel.

[0092] The first channel includes at least one associated storage channel, and the data line width of one associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2.

[0093] That is to say, the controller can merge all the storage channels into one or more associated storage channels. For example, if a memory chip includes 8 storage channels with a bit width of 8 bits, the 8 storage channels can be merged in pairs, that is, merged into 4 associated storage channels with a bit width of 16 bits each; it can also merge some of the storage channels into one or more associated storage channels. For example, if a memory chip includes 8 storage channels with a bit width of 8 bits, 4 of the 8 storage channels can be merged into a 32-bit associated storage channel, and the rest cannot be merged; or 4 of the 8 storage channels can be merged in pairs, that is, merged into 2 associated storage channels with a bit width of 16 bits each, and the rest cannot be merged.

[0094] In the above Figure 3The memory chip shown illustrates how to merge M memory channels among multiple memory channels into a first associated memory channel. The merging method of other associated memory channels included in the first channel is similar to that of the first associated memory channel, and therefore will not be described in detail here.

[0095] S503: The controller accesses the flash memory medium through the first channel.

[0096] Specifically, the controller accessing the flash memory medium through the first channel may include: the controller accessing the first flash memory medium through a first associated storage channel. The first associated storage channel is one of the associated storage channels in the first channel. The first flash memory medium is one of the flash memory media coupled to the controller through multiple storage channels. The number M of storage channels in the first associated storage channel satisfies the following relationship: M = (P / Q) * X; where P is the media capacity of the first flash memory medium; Q is the total media capacity of the flash memory media coupled to the controller through multiple storage channels; and X is the number of multiple storage channels coupled to the controller.

[0097] Furthermore, the controller accessing the first flash memory medium through the first associated storage channel may include: the controller writing data to the first flash memory medium through the first associated storage channel; and / or the controller reading data from the first flash memory medium through the first associated storage channel.

[0098] The controller includes an encoder, a decoder, a code word buffer, and an alignment controller. The encoder encodes the data to be stored into a CW data; the decoder decodes the CW data read from the flash memory medium to recover the data; the buffer caches the CW data; and the alignment controller aligns and maintains the order of the CW data in wide-port mode.

[0099] Figure 6 The interactive flow chart of the controller writing data to the first flash memory medium through the first associated storage channel in the embodiment of the present application is shown. Figure 6 , the controller writing data to the first flash memory medium through the first associated storage channel may include the following operations:

[0100] S601: The encoding unit sends first data to the cache unit.

[0101] Specifically, after the encoding unit completes the CW data encoding, it may send the CW data (ie, the first data) to the cache unit.

[0102] S602: The cache unit splits the first data into multiple data segments and caches the data segments in M ​​cache spaces corresponding to M storage channels in the first associated storage channel.

[0103] Specifically, the cache unit can split the received first data (i.e., a CW data) into multiple data segments, and then store the multiple data segments of the first data in a loop in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order. The preset order can be determined according to the number of the storage channel. For the specific storage method, please refer to the above Figure 3 The description of how the cache unit of the memory chip stores data is not repeated here.

[0104] S603: The cache unit notifies the alignment control unit to write the first data into the first flash memory medium.

[0105] S604: The alignment control unit reads first data from the cache unit.

[0106] S605: The alignment control unit sends a CLE / ALE instruction to the first associated memory channel.

[0107] Specifically, since only one of the first associated storage channels has its CLE and ALE signal input and output pins enabled, the alignment control unit only needs to send a CLE / ALE instruction to the storage channel with the CLE and ALE signal input and output pins enabled. The CLE / ALE instruction is used to indicate the type of the first data to be written to the first flash memory medium, that is, to determine whether the first data is an address, a command, or data.

[0108] S606: The first associated storage channel returns a CLE / ALE instruction response.

[0109] Specifically, after receiving the CLE / ALE instruction, the programmable timing generator (PTG) of one of the first associated storage channels may return an acknowledgment (ACK) indication to the alignment control unit.

[0110] S607: The first associated storage channel outputs the CLE / ALE timing sequence to the first flash memory medium.

[0111] Specifically, after the alignment control unit returns ACK, the programmable timing generator PTG in one of the first associated storage channels outputs CLE / ALE timing to the first flash memory medium to determine whether the first data being transmitted is an address, a command, or data.

[0112] S608: The alignment control unit outputs a direct memory access write operation (writeDMA) instruction to the first associated storage channel, and transmits the first data to the first associated storage channel.

[0113] Specifically, the alignment control unit reads data in step S604, and the alignment control unit transmits data to the first storage channel in step S608 in the following manner: the alignment control unit cyclically obtains the data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order, and sends them to the M storage channels in the first associated storage channel respectively, so that the first data is written into the first flash memory medium of the memory. Taking the first associated storage channel including two storage channels (CH0 and CH1) as an example, the alignment control unit will convert the first data read from the cache space corresponding to CH0 and CH1 into 16-bit data and output it alternately to CH0 and CH1, so that the first data is written into the first flash memory medium. For specific methods, please refer to Figure 3 In the memory chip shown, the content related to the alignment control unit writing the first data to the first flash memory medium through the first associated storage channel is not repeated here.

[0114] S609: The first associated storage channel outputs a DMA write operation sequence to the first flash memory medium and transmits the first data.

[0115] The PTG in the first associated storage channel outputs a timing sequence of a direct memory access write operation to the first flash memory medium and transmits the first data.

[0116] Specifically, when the first associated storage channel writes the first data to the first flash memory medium, the PTG of each storage channel in the first associated storage channel first outputs a DMA write operation timing to the first flash memory medium to transfer the first data. After the DMA write operation timing is generated, each storage channel in the first associated storage channel can then transfer the first data to the first flash memory medium, so that the first data is written to the first flash memory medium.

[0117] Figure 7 The interactive flow chart of the controller writing data to the first flash memory medium through the first associated storage channel in the embodiment of the present application is shown. Figure 7 , the controller may write data to the first flash memory medium through the first associated storage channel, and the following operations may be performed:

[0118] S701: The alignment control unit sends a CLE / ALE instruction to a first associated memory channel.

[0119] Specifically, since only one of the first associated storage channels has its CLE and ALE signal input and output pins enabled, the alignment control unit only needs to send a CLE / ALE instruction to the storage channel with the CLE and ALE signal input and output pins enabled. The CLE / ALE instruction is used to indicate the type of the second data read from the first flash memory medium, that is, to determine whether the second data is an address, a command, or data.

[0120] S702: The first associated storage channel returns a response to the CLE / ALE instruction.

[0121] Specifically, after receiving the CLE / ALE instruction, the programmable timing generator (PTG) of one of the first associated storage channels returns an acknowledgement (ACK) to the alignment control unit.

[0122] S703: The first associated storage channel outputs CLE / ALE timing to the first flash memory medium.

[0123] Specifically, after the alignment control unit returns ACK, the programmable timing generator PTG in one of the first associated storage channels outputs CLE / ALE timing to the first flash memory medium to determine whether the second data being transmitted is an address, a command, or data.

[0124] S704: The alignment control unit sends a direct memory access read operation (read DMA) instruction to the first associated storage channel.

[0125] S705: The first associated storage channel outputs a DMA read operation timing to the first flash memory medium.

[0126] S706: The first flash memory medium returns the second data to the cache unit.

[0127] Specifically, when the first flash memory medium returns the second data, it returns the second data through the M storage channels in the first associated storage channels. The cache unit obtains the second data from the M storage channels in the first associated storage channels respectively, and caches the second data in the M cache spaces corresponding to the M storage channels in the first associated storage channels respectively.

[0128] S707: The alignment control unit records the total length of the returned second data, and when the total length of the obtained second data reaches a preset length, sends the first information to the cache unit.

[0129] The first information is used to indicate that the acquired second data can be decoded. When the cache unit acquires data from the first flash memory medium via the first associated storage channel, the alignment control unit records the total length of the second data acquired from the first associated storage channel. If the total length of the acquired second data reaches a preset length, for example, the length of one CW data (4KB), the acquired CW data (i.e., the second data) can be decoded by the decoding unit, and the alignment control unit notifies the cache unit to send the decoded data (i.e., the first information). This allows the second data to be successfully decoded when it reaches the size of one CW data, completing the data read operation and ensuring correct data transmission, thereby improving the reliability of the memory chip.

[0130] S708: The cache unit sends the decoded data to the decoding unit.

[0131] The decoded data is the second data obtained by the cache unit. The cache unit sends the decoded data to the decoding unit, including: the cache unit obtains the second data of fixed length from the M cache spaces corresponding to the M storage channels in the first associated storage channel in a cycle according to a preset order. The cache unit sends the second data of fixed length to the decoding unit. How the cache unit obtains the second data of fixed length from the cache space can be referred to Figure 3 In the memory chip shown, the description of the cache unit obtaining the second data of fixed length is not repeated here. When the data of a coding block (ie, the length of a CW data) is read, the decoding unit decodes the received second data to complete data recovery.

[0132] It should be understood that the embodiment of the present application only describes how to access the first flash memory medium through the first associated storage channel. Accessing the corresponding flash memory medium through other associated storage channels in the first channel is similar and will not be repeated here.

[0133] Table 1

[0134]

[0135] For a storage device, its DMA read and write performance is related to the interface frequency and the data line width, that is, DMA read and write performance = frequency * width, so when the interface frequency remains unchanged, increasing the data line width can improve the DMA read and write performance. In the embodiment provided in the present application, the data line width can be increased by multiplexing idle storage channels, so that the DMA read and write performance is increased. For details, please refer to Table 1, which shows that in a storage device, when the total storage capacity remains unchanged, after the storage capacity of a single flash memory medium is increased, the number of flash memory media is reduced, so that each flash memory medium reuses an idle storage channel. When transmitting data with a page size of 18 kilobytes (KB), the reading performance is significantly improved after the storage channel data line width is expanded from 8 bits to 16 bits.

[0136] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0137] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0138] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0139] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0140] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0141] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0142] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory chip, characterized in that: include: a controller and a plurality of storage channels coupled to the controller; The controller is configured to determine an access mode for accessing the flash memory medium based on a number of the plurality of storage channels and a number of flash memory media coupled to the controller through the plurality of storage channels; The controller is further configured to, if the access mode is a wide-port mode, merge the multiple storage channels into a first channel; wherein the first channel includes at least one associated storage channel, and a data line width of the associated storage channel is N times that of a single storage channel, where N is a positive integer greater than or equal to 2; The controller is further configured to access the flash memory medium through the first channel.

2. The memory chip according to claim 1, wherein: The number of the plurality of storage channels coupled to the controller is X; the number of the flash memory media coupled to the controller through the plurality of storage channels is Y; X and Y are both positive integers; If X>Y, the access mode is wide-mouth mode.

3. The memory chip according to claim 1 or 2, wherein: The controller is further configured to access the flash memory medium through the multiple storage channels if the access mode is a normal mode.

4. The memory chip according to claim 1 or 2, wherein: The controller is further configured to access a first flash memory medium through a first associated storage channel; wherein the first associated storage channel is one of the first channels; and the first flash memory medium is one of the flash memory media; The number M of storage channels in the first associated storage channel satisfies the following relationship: M=(P / Q)*X; Wherein, P is the media capacity of the first flash memory medium; Q is the total media capacity of the flash memory medium coupled to the controller through the multiple storage channels; and X is the number of the multiple storage channels coupled to the controller.

5. The memory chip according to claim 4, wherein: The controller includes a cache unit and an alignment control unit; the cache unit includes a plurality of cache spaces, and the plurality of cache spaces correspond one-to-one to the plurality of storage channels in the memory chip respectively; The controller is configured to write data to the first flash memory medium through the first associated storage channel; The cache unit is configured to split the first data into multiple data segments, and cyclically store the multiple data segments of the first data in sequence according to a preset order in the M cache spaces corresponding to the M storage channels in the first associated storage channel; The alignment control unit is configured to cyclically obtain, in a preset order, data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channels, and send them to the M storage channels in the first associated storage channels, respectively, so that the first data is written to the first flash memory medium.

6. The memory chip according to claim 4, wherein: The controller includes a cache unit and an alignment control unit, the cache unit includes a plurality of cache spaces, and the plurality of cache spaces correspond one-to-one to the plurality of storage channels in the memory chip respectively; The controller is configured to read data from the first flash memory medium through the first associated storage channel; The cache unit is configured to obtain second data from M storage channels in the first associated storage channels, respectively, and cache the second data in the M cache spaces corresponding to the M storage channels in the first associated storage channels, respectively; wherein the second data is data stored in the first flash memory medium; The alignment control unit is configured to record a total length of the second data acquired from the first associated storage channel, and when the total length of the acquired second data reaches a preset length, send first information to the cache unit; wherein the first information is used to indicate that the acquired second data can be decoded; The cache unit is further configured to send decoded data; the decoded data is second data acquired by the cache unit.

7. The memory chip according to claim 6, wherein: The controller further includes a decoding unit; The cache unit is further configured to, in a preset order, cyclically obtain the second data of fixed length from the M cache spaces corresponding to the M storage channels in the first associated storage channels respectively; and send the second data of fixed length to the decoding unit.

8. A storage device, characterized in that: The device comprises a plurality of flash memory media and a memory chip according to any one of claims 1 to 6; the plurality of flash memory media are coupled to the controller via a plurality of memory channels in the memory chip.

9. A method for accessing a storage device, characterized in that: The storage device includes a storage chip and a plurality of flash memory media, the storage chip includes a controller and a plurality of storage channels coupled to the controller, and the plurality of flash memory media are coupled to the controller through the plurality of storage channels; The method comprises: The controller determines an access mode for accessing the flash memory medium based on the number of the plurality of storage channels and the number of flash memory media coupled to the controller through the plurality of storage channels; If the access mode is the wide-port mode, the controller merges the multiple storage channels into a first channel; wherein the first channel includes at least one associated storage channel, and a data line width of the associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2; The controller accesses the flash memory medium through the first channel.

10. The method according to claim 9, characterized in that The number of the plurality of storage channels coupled to the controller is X; the number of the flash memory media coupled to the controller through the plurality of storage channels is Y; X and Y are both positive integers; If X>Y, the access mode is wide-mouth mode.

11. The method according to claim 9 or 10, characterized in that If the access mode is a normal mode, the controller accesses the flash memory medium through the multiple storage channels.

12. The method according to claim 9 or 10, characterized in that The controller accesses the flash memory medium through the first channel, including: The controller accesses the first flash memory medium through a first associated storage channel; wherein the first associated storage channel is one of the associated storage channels in the first channel; and the first flash memory medium is one of the flash memory media; The number M of storage channels in the first associated storage channel satisfies the following relationship: M=(P / Q)*X, where P is the media capacity of the first flash memory medium; Q is the total media capacity of the flash memory medium coupled to the controller through the multiple storage channels; and X is the number of the multiple storage channels coupled to the controller.

13. The method according to claim 12, characterized in that The controller includes a cache unit and an alignment control unit; the cache unit includes a plurality of cache spaces, and the plurality of cache spaces correspond one-to-one to the plurality of storage channels in the memory chip respectively; The controller accesses the first flash memory medium through the first associated storage channel, including: The controller writes data to the first flash memory medium through the first associated storage channel; The cache unit splits the first data into multiple data segments; The cache unit stores the multiple data segments of the first data in a circular manner in the M cache spaces corresponding to the M storage channels in the first associated storage channel in accordance with a preset order; The alignment control unit cyclically obtains the data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channels in a preset order, and sends them to the M storage channels in the first associated storage channels respectively, so that the first data is written into the first flash memory medium.

14. The method according to claim 12, characterized in that The controller includes a cache unit and an alignment control unit. The cache unit includes a plurality of cache spaces. The plurality of cache spaces correspond one-to-one to a plurality of storage channels in the memory chip. The controller accesses the first flash memory medium through the first associated storage channel, including: The controller reads data from the first flash memory medium through the first associated storage channel; The cache unit obtains second data from M storage channels in the first associated storage channels, respectively, and caches the second data in the M storage channels in the first associated storage channels, respectively, in the M cache spaces corresponding thereto; the second data is data stored in the first flash memory medium; The alignment control unit records the total length of the second data acquired from the first associated storage channel, and when the total length of the acquired second data reaches a preset length, sends first information to the cache unit; the first information is used to indicate that the acquired second data can be decoded; The cache unit sends decoded data; the decoded data is second data acquired by the cache unit.

15. The method according to claim 14, characterized in that The controller further includes a decoding unit; the buffer unit sends the decoded data, including: The cache unit sequentially and cyclically obtains the second data of fixed length from the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order; The cache unit sends the second data of fixed length to the decoding unit.

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