A reset control method for a multi-board card control system

Abstract

The present invention relates to a reset control method for a multi-board control system, belonging to the technical field of control circuits. In the prior art, either it is complex or the main board does not have the ability to reset the slave boards. The control system provided by the present invention includes a main board and one or more slave boards. The main board includes an FPGA module, a power-on reset circuit, an external reset circuit, one or more interface circuits, a logic gate circuit, a monitoring circuit, and a microprocessor, which can achieve an orderly and reliable reset of the multi-board control system.

Description

Technical Field

[0001] The present invention belongs to the technical field of control circuits, and particularly relates to a reset control method for a multi-board control system. More typically, it is applicable to control systems composed of various multi-boards. Background Art

[0002] In a control system composed of multi-boards, the following problems often exist: (1) There are functions such as bus communication and control between the main board and the slave boards. Due to the complex design and composition of the main and slave boards, the reset loading times of each board after power-on are different. If the slave board has completed reset before the main board has completed reset loading, it may cause mis-triggering, mis-states, and mis-operations; (2) The main board does not have the ability to reset the slave boards. After the slave boards work abnormally, they do not have the ability to resume work through reset, or can only reset and initialize the boards by powering off and re-powering on the slave boards or even the entire system. However, implementing a separate power-off and re-power-on operation for the slave boards requires complex design and control of the power supply system, and the power-off and re-power-on operation for the entire system will interrupt the work of the main board and other normal slave boards, causing other losses. Summary of the Invention

[0003] In view of one or more of the above-mentioned defects or improvement requirements of the prior art, the present invention provides a reset control method for a multi-board control system. The reset control method includes a power-on reset control method and an external reset control method. The power-on reset control method includes the following steps.

[0004] Step S11: When the system is powered on, the power-on reset circuit of the main board outputs a signal to the FPGA module to make the FPGA module enter power-on loading; during the power-on loading process of the FPGA module, the FPGA module outputs a status signal and an external reset output signal to the logic gate circuit. The status signal is at a low level, the external reset output signal is kept at a high level, and the output signal of the logic gate circuit is at a low level.

[0005] Step S12: The monitoring circuit receives the output signal of the logic gate as an input signal. When the input signal is at a low level, the output signal of the monitoring circuit is a reset signal. After the output signal of the logic gate circuit becomes high level and after a delay of a certain time, the output signal of the monitoring circuit is a non-reset signal. The microprocessor and other circuits of the main board receive the output signal of the monitoring circuit.

[0006] Step S13: After the FPGA module has completed power-on loading, the status signal of the FPGA module becomes high level, then the output signal of the logic gate circuit becomes high level, and then the output signal of the monitoring circuit is a non-reset signal, completing the reset of the microprocessor and other circuits of the main board.

[0007] Step S14: The output signal of the monitoring circuit is connected to the FPGA module to realize the reset of the FPGA on the main board card;

[0008] Step S15: The FPGA module outputs a reset signal to the slave board card through the interface circuit. After the power-on reset of the main board card is completed, the reset control of the slave board card is released;

[0009] Step S16: If the power-on loading time of the slave board card is longer than that of the main board card, based on the specific power-on loading time of the slave board card, the microprocessor can issue a reset control signal to keep the reset signal corresponding to the slave board card in the reset state of the slave board card, or the FPGA module can directly control the reset signal corresponding to the slave board card to continue to be maintained until the reset time of the slave board card meets the requirements;

[0010] The external reset control method includes the following steps,

[0011] Step S21: After the external reset signal is processed by the external reset circuit, an external reset input signal is output to the FPGA module. In the scenario where external reset is allowed, the external reset lock signal remains in an invalid state, the external reset output signal output by the FPGA module is at a low level, and the logic gate output signal is at a low level through the logic gate circuit. Subsequently, the output signal of the monitoring circuit is a reset signal, and the microprocessor, other circuits, and FPGA module of the main board card receive the output signal of the monitoring circuit; According to the application scenario requirements, the main board card controls the state of the reset signal of the slave board card to control the reset or non-reset of the slave board card;

[0012] Step S22: After the external reset signal is withdrawn, the external reset output signal output by the FPGA module becomes high level, and then the logic gate circuit output signal becomes high level. After a delay of several times, the output signal of the monitoring circuit is a non-reset signal;

[0013] Step S23: In the scenario where external reset is not allowed, the microprocessor outputs an external reset lock signal to keep the external reset output signal output by the FPGA module at a high level.

[0014] Preferably, the monitoring circuit has a voltage monitoring function. When the power supply voltage VCC of the monitoring circuit is not established to an effective level, the output signal of the monitoring circuit is kept in a reset state. After the power supply voltage VCC is established to an effective level, the output signal of the monitoring circuit is controlled by the state of the input port of the monitoring circuit;

[0015] Preferably, the input port of the monitoring circuit is a manual reset input port;

[0016] Preferably, according to the differences in the active reset levels of the microprocessor, the other circuits, and the FPGA module, the output signal of the monitoring circuit can be connected to the microprocessor, the other circuits, and the FPGA module after passing through a logic NOT circuit to achieve reset.

[0017] Generally speaking, compared with the prior art, the beneficial effects of the above technical solutions conceived by the present invention include:

[0018] (1) The present invention provides a reset control method for a multi-board control system, which can achieve an orderly and reliable reset of the multi-board control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is an application diagram of a reset control method for a multi-board control system provided by the present invention.

[0020] In all the drawings, the same reference numerals represent the same technical features, specifically:

[0021] 1, main board card; 2, slave board card 1; 3, slave board card n; 4, logic gate circuit; 5, monitoring circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] A multi-board control system includes a main board card 1, a first slave board card 2, and an Nth slave board card 3. The main board card 1 includes an FPGA module, a power-on reset circuit, an external reset circuit, a plurality of interface circuits, a logic gate circuit 4, a monitoring circuit 5, a microprocessor, and other circuits;

[0024] The first slave board card 2 includes a controller, a power-on reset circuit, and an interface circuit. The Nth slave board card 3 has the same structure and / or composition as the first slave board card 2; the plurality of interface circuits of the main board card 1 are in one-to-one connection with the interface circuits of the plurality of slave board cards.

[0025] When the system is powered on:

[0026] (1) The power-on reset circuit of the main board card outputs a signal to the FPGA to enable the FPGA to enter power-on loading. During the power-on loading process of the FPGA, the FPGA status signal is at a low level, the external reset output signal is maintained at a high level, the FPGA status signal and the external reset output signal pass through the logic gate circuit, and the output signal of the logic gate circuit is at a low level;

[0027] (2) The monitoring circuit has a voltage monitoring function. Before the power supply voltage VCC of the monitoring circuit is established to the effective level, the output signal of the monitoring circuit is maintained in the reset state. After the power supply voltage VCC is established to the effective level, the output signal of the monitoring circuit is controlled by the state of the input port of the monitoring circuit;

[0028] (3) The input port of the monitoring circuit is a manual reset input port. When the output signal of the connected logic gate circuit is at a low level, the output signal is maintained in the reset state. After the output signal of the logic gate circuit becomes high level and after a certain delay, the output signal is in the non-reset state;

[0029] (4) After the FPGA on the main board card is powered on and loaded, the FPGA status signal becomes high level. Subsequently, the output signal of the logic gate circuit becomes high level, and then the output signal of the monitoring circuit is in the non-reset state, completing the reset of the microprocessor and other circuits on the main board card;

[0030] (5) The output signal of the monitoring circuit is connected to the FPGA to achieve the reset of the FPGA on the main board card;

[0031] (6) During the power-on loading process of the FPGA, multiple reset signals for the slave board cards are maintained in a state that keeps the slave board cards in the reset state. After the main board card completes the power-on reset, the reset control for the slave board cards is released;

[0032] (7) If the power-on loading time of the slave board card is longer than that of the main board card, based on knowing the specific power-on loading time of the slave board card, the main board card can send a reset control signal through the microprocessor to keep the reset signal corresponding to the slave board card in the reset state for the slave board card, or the FPGA can directly control the reset signal for the slave board card to continue to be maintained until the reset time of the slave board card meets the requirements;

[0033] During external reset:

[0034] (1) When the external reset signal is valid, after being processed by the external reset circuit on the main board card, the external reset input signal is output to the FPGA. In a scenario where external reset is allowed, the external reset lock signal remains in the invalid state, the FPGA outputs an external reset output signal at a low level, and through the logic gate circuit, the logic gate output signal becomes low level, and then the output signal of the monitoring circuit is in the reset state;

[0035] (2) After the external reset signal is revoked, the external reset output signal output by the FPGA becomes high level. Subsequently, the output signal of the logic gate circuit becomes high level, and after a certain delay, the reset state of the output signal of the monitoring circuit is revoked;

[0036] (3) During external reset, according to the needs of the application scenario, the main board card can control the state of the reset signal for the slave board card to control whether the slave board card is reset or not;

[0037] (4) In a scenario where external reset is not allowed, the external reset lock signal remains in an active state, keeping the external reset output signal output by the FPGA at a high level and not responding to the external reset input signal.

[0038] After power-on and when it is necessary to reset the slave board:

[0039] After power-on and when it is found that the slave board is malfunctioning or when it is necessary to reset the slave board for other reasons, the main board microprocessor sends a corresponding reset control signal to the FPGA, and the FPGA controls the corresponding slave board reset signal to the reset state of the slave board to achieve the reset of the slave board.

[0040] According to the difference in the reset active levels of each chip on the main board, the output signal of the monitoring circuit can be connected to a specific chip after passing through a logic NOT circuit to achieve reset.

[0041] According to the difference in the reset active levels of each chip on the slave board, the slave board reset signal output by the main board can be connected to a specific chip after being processed by an interface circuit to achieve reset.

[0042] The reset control signal sent by the main board microprocessor to the FPGA can be single-channel or multi-channel, and can be an IO signal or other control methods such as instruction control;

[0043] The reset signal of the main board to the slave board can be single-channel or multi-channel; it can be a single-ended signal such as an IO signal or a differential signal with stronger anti-interference performance, etc., and the specific conversion is performed by the interface circuit;

[0044] The external reset lock signal sent by the main board microprocessor to the FPGA can be an IO signal or other control methods such as instruction control;

[0045] The FPGA shown in this article is an example of a programmable logic control device, and it can also be other controllers with corresponding functions;

[0046] Those skilled in the art can easily understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A reset control method for a multi-board control system, characterized in that, the system includes a main board card and one or more slave board cards. The main board card includes an FPGA module, a power-on reset circuit, an external reset circuit, one or more interface circuits, a logic gate circuit, a monitoring circuit, and a microprocessor; the reset control method includes a power-on reset control method and an external reset control method. The power-on reset control method includes the following steps, Step S11: When the system is powered on, the power-on reset circuit outputs a signal to the FPGA module to make the FPGA module enter power-on loading; during the power-on loading process of the FPGA module, the FPGA module outputs a status signal and an external reset output signal to the logic gate circuit. The status signal is at a low level, keeping the external reset output signal at a high level, and the output signal of the logic gate circuit is at a low level; Step S12: The monitoring circuit receives the output signal of the logic gate as an input signal. When the input signal is at a low level, the output signal of the monitoring circuit is a reset signal. After the output signal of the logic gate circuit becomes high level and after a delay of a certain time, the output signal of the monitoring circuit is a non-reset signal. The microprocessor receives the output signal of the monitoring circuit; Step S13: After the FPGA module finishes power-on loading, the status signal of the FPGA module becomes high level, then the output signal of the logic gate circuit becomes high level, and then the output signal of the monitoring circuit is a non-reset signal, completing the reset of the microprocessor; Step S14: The output signal of the monitoring circuit is connected to the FPGA module to achieve the reset of the FPGA; Step S15: The FPGA module outputs a reset signal to the slave board card through the interface circuit. After the main board card completes power-on reset, the reset control of the slave board card is released; Step S16: If the power-on loading time of the slave board card is longer than that of the main board card, based on knowing the specific power-on loading time of the slave board card, the microprocessor can issue a reset control signal to keep the reset signal corresponding to the slave board card in the reset state of the slave board card, or the FPGA module can directly control the reset signal corresponding to the slave board card to continue to be maintained until the reset time of the slave board card meets the requirements; the external reset control method includes the following steps, Step S21: After the external reset signal is processed by the external reset circuit, an external reset input signal is output to the FPGA module. In a scenario where external reset is allowed, the external reset lock signal remains in an invalid state. The FPGA module outputs an external reset output signal at a low level, which makes the output signal of the logic gate at a low level through the logic gate circuit, and then the output signal of the monitoring circuit is a reset signal. The microprocessor and the FPGA module receive the output signal of the monitoring circuit; according to the needs of the application scenario, the main board card controls the state of the reset signal of the slave board card to control the reset or non-reset of the slave board card; Step S22: After the external reset signal is revoked, the external reset output signal output by the FPGA module becomes high level. Subsequently, the output signal of the logic gate circuit becomes high level. After a delay of several time periods, the output signal of the monitoring circuit is a non-reset signal; Step S23: In a scenario where external reset is not allowed, the microprocessor outputs an external reset lock signal to keep the external reset output signal output by the FPGA module at high level.

2. The method according to claim 1, characterized in that: the monitoring circuit has a voltage monitoring function. Before the power supply voltage VCC of the monitoring circuit is established to an effective level, the output signal of the monitoring circuit is kept in a reset state. After the power supply voltage VCC is established to the effective level, the output signal of the monitoring circuit is controlled by the state of the input port of the monitoring circuit.

3. The method according to claim 1, characterized in that: the input port of the monitoring circuit is a manual reset input port.

4. The method according to claim 1, characterized in that: According to the difference in the reset effective levels of the microprocessor and the FPGA module, the output signal of the monitoring circuit can be connected to the microprocessor and the FPGA module after passing through a logic NOT circuit to achieve reset.

5. The method according to claim 1, characterized in that: the main board card includes other circuits; in step S12, after a delay of several time periods, the output signal of the monitoring circuit is a non-reset signal, and the microprocessor and the other circuits receive the output signal of the monitoring circuit.

6. The method according to claim 5, characterized in that: in step S13, subsequently, the output signal of the monitoring circuit is a non-reset signal, completing the reset of the microprocessor and other circuits of the main board card.

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