Wafer notch screening method and apparatus, and nonvolatile storage medium

Abstract

The application discloses a wafer gap screening method and device and a nonvolatile storage medium. The method comprises the following steps: acquiring an edge image of a pre-alignment wafer, processing the edge image of the pre-alignment wafer, and obtaining a first target image comprising a suspected wafer gap; determining a gap correction graph according to the size of the suspected wafer gap in the first target image, converting the suspected wafer gap in the first target image to the gap correction graph, and obtaining a second target image; removing an abnormal wafer gap in the suspected wafer gap in the second target image, and obtaining a target wafer gap. The application solves the technical problem that the wafer position cannot be accurately determined due to the fact that the prior art cannot effectively screen the tiny wafer gap in the linear array image.

Description

Technical Field

[0001] This application relates to the field of wafer positioning, and more specifically, to a method and apparatus for screening wafer notches and a non-volatile storage medium. Background Technology

[0002] In wafer fabrication, one step involves cutting a notch in the silicon wafer ingot. A flat notch is called a flat notch, but to reduce wafer waste, a small circular notch, called a V-groove, is typically cut. In subsequent wafer fabrication processes, this notch is used to determine the wafer's placement, facilitating dicing and testing. In wafer testing, a pre-alignment step is performed before wafer mounting to correct the wafer's position and identify its ID. Therefore, this step requires locating and identifying the wafer's notch.

[0003] Existing methods for identifying wafer notches using linear array images involve traversing the edges of a pre-aligned wafer image and determining whether a notch is present based on the depth of the defect. However, a drawback of linear array images is the presence of light spots at the wafer edges, which exhibit a bright characteristic similar to notches in the linear array image. Flat notches are relatively easy to distinguish from light spots due to their larger size, but small notches, due to their small size, are frequently misidentified or not detected if there is interference from light spots at the wafer edges. This can lead to equipment failure to mount the wafer or significant mounting deviations, affecting subsequent testing. Therefore, it is necessary to screen small notches to ensure they can be distinguished from light spots in the linear array image. However, currently, there is no publicly available wafer notch screening method that can effectively screen small notches in linear array images.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This application provides a method and apparatus for screening wafer notches, as well as a non-volatile storage medium, to at least solve the technical problem of inaccurate wafer location determination caused by the inability of existing technologies to effectively screen for tiny wafer notches in linear array images.

[0006] According to one aspect of the embodiments of this application, a method for screening wafer notches is provided, comprising: acquiring an edge image of a pre-aligned wafer, and processing the edge image of the pre-aligned wafer to obtain a first target image including a suspected wafer notch; determining a notch correction image based on the size of the suspected wafer notch in the first target image, and converting the suspected wafer notch in the first target image to the notch correction image to obtain a second target image; removing abnormal wafer notches from the suspected wafer notches in the second target image to obtain a target wafer notch.

[0007] Optionally, removing the abnormal wafer gap from the suspicious wafer gap in the second target image includes: removing the first abnormal wafer gap from the suspicious wafer gap in the second target image based on the depth and length of the suspicious wafer gap in the second target image to obtain a third target image, wherein the depth of the suspicious wafer gap is the height of the second target image, and the length of the suspicious wafer gap is the width of the second target image; and determining the remaining suspicious wafer gap in the third target image as the first target wafer gap.

[0008] Optionally, based on the depth and length of the suspicious wafer notches in the second target image, removing the first abnormal wafer notch from the suspicious wafer notches in the second target image includes: identifying suspicious wafer notches in the second target image that do not meet preset screening conditions as the first abnormal wafer notch, wherein the preset screening conditions include: the depth of the suspicious wafer notch is less than the preset maximum depth value of the target wafer notch, the depth of the suspicious wafer notch is greater than the preset minimum depth value of the target wafer notch, the length of the suspicious wafer notch is less than the preset maximum length value of the target wafer notch, the length of the suspicious wafer notch is greater than the preset minimum length value of the target wafer notch, the area of ​​the suspicious wafer notch is greater than the preset minimum area of ​​the target wafer notch, and the ratio of the length of the suspicious wafer notch to the depth of the suspicious wafer notch is less than the ratio of the length of the target wafer notch to the depth of the wafer notch; deleting the first abnormal wafer notch from the suspicious wafer notches in the second target image.

[0009] Optionally, after determining the remaining suspicious wafer gaps in the third target image as the first target wafer gap, the method further includes: determining whether the first target wafer gap meets a first preset condition, wherein the first preset condition is: the number of first target wafer gaps is 1, or when the number of first target wafer gaps is 2, the longitudinal distance between the two wafer gaps included in the first target wafer gap exceeds a preset target longitudinal distance; if the first target wafer gap meets the first preset condition, the first target wafer gap is determined as a target wafer gap; if the first target wafer gap does not meet the first preset condition, the second abnormal wafer gap in the suspicious wafer gaps in the third target image is removed.

[0010] Optionally, determining the first target wafer notch as the target wafer notch includes: if the first preset condition is that the number of the first target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds the preset target longitudinal distance, the wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the first target wafer notch is determined as the target wafer notch.

[0011] Optionally, removing the second abnormal wafer gap from the suspicious wafer gaps in the third target image includes: dividing the third target image into a first sub-image and a second sub-image, wherein the height of the first sub-image is the same as the height of the second sub-image, and the width of the first sub-image is the same as the width of the second sub-image; performing a mirror flip operation on either the first sub-image or the second sub-image to obtain a first target sub-image; performing an XOR operation on the first target sub-image and the second target sub-image to obtain an image after the XOR operation, wherein the second target sub-image is the sub-image that has not undergone the mirror flip operation; determining the pixel area of ​​the XOR region in the image after the XOR operation; removing the second abnormal wafer gap from the suspicious wafer gaps in the third target image based on the pixel area of ​​the XOR region to obtain a fourth target image; and identifying the remaining suspicious wafer gaps in the fourth target image as the second target wafer gap.

[0012] Optionally, removing the second abnormal wafer gap from the suspicious wafer gaps in the third target image based on the pixel area of ​​the XOR region to obtain the fourth target image includes: determining the pixel area of ​​the suspicious wafer gap in the third target image; determining the symmetry of the suspicious wafer gap in the third target image based on the pixel area of ​​the XOR region and the pixel area of ​​the suspicious wafer gap in the third target image; identifying suspicious wafer gaps in the third target image whose symmetry is less than a preset target symmetry as the second abnormal wafer gap; and removing the second abnormal wafer gap from the suspicious wafer gaps in the third target image to obtain the fourth target image.

[0013] Optionally, after determining the remaining suspicious wafer gaps in the fourth target image as the second target wafer gap, the method further includes: determining whether the second target wafer gap meets a second preset condition, wherein the second preset condition is: the number of second target wafer gaps is 1, or when the number of second target wafer gaps is 2, the longitudinal distance between the two wafer gaps included in the second target wafer gap exceeds a preset target longitudinal distance; if the second target wafer gap meets the second preset condition, the second target wafer gap is determined as a target wafer gap; if the second target wafer gap does not meet the second preset condition, the third abnormal wafer gap in the suspicious wafer gaps in the fourth target image is removed.

[0014] Optionally, if the second preset condition is that the number of second target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the second target wafer notches exceeds the preset target longitudinal distance, determining the second target wafer notch as a target wafer notch includes: determining the wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the second target wafer notch as the target wafer notch.

[0015] Optionally, removing the third abnormal wafer gap from the suspicious wafer gap in the fourth target image includes: determining the parabolic function corresponding to the suspicious wafer gap contour in the fourth target image; removing the third abnormal wafer gap from the suspicious wafer gap in the fourth target image based on the parabolic function corresponding to the suspicious wafer gap contour, and determining the third target wafer gap.

[0016] Optionally, determining the parabolic function corresponding to the suspicious wafer notch contour in the fourth target image includes: determining the suspicious wafer notch contour image corresponding to the suspicious wafer notch contour; removing the bottom straight line of the suspicious wafer notch contour from the suspicious wafer notch contour image to obtain the target suspicious wafer notch contour image; determining the contour calculation points of the suspicious wafer notch contour in the target suspicious wafer notch contour image; obtaining the first abscissa and the first ordinate of the contour calculation points of the suspicious wafer notch contour, and transforming the first ordinate of the contour calculation points according to the height of the target suspicious wafer notch contour image to obtain the target ordinate of the contour calculation points; and fitting a parabolic function based on the first abscissa and the target ordinate.

[0017] Optionally, based on the parabolic function corresponding to the suspicious wafer notch contour, the third abnormal wafer notch in the fourth target image is removed to determine the third target wafer notch, including: substituting the first abscissa into the parabolic function to solve, and determining the solution as the second ordinate; determining the similarity deviation value between the first ordinate and the second ordinate, wherein the similarity deviation value is the average of the differences between the first ordinate and the second ordinate; identifying the suspicious wafer notch in the fourth target image whose similarity deviation value is greater than the preset target similarity deviation value as the third abnormal wafer notch; removing the third abnormal wafer notch from the suspicious wafer notches in the fourth target image to obtain the third target wafer notch.

[0018] Optionally, after determining the third target wafer notch, the method further includes: determining whether the third target wafer notch meets a third preset condition, wherein the third preset condition is: the number of third target wafer notches is 1, or when the number of third target wafer notches is 2, the longitudinal distance between the two wafer notches included in the third target wafer notch exceeds a preset target longitudinal distance; if the third target wafer notch meets the third preset condition, the third target wafer notch is determined to be a target wafer notch; if the third target wafer notch does not meet the third preset condition, an alarm message is generated.

[0019] Optionally, if the third preset condition is that the number of third target wafer gaps is 2, and the longitudinal distance between the two wafer gaps included in the third target wafer gap exceeds the preset target longitudinal distance, the third target wafer gap is determined as the target wafer gap, including: determining the wafer gap that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer gaps included in the second target wafer gap as the target wafer gap.

[0020] Optionally, the edge image of the pre-aligned wafer is processed to obtain a first target image including a suspected wafer notch, including: traversing the edge image of the pre-aligned wafer to determine the position of the suspected wafer notch in the edge image of the pre-aligned wafer; determining the first image based on the position of the suspected wafer notch; performing binarization processing on the first image to obtain a second image; filling the recessed portion of the edge contour of the suspected wafer notch in the second image to obtain a third image; determining a fourth image based on the second image and the third image; and performing deburring processing on the fourth image to determine the first target image.

[0021] Optionally, before determining the notch correction image based on the size of the suspected wafer notch in the first target image, the method further includes: determining a target bounding box for the suspected wafer notch in the first target image, wherein the target bounding box is the smallest rectangle surrounding the suspected wafer notch; determining the corner coordinates of the suspected wafer notch in the first target image based on the target bounding box; and determining the height and width of the suspected wafer notch in the first target image based on the corner coordinates.

[0022] Optionally, determining the notch correction pattern based on the size of the suspected wafer notch in the first target image includes: determining the height of the suspected wafer notch in the first target image as the width of the notch correction pattern; determining the width of the suspected wafer notch in the first target image as the height of the notch correction pattern; and determining the notch correction pattern based on the width and height of the notch correction pattern.

[0023] Optionally, converting the suspected wafer notch in the first target image to a notch correction image to obtain a second target image includes: converting the suspected wafer notch in the first target image to a notch correction image to obtain a fifth image; filling the recessed portion of the edge contour of the suspected wafer notch in the fifth image to obtain the second target image.

[0024] Optionally, converting the suspicious wafer notch in the first target image to a notch correction image to obtain the second target image includes: transforming the suspicious wafer notch in the first target image into a notch correction image to obtain the second target image.

[0025] According to another aspect of the embodiments of this application, a non-volatile storage medium is also provided, the storage medium including a stored program, wherein the program, when running, controls the device where the storage medium is located to execute the above-described wafer notch screening method.

[0026] According to another aspect of the embodiments of this application, an electronic device is also provided, including: a memory and a processor, the processor being configured to run a program stored in the memory, wherein the program executes the above-described wafer notch screening method during runtime.

[0027] In this embodiment, an edge image of a pre-aligned wafer is acquired and processed to obtain a first target image including a suspected wafer notch. A notch correction image is determined based on the size of the suspected wafer notch in the first target image, and the suspected wafer notch in the first target image is converted to the notch correction image to obtain a second target image. Abnormal wafer notches in the suspected wafer notches in the second target image are removed to obtain the target wafer notch. By removing abnormal wafer notches in the suspected wafer notches, the purpose of screening for tiny wafer notches in the linear array image is achieved, thereby realizing the technical effect of accurately determining the wafer position. This solves the technical problem of inaccurate wafer position determination caused by the inability of existing technology to effectively screen for tiny wafer notches in linear array images. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1 This is a flowchart of a wafer notch screening method according to an embodiment of this application;

[0030] Figure 2 This is a flowchart illustrating the processing of an edge image of a pre-aligned wafer according to an embodiment of this application;

[0031] Figure 3a This is a flowchart illustrating the determination of a notch correction diagram according to an embodiment of this application;

[0032] Figure 3b This is a flowchart illustrating the determination of a suspicious wafer notch size according to an embodiment of this application;

[0033] Figure 4 This is a flowchart illustrating the determination of a second target image according to an embodiment of this application;

[0034] Figure 5a This is a flowchart illustrating the process of removing abnormal wafer gaps from suspicious wafer gaps in a second target image according to an embodiment of this application;

[0035] Figure 5b This is a flowchart illustrating the process of determining a target wafer notch and removing abnormal wafer notches according to an embodiment of this application;

[0036] Figure 6a This is a flowchart illustrating a method for removing a second abnormal wafer gap from a suspicious wafer gap in a third target image, according to an embodiment of this application.

[0037] Figure 6b This is a flowchart illustrating the determination of a fourth target image according to an embodiment of this application;

[0038] Figure 6c This is another flowchart of determining the target wafer notch and removing abnormal wafer notches according to an embodiment of this application;

[0039] Figure 7a This is a flowchart illustrating the process of removing a third abnormal wafer gap from a suspicious wafer gap in a fourth target image, according to an embodiment of this application.

[0040] Figure 7b This is a flowchart illustrating a method for determining the parabolic function corresponding to the profile of a suspicious wafer notch in a fourth target image, according to an embodiment of this application.

[0041] Figure 7c This is a flowchart illustrating the determination of a third target wafer notch according to an embodiment of this application;

[0042] Figure 7d This is another flowchart of determining the target wafer notch and removing abnormal wafer notches according to an embodiment of this application;

[0043] Figure 8a This is a flowchart of another wafer notch screening method according to an embodiment of this application;

[0044] Figure 8b This is a flowchart of another wafer notch screening method according to an embodiment of this application;

[0045] Figure 8c This is a flowchart of another wafer notch screening method according to an embodiment of this application;

[0046] Figure 9a This is a schematic diagram of the edge image of a pre-aligned wafer according to an embodiment of this application;

[0047] Figure 9b This is a schematic diagram of a suspected wafer notch image according to an embodiment of this application;

[0048] Figure 9c This is a schematic diagram of another suspected wafer notch image according to an embodiment of this application;

[0049] Figure 9d This is a schematic diagram of another suspected wafer notch image according to an embodiment of this application;

[0050] Figure 9e This is a schematic diagram of another suspected wafer notch image according to an embodiment of this application;

[0051] Figure 9f This is a schematic diagram of another suspected wafer notch image according to an embodiment of this application;

[0052] Figure 10a This is a schematic diagram of a notch correction diagram according to an embodiment of this application;

[0053] Figure 10b This is a schematic diagram of another notch correction diagram according to an embodiment of this application;

[0054] Figure 11a This is a schematic diagram of the left half of a suspected wafer notch according to an embodiment of this application;

[0055] Figure 11b This is a schematic diagram of the right half of a suspected wafer notch according to an embodiment of this application;

[0056] Figure 11c This is a schematic diagram of the right half of a mirrored image of a suspected wafer notch according to an embodiment of this application;

[0057] Figure 11d This is a schematic diagram of an image after an XOR operation on the left and right sides of a suspected wafer notch according to an embodiment of this application;

[0058] Figure 12a This is a schematic diagram of a corrected suspicious wafer notch outline image according to an embodiment of this application;

[0059] Figure 12b This is a schematic diagram of another corrected suspicious wafer notch contour image according to an embodiment of this application;

[0060] Figure 13 This is a structural diagram of a wafer notch screening device according to an embodiment of this application;

[0061] Figure 14 This is a hardware structure block diagram of a computer terminal (or electronic device) for a wafer notch screening method provided in an embodiment of this application. Detailed Implementation

[0062] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0063] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] In related technologies, linear sensors are used to identify wafer notches. While linear sensors offer high positioning accuracy, they cannot identify wafer identification numbers (IDs). Using a line scan camera can integrate notch identification and wafer ID recognition, thereby saving probe station space and improving testing efficiency. However, related wafer notch identification based on line scan images does not effectively filter wafer notches, resulting in the inability to locate wafer notches in line scan images interfered with by edge spots (caused by dirt, wear, etc.). To address this issue, this application provides a related solution, which is detailed below.

[0065] According to an embodiment of this application, a method embodiment for screening wafer notches is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0066] Figure 1 This is a flowchart of a wafer notch screening method according to an embodiment of this application, such as... Figure 1 As shown, the method includes the following steps:

[0067] Step S102: Obtain the edge image of the pre-aligned wafer and process the edge image of the pre-aligned wafer to obtain a first target image including the suspected wafer notch.

[0068] The probe station is scanned using a linear scan camera to acquire edge images of the pre-aligned wafer. These edge images are shown below. Figure 9a As shown, the edge image of the pre-aligned wafer is processed, wherein, Figure 2 This is a flowchart illustrating the processing of an edge image of a pre-aligned wafer according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0069] Step S202: Traverse the edge image of the pre-aligned wafer to determine the location of the suspicious wafer gap in the edge image of the pre-aligned wafer.

[0070] Step S204: Determine the first image based on the location of the suspected wafer notch.

[0071] Suspicious wafer notches are initially located by traversing rows of pixels in the edge image of the pre-aligned wafer. A local area at the initially located suspected wafer notch is then cropped to determine the first image.

[0072] Step S206: Binarize the first image to obtain the second image.

[0073] The first image is binarized to obtain a second image, which contains only black and white components. The second image is shown below. Figure 9b As shown, in Figure 9b In the diagram, the white component represents the wafer portion, and the black component represents the non-wafer portion.

[0074] Step S208: Fill in the recessed portion of the edge contour of the suspected wafer notch in the second image to obtain the third image.

[0075] First, extract the protruding portion and the concave portion of the edge contour of the suspected wafer notch in the second image. The extracted image is as follows. Figure 9c As shown, the protruding portion of the edge contour of the suspected wafer notch in the second image is removed, and the concave portion of the edge contour of the suspected wafer notch in the second image is filled to obtain the third image, wherein the third image is as follows. Figure 9d As shown.

[0076] Step S210: Determine the fourth image based on the second and third images.

[0077] By removing the overlapping portion between the third and second images from the third image, a fourth image is obtained, as shown in the image below. Figure 9e As shown.

[0078] Step S212: Deburring is performed on the fourth image to determine the first target image.

[0079] The fourth image is subjected to lateral deburring to remove fine line interference, and the first target image is finally determined, wherein the first target image is as follows. Figure 9f As shown.

[0080] Step S104: Determine the notch correction image based on the size of the suspected wafer notch in the first target image, and convert the suspected wafer notch in the first target image to the notch correction image to obtain the second target image.

[0081] Figure 3a A flowchart for determining a notch correction diagram according to an embodiment of this application is shown below. Figure 3a As shown, the process includes the following steps:

[0082] Step S302: The height of the suspicious wafer notch in the first target image is determined as the width of the notch correction image.

[0083] Step S304: The width of the suspected wafer notch in the first target image is determined as the height of the notch correction image.

[0084] Step S306: Determine the notch correction diagram based on the width and height of the notch correction diagram.

[0085] Figure 3b This is a flowchart illustrating the determination of a suspicious wafer notch size according to an embodiment of this application, such as... Figure 3b As shown, the process includes the following steps:

[0086] Step S3011: Determine the target bounding box of the suspected wafer notch in the first target image, wherein the target bounding box is the smallest rectangle that surrounds the suspected wafer notch.

[0087] Understandably, the target bounding box is a rectangle that can enclose the suspicious wafer gap with the smallest possible area.

[0088] Step S3012: Determine the corner coordinates of the suspicious wafer notch in the first target image based on the target bounding box.

[0089] The target bounding box is a rectangle with a regular shape, which makes it easy to determine the corner coordinates of the target bounding box. The target bounding box is also the smallest rectangle that surrounds the suspected wafer notch. Therefore, the corner coordinates of the target bounding box can be approximated as the corner coordinates of the suspected wafer notch.

[0090] Step S3013: Determine the height and width of the suspicious wafer notch in the first target image based on the corner coordinates.

[0091] Figure 4 A flowchart for determining a second target image according to an embodiment of this application is shown below. Figure 4 As shown, the process includes the following steps:

[0092] Step S402: Convert the suspicious wafer notch in the first target image to a notch correction image to obtain the fifth image.

[0093] The four corner points of the suspected wafer notch in the first target image are converted to the notch correction image to obtain the fifth image, where the fifth image is as follows. Figure 10a As shown.

[0094] Step S404: Fill in the recessed portion of the edge contour of the suspected wafer notch in the fifth image to obtain the second target image.

[0095] Figure 10b This is a schematic diagram of another notch correction diagram according to an embodiment of this application, wherein the second target image is as follows. Figure 10b As shown.

[0096] Step S106: Remove the abnormal wafer gap from the suspicious wafer gap in the second target image to obtain the target wafer gap.

[0097] Figure 5a A flowchart of removing abnormal wafer gaps from suspicious wafer gaps in a second target image according to an embodiment of this application is shown below. Figure 5a As shown, the process includes the following steps:

[0098] Step S502: Based on the depth and length of the suspicious wafer gap in the second target image, remove the first abnormal wafer gap from the suspicious wafer gap in the second target image to obtain the third target image, wherein the depth of the suspicious wafer gap is the height of the second target image, and the length of the suspicious wafer gap is the width of the second target image.

[0099] According to an optional embodiment of this application, suspicious wafer notches in the second target image that do not meet preset screening conditions are identified as first abnormal wafer notches. The preset screening conditions include: the depth of the suspicious wafer notch is less than a preset maximum depth value for target wafer notches; the depth of the suspicious wafer notch is greater than a preset minimum depth value for target wafer notches; the length of the suspicious wafer notch is less than a preset maximum length value for target wafer notches; the length of the suspicious wafer notch is greater than a preset minimum length value for target wafer notches; the area of ​​the suspicious wafer notch is greater than a preset minimum area for target wafer notches; and the ratio of the length to the depth of the suspicious wafer notch is less than the ratio of the length to the depth of the target wafer notch. The first abnormal wafer notches are then removed from the suspicious wafer notches in the second target image.

[0100] Step S504: The remaining suspicious wafer gap in the third target image is identified as the first target wafer gap.

[0101] Figure 5b This is a flowchart illustrating the process of determining a target wafer notch and removing abnormal wafer notches according to an embodiment of this application, such as... Figure 5b As shown, the process includes the following steps:

[0102] Step S5051: Determine whether the first target wafer notch meets the first preset condition. The first preset condition is: the number of the first target wafer notches is 1, or when the number of the first target wafer notches is 2, the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0103] Step S5052: If the first target wafer notch meets the first preset condition, the first target wafer notch is determined to be the target wafer notch.

[0104] Step S5053: If the first target wafer gap does not meet the first preset condition, remove the second abnormal wafer gap from the suspicious wafer gaps in the third target image.

[0105] According to another optional embodiment of this application, if the number of first target wafer notches is 1, it is determined that all suspicious notches on the wafer have been removed, and the first target wafer notch is the actual notch on the wafer (target wafer notch). If the number of first target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds a preset target longitudinal distance (recommended value 14000 pixels), meaning that the wafer rotates more than 360 degrees during the image acquisition process by the line scan camera, the two wafer notches in the image are actually the same wafer notch acquired twice by the line scan camera. Therefore, if the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds the preset target longitudinal distance (recommended value 14000 pixels), it is also determined that all suspicious notches on the wafer have been removed. The wafer notch closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the first target wafer notch is the actual wafer notch, and the coordinates of the actual notch are determined.

[0106] It is understandable that the line scan camera captures images of the wafer while it is rotating. That is, the line scan camera takes pictures of the wafer while it is rotating. If the wafer rotates more than 360 degrees, the line scan camera may capture the notch twice. That is, two wafer notches that are more than the preset target vertical distance (the recommended value is 14,000 pixels) will be the same wafer notch captured twice by the line scan camera.

[0107] Figure 6a This is a flowchart illustrating a method for removing a second abnormal wafer gap from a suspicious wafer gap in a third target image, according to an embodiment of this application. Figure 6a As shown, the process includes the following steps:

[0108] Step S602: The third target image is segmented into a first sub-image and a second sub-image, wherein the height of the first sub-image is the same as the height of the second sub-image, and the width of the first sub-image is the same as the width of the second sub-image.

[0109] As an optional embodiment of this application, the third target image is divided into two images with the same height and width, namely a first sub-image and a second sub-image. For example, the first sub-image is the left half of the suspected wafer notch, such as... Figure 11a As shown, the second sub-image is the right half of the suspected wafer notch, as... Figure 11b As shown.

[0110] Step S604: Perform a mirror flip operation on either the first sub-image or the second sub-image to obtain the first target sub-image.

[0111] The right half of the suspected wafer notch image is mirrored to obtain the mirrored right half of the suspected wafer notch image, i.e., the first target sub-image, as shown below. Figure 11c As shown.

[0112] Step S606: Perform an XOR operation on the first target sub-image and the second target sub-image to obtain the image after the XOR operation, wherein the second target sub-image is the sub-image that has not undergone the mirror flip operation.

[0113] Perform an XOR operation on the right half of the image of the suspected wafer notch (i.e., the first target sub-image) and the left half of the image of the suspected wafer notch, obtained by mirroring and flipping the image, to obtain the image after the XOR operation. The image after the XOR operation is shown below. Figure 11d As shown, in Figure 11d In the diagram, the XOR region is the non-overlapping area between the left and right images, i.e., the white area.

[0114] Step S608: Determine the pixel area of ​​the XOR region in the image after the XOR operation.

[0115] Step S610: Remove the second abnormal wafer gap in the suspicious wafer gap in the third target image based on the pixel area of ​​the XOR region to obtain the fourth target image.

[0116] Figure 6b This is a flowchart illustrating the determination of a fourth target image according to an embodiment of this application, such as... Figure 6b As shown, the process includes the following steps:

[0117] Step S6101: Determine the pixel area of ​​the suspicious wafer notch in the third target image.

[0118] Step S6102: Determine the symmetry of the suspicious wafer gap in the third target image based on the pixel area of ​​the XOR region and the pixel area of ​​the suspicious wafer gap in the third target image.

[0119] The symmetry of the suspicious wafer notch in the third target image is determined using the following formula:

[0120] Symmetry = (Pixel area of ​​suspected wafer notch - Pixel area of ​​XOR region × 2) / Pixel area of ​​suspected wafer notch.

[0121] Step S6103: The suspected wafer gap in the third target image whose symmetry is less than the preset target symmetry is identified as the second abnormal wafer gap.

[0122] Step S6104: Remove the second abnormal wafer gap from the suspicious wafer gap in the third target image to obtain the fourth target image.

[0123] Step S612: The remaining suspicious wafer gap in the fourth target image is identified as the second target wafer gap.

[0124] Figure 6c This is another flowchart of determining the target wafer notch and removing abnormal wafer notches according to an embodiment of this application, such as... Figure 6c As shown, the process includes the following steps:

[0125] Step S6131: Determine whether the second target wafer notch meets the second preset condition. The second preset condition is: the number of second target wafer notches is 1, or when the number of second target wafer notches is 2, the longitudinal distance between the two wafer notches included in the second target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0126] Step S6132: If the second target wafer notch meets the second preset condition, determine the second target wafer notch as the target wafer notch.

[0127] Step S6133: If the second target wafer gap does not meet the second preset condition, remove the third abnormal wafer gap from the suspicious wafer gaps in the fourth target image.

[0128] According to another optional embodiment of this application, if the number of second target wafer notches is 1, it is determined that all suspicious notches on the wafer have been removed, and the second target wafer notch is the actual notch of the wafer (target wafer notch). If the number of second target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the second target wafer notch exceeds a preset target longitudinal distance (suggested value is 14000 pixels), it is also determined that all suspicious notches on the wafer have been removed, and the wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the second target wafer notch is determined as the actual notch of the wafer (target wafer notch).

[0129] Figure 7a This is a flowchart illustrating a method for removing a third abnormal wafer notch from a suspicious wafer notch in a fourth target image, according to an embodiment of this application. Figure 7a As shown, the process includes the following steps:

[0130] Step S702: Determine the parabolic function corresponding to the profile of the suspicious wafer notch in the fourth target image.

[0131] Figure 7b This is a flowchart illustrating a method for determining the parabolic function corresponding to the profile of a suspicious wafer notch in a fourth target image, according to an embodiment of this application. Figure 7b As shown, the process includes the following steps:

[0132] Step S7021: Determine the suspicious wafer notch contour image corresponding to the suspicious wafer notch contour.

[0133] Figure 12a This is a schematic diagram of a corrected suspicious notch contour image according to an embodiment of this application. The aforementioned suspicious wafer notch contour image is as follows: Figure 12a As shown.

[0134] Step S7022: Remove the bottom straight line of the suspicious wafer notch outline from the suspicious wafer notch outline image to obtain the target suspicious wafer notch outline image.

[0135] Because the wafer notch outline is circular, the bottom straight line of the suspected wafer notch outline is removed from the suspected wafer notch outline image to obtain the target suspected wafer notch outline image, where the target suspected wafer notch outline image is as follows. Figure 12b As shown.

[0136] Step S7023: Determine the contour calculation points of the suspicious wafer notch contour in the target suspicious wafer notch contour image.

[0137] Step S7024: Obtain the first abscissa and first ordinate of the contour calculation point of the suspected wafer notch contour, and transform the first ordinate of the contour calculation point according to the height of the target suspected wafer notch contour image to obtain the target ordinate of the contour calculation point.

[0138] The first ordinate of the contour calculation point is transformed using the following formula:

[0139] y′=Hy

[0140] Where H is the height of the target suspicious wafer notch contour image, y is the first ordinate of the contour calculation point, and y' is the target ordinate of the contour calculation point.

[0141] Step S7025: Based on the first abscissa and the target ordinate, a parabolic function is fitted to obtain the parabola function.

[0142] Based on the first x-coordinate and the target y-coordinate, a parabolic function is obtained by fitting using the least squares method. Specifically, the optimization function is first determined:

[0143]

[0144] Where, x k and y k Let A, B, and C be the first x-coordinate and first y-coordinate of the contour calculation point, respectively. Set the partial derivative to 0, and solve to obtain A, B, and C.

[0145] The parabolic function is obtained by fitting the contour calculation points:

[0146] y = Ax 2 +Bx+C

[0147] Step S704: Based on the parabolic function corresponding to the suspicious wafer notch contour, remove the third abnormal wafer notch from the suspicious wafer notch in the fourth target image to determine the third target wafer notch.

[0148] Figure 7c This is a flowchart illustrating the determination of a third target wafer notch according to an embodiment of this application, such as... Figure 7c As shown, the process includes the following steps:

[0149] Step S7041: Substitute the first abscissa into the parabola function to solve, and determine the solution as the second ordinate.

[0150] Substitute the x-value (first abscissa) of the contour calculation point into the parabola function above to solve for the y-value (second ordinate) on the parabola.

[0151] Step S7042: Determine the similarity deviation value between the first ordinate and the second ordinate, wherein the similarity deviation value is the average of the absolute values ​​of the differences between the first ordinate and the second ordinate.

[0152] Step S7043: The suspicious wafer gap in the fourth target image whose similarity deviation value is greater than the preset target similarity deviation value is identified as the third abnormal wafer gap.

[0153] Step S7044: Remove the third abnormal wafer gap from the suspicious wafer gap in the fourth target image to obtain the third target wafer gap.

[0154] Figure 7d This is another flowchart of determining the target wafer notch and removing abnormal wafer notches according to an embodiment of this application, such as... Figure 7d As shown, the process includes the following steps:

[0155] Step S7051: Determine whether the third target wafer notch meets the third preset condition. The third preset condition is: the number of third target wafer notches is 1, or when the number of third target wafer notches is 2, the longitudinal distance between the two wafer notches included in the third target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0156] Step S7052: If the third target wafer gap meets the third preset condition, the third target wafer gap is determined to be the target wafer gap.

[0157] Step S7053: If the third target wafer notch does not meet the third preset condition, generate an alarm message.

[0158] According to another optional embodiment of this application, if the number of third target wafer notches is 1, it is determined that all suspicious notches on the wafer have been removed, and the third target wafer notch is the actual notch of the wafer (target wafer notch). If the number of third target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the third target wafer notch exceeds a preset target longitudinal distance (recommended value is 14000 pixels), it is also determined that all suspicious notches on the wafer have been removed, and the wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the third target wafer notch is determined as the actual notch of the wafer (target wafer notch).

[0159] If the third target wafer notch does not meet the above third preset condition, it is determined that the suspected wafer notch has not been completely removed. At this time, an alarm message is generated to remind the client to adjust parameters such as the brightness of the light source, and then remove the suspected wafer notch again.

[0160] Figure 8aThis is a flowchart of another wafer notch screening method according to an embodiment of this application. Figure 8b This is a flowchart of another wafer notch screening method according to an embodiment of this application. Figure 8c This is a flowchart of another wafer notch screening method according to an embodiment of this application, such as... Figure 8a , Figure 8b and Figure 8c As shown, the method includes the following steps:

[0161] Step S802: Scan the wafer using a linear scan camera to acquire the edge image of the pre-aligned wafer. The edge image of the pre-aligned wafer is shown below. Figure 9a As shown.

[0162] Step S804: The suspected wafer gap is initially located by traversing the rows of pixels in the edge image of the pre-aligned wafer, and the location of the suspected wafer gap is initially determined.

[0163] Step S806: Extract a local area of ​​the initially located suspected wafer notch location to determine the first image; perform binarization processing on the first image to obtain a binary image containing only black and white components, i.e., the second image, wherein the second image is as follows: Figure 9b As shown, in Figure 9b In the diagram, the white component represents the wafer portion, and the black component represents the non-wafer portion.

[0164] Step S808: Extract the convex hull of the suspected wafer notch, that is, extract the convex portion and the concave portion of the edge contour of the suspected wafer notch in the second image. The extracted image is as follows. Figure 9c As shown.

[0165] Step S810: Fill in the recessed portion of the edge contour of the suspected wafer notch in the second image to obtain a third image, wherein the third image is as follows: Figure 9d As shown.

[0166] Step S812: Subtract the second image from the third image, that is, remove the overlapping part of the third and second images in the third image, to obtain the fourth image, wherein the fourth image is as follows: Figure 9e As shown.

[0167] Step S814: Perform a horizontal deburring operation on the fourth image to remove fine line interference, and finally determine the first target image, wherein the first target image is as follows: Figure 9f As shown.

[0168] Step S816: Determine the minimum rotation bounding moment of the suspicious wafer notch in the first target image, that is, determine the target bounding box of the first target image, wherein the target bounding box is a rotatable rectangle, so as to enclose the suspicious wafer notch with the minimum area.

[0169] Step S818: Determine the corner position of the suspicious wafer notch in the first target image based on the minimum rotation bounding moment (target bounding box), that is, determine the corner coordinates of the suspicious wafer notch.

[0170] Step S820: Determine the height and width of the suspicious wafer notch in the first target image based on the corner coordinates in step S818.

[0171] Step S822: Create a notch correction map, wherein the width of the notch correction map is the height of the suspected wafer notch, and the height of the notch correction map is the width of the suspected wafer notch.

[0172] Step S824: Transform the four corner points of the suspected wafer notch in the first target image into a notch correction image to obtain the fifth image, wherein the fifth image is as follows: Figure 10a As shown.

[0173] Step S826: After repairing and filling the edge of the suspected wafer notch using convex hull, that is, filling the recessed part of the edge contour of the suspected wafer notch in the fifth image, a second target image is obtained, wherein the second target image is as follows: Figure 10b As shown.

[0174] Step S828: Add the corrected and repaired image of the suspicious wafer notch (the second target image) to the suspicious notch image container set.

[0175] Step S830: Count the non-zero pixel values ​​on the corrected and repaired image of the suspected wafer notch (second target image) and calculate the area of ​​the suspected wafer notch.

[0176] Step S832: Determine the depth and length of the suspected wafer notch based on the width and height of the corrected suspected wafer notch image (second target image), wherein the depth of the suspected wafer notch is the image height and the length of the suspected wafer notch is the image width.

[0177] Step S834: Determine whether the depth and length of the suspected wafer notch meet the preset screening conditions. The screening conditions are as follows:

[0178] 1. The depth of the suspected wafer notch is less than the preset target wafer notch maximum depth value, where the suggested value for the preset target wafer notch maximum depth value is 50 pixels;

[0179] 2. The depth of the suspected wafer notch is greater than the preset minimum depth of the target wafer notch, where the suggested value for the preset maximum depth of the target wafer notch is 20 pixels;

[0180] 3. The length of the suspected wafer notch is less than the preset maximum length of the target wafer notch, where the suggested value for the preset maximum depth of the target wafer notch is 90 pixels;

[0181] 4. The length of the suspected wafer notch is greater than the preset minimum length of the target wafer notch, where the suggested maximum depth of the preset target wafer notch is 45 pixels;

[0182] 5. The area of ​​the suspected wafer notch is larger than the minimum area of ​​the preset target wafer notch, where the suggested value for the maximum depth of the preset target wafer notch is 500 pixels;

[0183] 6. The ratio of the length of the suspected wafer notch to the depth of the suspected wafer notch is less than the ratio of the length of the target wafer notch to the depth of the wafer notch. The suggested value for the ratio of the length of the target wafer notch to the depth of the wafer notch is 3.

[0184] Step S836: If all six conditions in step S834 are met simultaneously, the suspected wafer gap is added to the size screening container; if none of the above six conditions are met simultaneously, the suspected wafer gap is the first abnormal wafer gap, and the first abnormal wafer gap is removed from the suspected wafer gaps in the second target image.

[0185] Step S838: Determine whether the first target wafer notch meets the first preset condition, wherein the first preset condition is: the number of the first target wafer notches is 1, or when the number of the first target wafer notches is 2, the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0186] If the first target wafer notch meets the first preset condition, the first target wafer notch is determined to be the target wafer notch. The first abnormal wafer notch is removed from the suspicious wafer notches in the second target image to obtain the third target image.

[0187] According to an optional embodiment of this application, if the first target wafer notch meets the first preset condition, step S876 is executed, wherein...

[0188] If the number of first target wafer gaps in the first preset condition is 1, the first target wafer gap is determined to be the target wafer gap, that is, the actual gap of the wafer, and the wafer gap screening process ends.

[0189] If the number of first target wafer gaps in the first preset condition is 2, and the longitudinal distance between the two wafer gaps included in the first target wafer gap exceeds the preset target longitudinal distance (suggested value is 14000 pixels), execute step S876, determine the wafer gap that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer gaps included in the first target wafer gap as the target wafer gap, that is, the real gap of the wafer, and end the wafer gap screening process.

[0190] Step S840: If the first target wafer notch does not meet the first preset condition, the third target image is divided into two images with the same height and width, namely, a first sub-image and a second sub-image. For example, the first sub-image is the left half of the suspected wafer notch. Figure 11a As shown, the second sub-image is the right half of the suspected wafer notch, as... Figure 11b As shown.

[0191] Step S842: Perform a mirror flip operation on the right half of the suspected wafer notch image to obtain the mirror flipped right half of the suspected wafer notch image, i.e., the first target sub-image, wherein the first target sub-image is as follows: Figure 11c As shown.

[0192] Step S844: Perform an XOR operation on the right half of the mirrored image of the suspected wafer notch (i.e., the first target sub-image) and the left half of the suspected wafer notch image to obtain the XORed image, where the XORed image is as follows. Figure 11d As shown, in Figure 11d In the diagram, the XOR region is the non-overlapping area between the left and right images, i.e., the white area.

[0193] Step S846: Determine the pixel area of ​​the XOR region in the image after the XOR operation.

[0194] Step S848: Determine the overall pixel area of ​​the suspicious wafer notch in the third target image.

[0195] Step S850: Determine the symmetry of the suspected wafer notch in the third target image according to the following formula:

[0196] Wherein, symmetry = (pixel area of ​​suspected wafer notch - pixel area of ​​XOR region × 2) / pixel area of ​​suspected wafer notch.

[0197] Step S852: Determine whether the symmetry of the suspected wafer notch in the third target image is less than the minimum symmetry of the wafer notch (preset target symmetry), wherein the suggested value for the minimum symmetry of the wafer notch is 0.75.

[0198] Step S854: If the symmetry of the suspected wafer notch in the third target image is less than the minimum symmetry of the wafer notch, the suspected wafer notch is determined to be the second abnormal wafer notch. The second abnormal wafer notch is removed from the suspected wafer notches in the third target image to obtain the fourth target image. The remaining suspected wafer notches in the fourth target image are determined to be the second target wafer notches. If the symmetry of the suspected wafer notch in the third target image is greater than the minimum symmetry of the wafer notch, the suspected wafer notch is added to the symmetry screening container.

[0199] Step S856: Determine whether the second target wafer notch meets the second preset condition. The second preset condition is: the number of second target wafer notches is 1, or when the number of second target wafer notches is 2, the longitudinal distance between the two wafer notches included in the second target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0200] If the second target wafer notch meets the second preset condition, proceed to step S876, wherein...

[0201] If the number of second target wafer gaps in the second preset condition is 1, the second target wafer gap is determined to be the target wafer gap, that is, the actual gap of the wafer, and the wafer gap screening process ends.

[0202] If the number of second target wafer gaps in the second preset condition is 2, and the longitudinal distance between the two wafer gaps included in the second target wafer gap exceeds the preset target longitudinal distance (suggested value is 14000 pixels), the wafer gap that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer gaps included in the second target wafer gap is determined as the target wafer gap, that is, the real gap of the wafer, and the wafer gap screening process ends.

[0203] Step S858: If the second target wafer notch does not meet the second preset condition, obtain the suspected wafer notch contour image corresponding to the suspected wafer notch contour. The suspected wafer notch contour image is as follows: Figure 12a As shown.

[0204] Step S860: Remove the bottom straight line of the suspicious wafer notch contour from the suspicious wafer notch contour image to obtain the target suspicious wafer notch contour image, wherein the target suspicious wafer notch contour image is as follows: Figure 12b As shown.

[0205] Step S862: Determine the contour calculation points of the suspicious wafer notch contour in the target suspicious wafer notch contour image, that is, obtain the contour calculation points of all suspicious wafer notch contours after removing the bottom straight line part.

[0206] Obtain the first x-coordinate and first y-coordinate of the contour calculation point of the suspected wafer notch outline, and transform the first y-coordinate of the contour calculation point according to the height of the target suspected wafer notch outline image to obtain the target y-coordinate of the contour calculation point. The transformation formula is as follows:

[0207] y′=Hy

[0208] Where H is the height of the target suspicious wafer notch contour image, y is the first ordinate of the contour calculation point, and y' is the target ordinate of the contour calculation point.

[0209] Step S864: Based on the first abscissa and the target ordinate, a parabolic function is fitted to obtain the parabola function.

[0210] Based on the first x-coordinate and the target y-coordinate, a parabolic function is obtained by fitting using the least squares method. Specifically, the optimization function is first determined:

[0211]

[0212] Where, x k and y k Let A, B, and C be the first x-coordinate and first y-coordinate of the contour calculation point, respectively. Set the partial derivative to 0, and solve to obtain A, B, and C.

[0213] The parabolic function is obtained by fitting the contour calculation points:

[0214] y = Ax 2 +Bx+C

[0215] Step S866: Substitute the x-value (first abscissa) of the contour calculation point into the parabola function above to solve for the y-value (second ordinate) on the parabola.

[0216] Step S868: Determine the similarity deviation value between the first ordinate and the second ordinate, wherein the similarity deviation value is the average of the absolute values ​​of the differences between the first ordinate and the second ordinate.

[0217] Step S870: Determine whether the similarity deviation value is greater than the preset target similarity deviation value. The preset target similarity deviation value is used to characterize the degree of similarity with the arc shape of the wafer notch. The smaller the shape similarity deviation, the more realistic and the more similar the notch. The suggested value for the preset target similarity deviation value is 2.7.

[0218] Step S872: If the similarity deviation value is greater than the preset target similarity deviation value, the suspicious wafer notch is determined to be the third abnormal wafer notch. The third abnormal wafer notch is removed from the suspicious wafer notches in the fourth target image to obtain the third target wafer notch. The remaining suspicious wafer notches in the fourth target image are then determined to be the third target wafer notches. If the similarity deviation value is less than the preset target similarity deviation value, the suspicious wafer notch is added to the symmetry screening container.

[0219] Step S874: Determine whether the third target wafer notch meets the third preset condition. The third preset condition is: the number of third target wafer notches is 1, or when the number of third target wafer notches is 2, the longitudinal distance between the two wafer notches included in the third target wafer notch exceeds the preset target longitudinal distance (suggested value is 14000 pixels).

[0220] Step S876: If the third target wafer gap meets the third preset condition, the third target wafer gap is determined to be the target wafer gap, that is, the real wafer gap.

[0221] If the number of third target wafer gaps in the third preset condition is 1, the third target wafer gap is determined to be the target wafer gap, that is, the actual gap of the wafer, and the wafer gap screening process ends.

[0222] If the number of third target wafer gaps in the third preset condition is 2, and the longitudinal distance between the two wafer gaps included in the third target wafer gap exceeds the preset target longitudinal distance (suggested value is 14000 pixels), the wafer gap that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer gaps included in the third target wafer gap is determined as the target wafer gap, that is, the real gap of the wafer, and the wafer gap screening process ends.

[0223] Step S878: If the third target wafer notch does not meet the third preset condition, an alarm message is generated, indicating that the wafer notch cannot be found, and parameters such as the brightness of the light source are adjusted.

[0224] Step S880: Adjust the parameters and execute step S802 to obtain the edge image of the pre-aligned wafer after parameter adjustment.

[0225] Based on the above steps, wafer notches are progressively screened based on size, symmetry, and morphological similarity to obtain the true wafer notches.

[0226] The wafer notch size filtering method includes: extracting the depth, length, aspect ratio (ratio of length to depth), and area of ​​suspicious notches, and filtering out suspicious notches whose depth, length, aspect ratio, and area do not meet the set requirements. This method can effectively filter out light spot interference that does not conform to size specifications.

[0227] The wafer notch symmetry filtering method includes: constructing a symmetry calculation method, symmetry = (total pixel area of ​​the suspected notch - pixel area of ​​the XOR region × 2) / total pixel area of ​​the suspected notch, and filtering out suspected notches that do not meet the symmetry requirements. This method can effectively filter out similar spot interference that meets the size requirements but is asymmetrical.

[0228] The filtering method for wafer notch morphology similarity includes: describing the morphological features using a parabolic function, extracting the contour points of suspicious notches, fitting the parabolic function with multiple contour calculation points, calculating the average absolute deviation of the distance from the contour points to the parabolic function, and filtering out suspicious notches with large average absolute deviations. This method can effectively filter out interference from similar light spots that are rectangular, multi-dimensional, or otherwise symmetrical.

[0229] In summary, the wafer notch screening method provided in this application achieves the technical effect of effectively filtering edge light spot interference and improving the wafer notch positioning accuracy when using a line scan camera.

[0230] Figure 13 This is a structural diagram of a wafer notch screening device according to an embodiment of this application, as shown below. Figure 13 As shown, the device includes:

[0231] 1302 First processing module is used to acquire the edge image of the pre-aligned wafer and process the edge image of the pre-aligned wafer to obtain a first target image including the suspected wafer notch;

[0232] 1304 The second processing module is used to determine the notch correction image based on the size of the suspected wafer notch in the first target image, and convert the suspected wafer notch in the first target image into the notch correction image to obtain the second target image;

[0233] The 1306 determination module is used to remove the abnormal wafer gap from the suspicious wafer gap in the second target image to obtain the target wafer gap.

[0234] It should be noted that the above Figure 13 The modules in the above can be program modules (e.g., a set of program instructions that implement a specific function) or hardware modules. For the latter, they can be represented in the following forms, but are not limited to these: each of the above modules is represented by a processor, or the functions of each of the above modules are implemented by a processor.

[0235] Figure 14 A hardware block diagram of a computer terminal (or mobile device) for implementing a wafer notch screening method is shown. Figure 14As shown, the computer terminal 140 (or mobile device 140) may include one or more processors 1402 (shown as 1402a, 1402b, ..., 1402n in the figure) (processor 1402 may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.), a memory 1404 for storing data, and a transmission module 1406 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 14 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, the computer terminal 140 may also include... Figure 14 The more or fewer components shown, or having the same Figure 14 The different configurations shown.

[0236] It should be noted that the aforementioned one or more processors 1402 and / or other data processing circuitry are generally referred to herein as "data processing circuitry". This data processing circuitry may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuitry may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the computer terminal 140 (or mobile device). As involved in the embodiments of this application, this data processing circuitry serves as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0237] The memory 1404 can be used to store software programs and modules for application software, such as the program instructions / data storage device corresponding to the wafer notch screening method in this embodiment. The processor 1402 executes various functional applications and data processing by running the software programs and modules stored in the memory 1404, thereby implementing the aforementioned wafer notch screening method. The memory 1404 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1404 may further include memory remotely located relative to the processor 1402, and these remote memories can be connected to the computer terminal 140 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0238] The transmission module 1406 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the computer terminal 140. In one example, the transmission module 1406 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission module 1406 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0239] The display may be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of the computer terminal 140 (or mobile device).

[0240] It should be noted here that, in some optional embodiments, the above... Figure 14 The computer device (or electronic device) shown may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium), or a combination of both hardware and software elements. It should be noted that... Figure 14 This is only one instance of a particular specific instance, and is intended to illustrate the types of components that may exist in the aforementioned computer equipment (or electronic equipment).

[0241] It should be noted that, Figure 14 The electronic device shown is used to perform Figure 1 The wafer notch screening method shown above also applies to this electronic device, and will not be repeated here.

[0242] This application embodiment also provides a non-volatile storage medium, which includes a stored program, wherein the program, when running, controls the device where the storage medium is located to execute the above-mentioned wafer notch screening method.

[0243] A non-volatile storage medium performs the following functions: acquires an edge image of a pre-aligned wafer, processes the edge image of the pre-aligned wafer to obtain a first target image including a suspected wafer notch; determines a notch correction image based on the size of the suspected wafer notch in the first target image, and converts the suspected wafer notch in the first target image to the notch correction image to obtain a second target image; removes the abnormal wafer notch from the suspected wafer notch in the second target image to obtain the target wafer notch.

[0244] This application also provides an electronic device, including: a memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the program executes the above-described wafer notch screening method during runtime.

[0245] The processor is used to run a program that performs the following functions: acquires an edge image of the pre-aligned wafer, processes the edge image of the pre-aligned wafer to obtain a first target image including a suspected wafer notch; determines a notch correction image based on the size of the suspected wafer notch in the first target image, and converts the suspected wafer notch in the first target image to the notch correction image to obtain a second target image; removes the abnormal wafer notch in the suspected wafer notch in the second target image to obtain the target wafer notch.

[0246] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0247] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0248] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0249] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0250] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0251] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to related technologies, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0252] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for screening wafer notches, characterized in that, include: Obtain an edge image of the pre-aligned wafer and process the edge image of the pre-aligned wafer to obtain a first target image including a suspected wafer notch; Based on the size of the suspected wafer notch in the first target image, a notch correction image is determined, and the suspected wafer notch in the first target image is converted to the notch correction image to obtain a second target image; Remove the abnormal wafer gap from the suspected wafer gap in the second target image to obtain the target wafer gap; The removal of abnormal wafer gaps from the suspected wafer gaps in the second target image includes: identifying suspected wafer gaps in the second target image that do not meet preset screening conditions as the first abnormal wafer gap among the suspected wafer gaps. The preset screening conditions include: the depth of the suspected wafer gap is less than a preset maximum depth value for target wafer gaps; the depth of the suspected wafer gap is greater than a preset minimum depth value for target wafer gaps; the length of the suspected wafer gap is less than a preset maximum length value for target wafer gaps; and the length of the suspected wafer gap is greater than a preset minimum length value for target wafer gaps. The area of ​​the suspected wafer notch is greater than the minimum area of ​​the preset target wafer notch, and the ratio of the length to the depth of the suspected wafer notch is less than the ratio of the length to the depth of the preset target wafer notch. The first abnormal wafer notch is deleted from the suspected wafer notch in the second target image to obtain a third target image, wherein the depth of the suspected wafer notch is the height of the second target image, and the length of the suspected wafer notch is the width of the second target image. The remaining suspected wafer notches in the third target image are determined as the first target wafer notch.

2. The method according to claim 1, characterized in that, After identifying the remaining suspicious wafer gap in the third target image as the first target wafer gap, the method further includes: Determine whether the first target wafer notch meets the first preset condition, wherein the first preset condition is: the number of the first target wafer notches is 1, or when the number of the first target wafer notches is 2, the longitudinal distance between the two wafer notches included in the first target wafer notch exceeds the preset target longitudinal distance; If the first target wafer notch meets the first preset condition, the first target wafer notch is determined to be the target wafer notch; If the first target wafer notch does not meet the first preset condition, remove the second abnormal wafer notch from the suspicious wafer notches in the third target image.

3. The method according to claim 2, characterized in that, Determining the first target wafer notch as the target wafer notch includes: If the first preset condition is that the number of first target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the first target wafer notches exceeds the preset target longitudinal distance, the wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the first target wafer notches is determined as the target wafer notch.

4. The method according to claim 2, characterized in that, Removing the second abnormal wafer notch from the suspicious wafer notch in the third target image includes: The third target image is divided into a first sub-image and a second sub-image, wherein the height of the first sub-image is the same as the height of the second sub-image, and the width of the first sub-image is the same as the width of the second sub-image. Perform a mirror flip operation on either the first sub-image or the second sub-image to obtain the first target sub-image; Perform an XOR operation on the first target sub-image and the second target sub-image to obtain the image after the XOR operation, wherein the second target sub-image is the sub-image that has not undergone the mirror flip operation; Determine the pixel area of ​​the XOR region in the image after the XOR operation; The second abnormal wafer gap in the suspected wafer gap in the third target image is removed based on the pixel area of ​​the XOR region to obtain the fourth target image; The remaining suspicious wafer gap in the fourth target image is identified as the second target wafer gap.

5. The method according to claim 4, characterized in that, Based on the pixel area of ​​the XOR region, the second abnormal wafer notch in the suspected wafer notch of the third target image is removed to obtain the fourth target image, including: Determine the pixel area of ​​the suspected wafer notch in the third target image; The symmetry of the suspected wafer gap in the third target image is determined based on the pixel area of ​​the XOR region and the pixel area of ​​the suspected wafer gap in the third target image; Suspicious wafer gaps in the third target image whose symmetry is less than or equal to a preset target symmetry are identified as the second abnormal wafer gaps; The second abnormal wafer gap in the suspicious wafer gap in the third target image is removed to obtain the fourth target image.

6. The method according to claim 4, characterized in that, After identifying the remaining suspicious wafer gap in the fourth target image as the second target wafer gap, the method further includes: Determine whether the second target wafer notch meets the second preset condition, wherein the second preset condition is: the number of the second target wafer notches is 1, or when the number of the second target wafer notches is 2, the longitudinal distance between the two wafer notches included in the second target wafer notch exceeds the preset target longitudinal distance; If the second target wafer notch meets the second preset condition, the second target wafer notch is determined to be the target wafer notch; If the second target wafer gap does not meet the second preset condition, remove the third abnormal wafer gap from the suspicious wafer gaps in the fourth target image.

7. The method according to claim 6, characterized in that, If the second preset condition is that the number of second target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the second target wafer notches exceeds the preset target longitudinal distance, then the second target wafer notch is determined to be the target wafer notch, including: The wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the second target wafer notch is determined as the target wafer notch.

8. The method according to claim 6, characterized in that, Removing the third anomalous wafer notch from the suspicious wafer notch in the fourth target image includes: Determine the parabolic function corresponding to the profile of the suspected wafer notch in the fourth target image; Based on the parabolic function corresponding to the suspicious wafer notch contour, the third abnormal wafer notch of the suspicious wafer notch in the fourth target image is removed, and the third target wafer notch is determined.

9. The method according to claim 8, characterized in that, Determining the parabolic function corresponding to the profile of the suspected wafer notch in the fourth target image includes: Determine the suspicious wafer notch contour image corresponding to the suspicious wafer notch contour; Remove the bottom straight line of the suspicious wafer notch outline from the suspicious wafer notch outline image to obtain the target suspicious wafer notch outline image; Determine the contour calculation points of the suspicious wafer notch contour in the target suspicious wafer notch contour image; Obtain the first abscissa and first ordinate of the contour calculation point of the suspected wafer notch contour, and transform the first ordinate of the contour calculation point according to the height of the target suspected wafer notch contour image to obtain the target ordinate of the contour calculation point; The parabolic function is obtained by fitting the first horizontal coordinate and the target vertical coordinate.

10. The method according to claim 9, characterized in that, Based on the parabolic function corresponding to the suspicious wafer notch contour, the third abnormal wafer notch of the suspicious wafer notch in the fourth target image is removed to determine the third target wafer notch, including: Substitute the first abscissa into the parabolic function to solve for the solution, and determine the second ordinate as the solution. Determine the similarity deviation value between the first ordinate and the second ordinate, wherein the similarity deviation value is the average of the differences between the first ordinate and the second ordinate; The suspicious wafer gap in the fourth target image whose similarity deviation value is greater than the preset target similarity deviation value is identified as the third abnormal wafer gap; Remove the third abnormal wafer gap from the suspicious wafer gap in the fourth target image to obtain the third target wafer gap.

11. The method according to claim 8, characterized in that, After determining the third target wafer notch, the method further includes: Determine whether the third target wafer notch meets a third preset condition, wherein the third preset condition is: the number of the third target wafer notches is 1, or when the number of the third target wafer notches is 2, the longitudinal distance between the two wafer notches included in the third target wafer notch exceeds the preset target longitudinal distance; If the third target wafer notch meets the third preset condition, the third target wafer notch is determined to be the target wafer notch; If the third target wafer notch does not meet the third preset condition, an alarm message is generated.

12. The method according to claim 11, characterized in that, If the third preset condition is that the number of third target wafer notches is 2, and the longitudinal distance between the two wafer notches included in the third target wafer notches exceeds the preset target longitudinal distance, then the third target wafer notch is determined to be the target wafer notch, including: The wafer notch that is closer to the center point of the edge image of the pre-aligned wafer among the two wafer notches included in the second target wafer notch is determined as the target wafer notch.

13. The method according to claim 1, characterized in that, The edge image of the pre-aligned wafer is processed to obtain a first target image including a suspected wafer notch, including: The edge image of the pre-aligned wafer is traversed to determine the location of the suspected wafer notch in the edge image of the pre-aligned wafer; Based on the location of the suspected wafer notch, a first image is determined; The first image is binarized to obtain the second image; Fill in the recessed portion of the edge contour of the suspected wafer notch in the second image to obtain the third image; Based on the second image and the third image, determine the fourth image; The fourth image is de-deburred to determine the first target image.

14. The method according to claim 1, characterized in that, Before determining the notch correction pattern based on the size of the suspected wafer notch in the first target image, the method further includes: Determine the target bounding box of the suspected wafer notch in the first target image, wherein the target bounding box is the smallest rectangle that surrounds the suspected wafer notch; The corner coordinates of the suspicious wafer notch in the first target image are determined based on the target bounding box; The height and width of the suspicious wafer notch in the first target image are determined based on the corner coordinates.

15. The method according to claim 14, characterized in that, Determining the notch correction pattern based on the size of the suspected wafer notch in the first target image includes: The height of the suspicious wafer notch in the first target image is determined as the width of the notch correction image; The width of the suspected wafer notch in the first target image is determined as the height of the notch correction image; The notch correction pattern is determined based on the width and height of the notch correction pattern.

16. The method according to claim 1, characterized in that, The suspected wafer notch in the first target image is converted to the notch correction image to obtain the second target image, including: The suspicious wafer notch in the first target image is converted to the notch correction image to obtain the fifth image; The second target image is obtained by filling in the recessed portion of the edge contour of the suspected wafer notch in the fifth image.

17. The method according to claim 1, characterized in that, Converting the suspected wafer notch in the first target image to the notch correction image to obtain the second target image includes: transforming the suspected wafer notch in the first target image through perspective to the notch correction image to obtain the second target image.

18. A wafer notch screening device, characterized in that, include: The first processing module is used to acquire the edge image of the pre-aligned wafer and process the edge image of the pre-aligned wafer to obtain a first target image including the suspected wafer notch; The second processing module is used to determine a notch correction image based on the size of the suspected wafer notch in the first target image, and to convert the suspected wafer notch in the first target image to the notch correction image to obtain the second target image; The determination module is used to remove the abnormal wafer gap in the suspected wafer gap in the second target image to obtain the target wafer gap; The removal of abnormal wafer gaps from the suspected wafer gaps in the second target image includes: identifying suspected wafer gaps in the second target image that do not meet preset screening conditions as the first abnormal wafer gap among the suspected wafer gaps. The preset screening conditions include: the depth of the suspected wafer gap is less than a preset maximum depth value for target wafer gaps; the depth of the suspected wafer gap is greater than a preset minimum depth value for target wafer gaps; the length of the suspected wafer gap is less than a preset maximum length value for target wafer gaps; and the length of the suspected wafer gap is greater than a preset minimum length value for target wafer gaps. The area of ​​the suspected wafer notch is greater than the minimum area of ​​the preset target wafer notch, and the ratio of the length to the depth of the suspected wafer notch is less than the ratio of the length to the depth of the preset target wafer notch. The first abnormal wafer notch is deleted from the suspected wafer notch in the second target image to obtain a third target image, wherein the depth of the suspected wafer notch is the height of the second target image, and the length of the suspected wafer notch is the width of the second target image. The remaining suspected wafer notches in the third target image are determined as the first target wafer notch.

19. A non-volatile storage medium, characterized in that, The non-volatile storage medium includes a stored program, wherein, when the program is executed, it controls the device containing the non-volatile storage medium to perform the wafer notch screening method according to any one of claims 1 to 17.

20. An electronic device, characterized in that, include: A memory and a processor, the processor being configured to run a program stored in the memory, wherein the program, when running, performs the wafer notch screening method according to any one of claims 1 to 17.

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