Circuit and method for switching between ternary modulation and quaternary modulation

Abstract

A switching circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation of a target device. The first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a load signal, wherein the first signal is generated by performing a one-bit left shift operation on the input signal, and the second signal is generated by adding the input signal and the load signal. The second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the load signal, wherein the third signal is generated by subtracting the input signal from the load signal, and the fourth signal is generated by performing a two's complement conversion and a one-bit left shift operation on the input signal.

Description

Technical Field

[0001] This invention relates to a circuit and method for modulation switching of a target device. More specifically, this invention relates to a circuit and method for switching between ternary modulation and quaternary modulation of a target device. Background Technology

[0002] A Class D amplifier is a commonly used audio amplifier in the field of this invention. A Class D amplifier provides two pulse-width modulation (PWM) signals to a load (e.g., a speaker), thereby driving the load with these two PWM signals. These two PWM signals can form either ternary or quaternary modulation corresponding to a target load period (i.e., the desired load period for performing modulation). When a PWM signal corresponding to a "large" target load period (e.g., 50% of a target load period) is provided, ternary modulation offers higher efficiency and lower power consumption than quaternary modulation. On the other hand, when a PWM signal corresponding to a "small" target load period (e.g., 20% of a load period) is provided, quaternary modulation offers better total harmonic distortion (THD) and lower noise than ternary modulation. Therefore, the ideal use of a Class D amplifier is to alternate between these two modulations according to the target load period to achieve better overall amplifier performance.

[0003] Figure 1A is a schematic diagram of a conventional Class D amplifier driving a load. Figure 1B illustrates two pulse-width modulated (PWM) signals provided by a conventional Class D amplifier with an initial load period of 50%. Referring to both Figures 1A and 1B, the Class D amplifier 10 can drive a load SPK1 using a PWM signal 101 and a PWM signal 102. An LC circuit including an inductor L1 and a capacitor C1, and another LC circuit including an inductor L2 and a capacitor C2, are arranged between the Class D amplifier 10 and the load SPK1. In the conventional modulation method, the initial load period of the load signal is set to 50%, that is, at the start of modulation, the two PWM signals 101 and 102 of the Class D amplifier 10 each have a 50% load period. Since the PWM signals 101 and 102 have the same load period, no current flows through the two output terminals of the Class D amplifier 10, and the load SPK1 (e.g., a speaker) is not driven. However, since pulse width modulation signals 101 and 102 will remain at a high level for half a cycle, capacitors C1 and C2 will still be charged by pulse width modulation signals 101 and 102 during this period, which will lead to unnecessary power consumption.

[0004] In view of this, there is an urgent need in the technical field of this invention for a new method of providing ternary or quaternary modulation with less power consumption. Summary of the Invention

[0005] To at least address the aforementioned problems, the present invention provides a switching circuit for switching between a ternary modulation and a quaternary modulation in a target device. The switching circuit may include a first calculation circuit and a second calculation circuit. The first calculation circuit is used to provide a first output signal and may include a shifter, an adder, a first multiplexer, a second multiplexer, and a third multiplexer. The first multiplexer is electrically connected to the shifter and the adder, the second multiplexer is electrically connected to the adder and a ground signal source, and the third multiplexer is electrically connected to the first and second multiplexers. The shifter performs a one-bit left shift operation on an input signal to generate a first signal. The adder adds the input signal to a load signal to generate a second signal. The second computing circuit can be used to provide a second output signal, and the second computing circuit may include a subtractor, a two's complement shifter, a fourth multiplexer, a fifth multiplexer, and a sixth multiplexer. The fourth multiplexer may be electrically connected to the ground signal source and the subtractor, the fifth multiplexer may be electrically connected to the subtractor and the two's complement shifter, and the sixth multiplexer may be electrically connected to the fourth and fifth multiplexers. The subtractor is used to subtract the input signal from the load signal to generate a third signal. The two's complement shifter is used to perform a two's complement transformation and a left shift operation on the input signal to generate a fourth signal. When one polarity of the input signal is positive and the number represented by the input signal is greater than the number represented by the load signal, the first output signal output by the third multiplexer can be the first signal, and the second output signal output by the sixth multiplexer can be a ground signal. When the polarity of the input signal is positive and the number represented by the input signal is not greater than the number represented by the load signal, or when the polarity of the input signal is negative and the number represented by an inverted signal of the input signal is not greater than the number represented by the load signal, the first output signal can be the second signal, and the second output signal can be the third signal. When the polarity of the input signal is negative and the number represented by the inverted signal is higher than the number represented by the load signal, the first output signal can be the ground signal, and the second output signal can be the fourth signal.

[0006] To at least address the aforementioned problems, the present invention also provides a method for switching between ternary modulation and quaternary modulation in a target device. This method can be executed by an electronic computing device. The method may include the following steps: providing a first output signal from one of a first signal, a second signal, and a ground signal based on an input signal and a load signal, wherein the first signal is generated by performing a left shift operation of one bit on the input signal, and the second signal is generated by adding the input signal to the load signal; and providing a second output signal from one of a third signal, a fourth signal, and the ground signal based on the input signal and the load signal, wherein the third signal is generated by subtracting the input signal from the load signal, and the fourth signal is generated by performing a two's complement transformation and a left shift operation of one bit on the input signal. When a polarity of the input signal is positive and a number represented by the input signal is greater than a number represented by the load signal, the first output signal may be the first signal, and the second output signal may be a ground signal. When the polarity of the input signal is positive and the number represented by the input signal is not higher than the number represented by the load signal, or when the polarity of the input signal is negative and the number represented by an inverted signal of the input signal is not greater than the number represented by the load signal, the first output signal can be the second signal, and the second output signal can be the third signal. When the polarity of the input signal is negative and the number represented by the inverted signal is greater than the number represented by the load signal, the first output signal can be the ground signal, and the second output signal can be the fourth signal.

[0007] The modulation circuit and method provided by this invention allow the load signal to have a variable load period, which further allows the initial load period of modulation to be reduced from 50% while still providing a correct ternary or quaternary modulation to the target device. Therefore, the charging time of the aforementioned LC circuit can be shortened, thereby reducing power consumption. In view of this, the modulation circuit and method provided by this invention truly solve the aforementioned problems in the technical field to which this invention pertains.

[0008] This summary paragraph describes the core concepts of the present invention, covering the problems to be solved, the means of solving the problems, and the effects of the invention, to provide a basic understanding of the invention for those skilled in the art. However, it should be understood that this summary paragraph is not intended to include all embodiments of the invention, but is only provided to present the core concepts of the invention in a simplified form and as an introduction to the following detailed description. To further enable those skilled in the art to understand the technical features of the invention, detailed techniques and preferred embodiments implemented with respect to the invention are described in the following paragraphs and figures. Attached Figure Description

[0009] The drawings can help describe the present invention, wherein:

[0010] Figure 1A A schematic diagram of a conventional Class D amplifier driving a load.

[0011] Figure 1B The diagram illustrates two pulse-width modulated signals provided by a conventional Class D amplifier with an initial load period of 50%.

[0012] Figure 2 This is a schematic diagram of a switching circuit according to one or more embodiments of the present invention.

[0013] Figure 3A This is a schematic diagram of quaternary modulation according to one or more embodiments of the present invention.

[0014] Figure 3B This is a schematic diagram of ternary modulation according to one or more embodiments of the present invention.

[0015] Figure 4 This is a schematic diagram of a switching circuit including a power-saving mode control circuit according to one or more embodiments of the present invention.

[0016] Figure 5 A method for switching between ternary modulation and quaternary modulation according to one or more embodiments of the present invention is illustrated.

[0017] 1: Switching circuit

[0018] 4: Modulation method / method

[0019] 10: Class D amplifier

[0020] 11: First Calculation Circuit

[0021] 12: Second Calculation Circuit

[0022] 101, 102: Pulse width modulation signals

[0023] 111: Shifter

[0024] 112: Adder

[0025] 113: First Multiplexer

[0026] 114: Second Multiplexer

[0027] 115: Third Multiplexer

[0028] 121: Subtractor

[0029] 122, 313: Two-complement shifters

[0030] 123: Fourth Multiplexer

[0031] 124: Fifth Multiplexer

[0032] 125: Sixth Multiplexer

[0033] 201, 202: Target pulse width modulation signal

[0034] 31: Ternary modulation setting circuit

[0035] 32: Three-element modulation switching circuit

[0036] 311: Shifter

[0037] 312, 314, 321, 322: Multiplexers

[0038] 401, 402: Steps

[0039] CP1, CP2: Comparison signals

[0040] D1: Load signal

[0041] GND: Ground signal

[0042] IN1: Input signal

[0043] O1: First output signal / Output signal

[0044] O2: Second output signal / Output signal

[0045] P1: Polarity signal

[0046] P2: Power saving mode control signal

[0047] C1, C2: Capacitors

[0048] L1, L2: Inductors

[0049] OP1: First power-saving output signal

[0050] OP2: Second power-saving output signal

[0051] S1: First signal

[0052] S2: Second signal

[0053] S3: Third Signal

[0054] S4: Fourth Signal

[0055] S5: Fifth Signal

[0056] S6: Sixth Signal

[0057] SPK1: Load

[0058] TS1, TS2: Ternary modulation signal / Ternary modulation setting signal Detailed Implementation

[0059] In the following description, the modulation circuit and modulation method for providing ternary or quaternary modulation for a target device provided by the present invention will be illustrated with reference to embodiments thereof. However, these embodiments are not intended to limit the invention to any environment, application, or implementation described therein. Therefore, the description of these embodiments is for illustrative purposes only and is not intended to limit the invention. It should be understood that elements unrelated to the invention are not shown in the following embodiments and drawings. Furthermore, the dimensions and scales of individual elements in the drawings are provided for illustrative purposes only and do not limit the scope of the invention.

[0060] Figure 2 is a schematic diagram of a switching circuit according to one or more embodiments of the present invention. The content shown in Figure 2 is for illustrative purposes only and is not intended to limit the present invention.

[0061] Referring to Figure 2, a switching circuit 1 may substantially comprise a first computing circuit 11 and a second computing circuit 12. An input signal IN1, a load signal D1, and a ground signal GND may be input to both the first computing circuit 11 and the second computing circuit 12. The input signal IN1 may represent half of the target load cycle modulated by a set of pulse width modulation signals (hereinafter referred to as a set of "target pulse width modulation signals") used to drive a target device in the future. The load signal D1 may represent the initial load cycle of the two output signals at the start of modulation. The ground signal GND is a signal provided by a ground signal source. In some embodiments, the input signal IN1, the load signal D1, and the ground signal GND may be binary signals, using the number "0" to represent a reference voltage and the number "1" to represent a power supply voltage.

[0062] The first computing circuit 11 and the second computing circuit 12 can process the load signal D1 using the input signal IN1 to generate a first output signal O1 and a second output signal O2, respectively. The numbers represented by the two output signals O1 and O2 can represent the load period of the target pulse width modulation signal. In some embodiments, the first computing circuit 11 and the second computing circuit 12 can be electrically connected to a pulse width modulation signal generation circuit, and the two output signals O1 and O2 can be transmitted to the pulse width modulation signal generation circuit. Since both output signals O1 and O2 are binary signals capable of representing numbers, the pulse width modulation signal generation circuit can be used to generate the target pulse width modulation signal based on the first output signal O1 and the second output signal O2, such that the target pulse width modulation signal can have a load period corresponding to the output signals O1 and O2. The target pulse width modulation signal can form a ternary modulation or a quaternary modulation. The specific details of the pulse width modulation signal generation circuit (i.e., a circuit capable of generating a pulse width modulation signal with a specific load period based on the input signal representing a number) are well understood by those skilled in the art to which this invention pertains, and therefore will not be elaborated further.

[0063] After the target pulse width modulation signal is applied to both sides of the target device, when there is a load period difference between the target pulse width modulation signals, there may be a bit level difference between the two sides, and therefore the target device may be driven by this bit level difference. Therefore, the load period of the target pulse width modulation signal applied to the target device may directly affect the performance of the target device. The target device may be, for example, a speaker, a headset, or any other audio output device known to those skilled in the art to which this invention pertains.

[0064] The first computing circuit 11 may include a shifter 111, an adder 112, a first multiplexer 113, a second multiplexer 114, and a third multiplexer 115. The shifter 111 can perform a one-bit left shift operation on the input signal IN1 to generate a first signal S1. The adder 112 can add the input signal IN1 to the load signal D1 to generate a second signal S2.

[0065] A first multiplexer 113 is electrically connected to a shifter 111 and an adder 112 to receive a first signal S1 and a second signal S2. The first multiplexer 113 can select (i.e., allow) one of the first signal S1 and the second signal S2 as an output based on a comparison signal CP1. The comparison signal CP1 can present a "1" when the number represented by the input signal IN1 is greater than the number represented by the load signal D1, and a "0" when the number represented by the input signal IN1 is not greater than the number represented by the load signal D1. When the comparison signal CP1 presents a "1", the first multiplexer 113 allows the first signal S1 to be transmitted to the corresponding terminal. Conversely, when the comparison signal CP1 presents a "0", the first multiplexer 113 allows the second signal S2 to be transmitted to the corresponding terminal.

[0066] It should be noted that since the input signal IN1, the load signal D1, and the ground signal GND can be binary signals representing numbers, for ease of description, the sentence in the following text in the form of "a number represented by one signal is greater than / less than a number represented by another signal" can be abbreviated to the form of "one signal is greater than / less than another signal".

[0067] The second multiplexer 114 is electrically connected to the adder 112 and a ground signal source to receive the second signal S2 and the ground signal GND. The second multiplexer 114 can select either the second signal S2 or the ground signal GND as an output based on a comparison signal CP2. When the inverse of the input signal IN1 is greater than the load signal D1, the comparison signal CP2 can be "1", and when the inverse of the input signal IN1 is not greater than the load signal D1, the comparison signal CP2 can be "0". When the comparison signal CP2 is "1", the second multiplexer 114 allows the ground signal GND to be transmitted to the corresponding terminal. Conversely, when the comparison signal CP2 is "0", the second multiplexer 114 allows the second signal S2 to be transmitted to the corresponding terminal. In some embodiments, the switching circuit 1 may further include a digital comparator and an inverter to generate comparison signals CP1 and CP2.

[0068] The third multiplexer 115 is electrically connected to the first multiplexer 113 and the second multiplexer 114, and can select one of the outputs of the first multiplexer 113 and the second multiplexer 114 as the first output signal O1 according to a polarity signal P1. The polarity signal P1 can represent a polarity (i.e., positive / negative) of the input signal IN1. In some embodiments, the polarity signal P1 is the most significant bit (MSB, i.e., the leftmost bit) of the input signal IN1, and the MSB can be "0" for positive polarity and "1" for negative polarity. When the polarity signal P1 is "1", the third multiplexer 115 can select the output of the second multiplexer 114 as the first output signal O1. Conversely, when the polarity signal P1 is "0", the third multiplexer 115 can select the output of the first multiplexer 113 as the first output signal O1.

[0069] The second calculation circuit 12 is similar to the first calculation circuit 11. Specifically, the second calculation circuit 12 may include a subtractor 121, a two's complement shifter 122, a fourth multiplexer 123, a fifth multiplexer 124, and a sixth multiplexer 125. The subtractor 121 can be used to subtract the input signal IN1 from the load signal D1 to generate a third signal S3. The two's complement shifter 122 can be used to perform a two's complement transformation and a left shift operation of one bit on the input signal IN1 to generate a fourth signal S4.

[0070] The fourth multiplexer 123 can be electrically connected to the ground signal source and the subtractor 121 to receive the ground signal GND and the third signal S3. The fourth multiplexer 123 can select either the ground signal GND or the third signal S3 as an output based on the comparison signal CP1. When the comparison signal CP1 is "1", the fourth multiplexer 123 allows the ground signal GND to be transmitted to the corresponding terminal. Conversely, when the comparison signal CP1 is "0", the fourth multiplexer 123 allows the third signal S3 to be transmitted to the corresponding terminal.

[0071] The fifth multiplexer 124 can be electrically connected to the subtractor 121 and the complement shifter 122 to receive the third signal S3 and the fourth signal S4. The fifth multiplexer 124 can select one of the third signal S3 and the fourth signal S4 as an output based on the comparison signal CP2. When the comparison signal CP2 is "1", the fifth multiplexer 124 allows the fourth signal S4 to be transmitted to the corresponding terminal. Conversely, when the comparison signal CP2 is "0", the fifth multiplexer 124 allows the third signal S3 to be transmitted to the corresponding terminal.

[0072] The sixth multiplexer 125 can be electrically connected to the fourth multiplexer 123 and the fifth multiplexer 124, and the sixth multiplexer 125 can select one of the outputs of the fourth multiplexer 123 and the fifth multiplexer 124 as the second output signal O2 according to the polarity signal P1. More specifically, when the polarity signal P1 is "1", the sixth multiplexer 125 can select the output of the fifth multiplexer 124 as the second output signal O2. Conversely, when the polarity signal P1 is "0", the sixth multiplexer 125 can select the output of the fourth multiplexer 123 as the second output signal O2.

[0073] As described above, the switching circuit 1 can generate a first output signal O1 and a second output signal O2 based on the input signal IN1, the load signal D1, the ground signal GND, and the polarity signal P1. Therefore, the target pulse width modulation signal can be obtained by generating the corresponding pulse width modulation signal based on the first output signal O1 and the second output signal O2.

[0074] The different results of modulation type (i.e., ternary or quaternary) with the first output signal O1 and the second output signal O2, as well as the corresponding relationships between the types of input signal IN1, load signal D1, polarity signal P1, and the two output signals O1 and O2, can be summarized into four cases (a) to (d), as shown in Table 1 below:

[0075] Table 1

[0076]

[0077] Referring to Table 1, in cases (a) and (b), the polarity of the input signal is positive, and the polarity signal P1 may be "0". Therefore, the third multiplexer 115 can select the output of the first multiplexer 113 as the first output signal O1, and the sixth multiplexer 125 can select the output of the fourth multiplexer 123 as the second output signal O2. The outputs of the first multiplexer 113 and the fourth multiplexer 123 can be determined based on the comparison signal CP1 instead of the comparison signal CP2. When the comparison signal CP1 is "0" (i.e., the input signal IN1 is not greater than the load signal D1, which corresponds to case (a) above), the output of the first multiplexer 113 can be the second signal S2, and the output of the fourth multiplexer 123 can be the third signal S3. Therefore, the first output signal O1 and the second output signal O2 can be the second signal S2 and the third signal S3, respectively. Since both the first output signal O1 and the second output signal O2 represent a specific number rather than the ground signal GND, a quaternary modulation can be formed based on the target pulse width modulation signals generated from the first output signal O1 and the second output signal O2. On the other hand, when CP1 is "1" (i.e., the input signal IN1 is greater than the load signal D1, corresponding to the above case (b)), the output of the first multiplexer 113 can be the first signal S1, and the output of the fourth multiplexer 123 can be the ground signal GND. Therefore, the first output signal O1 and the second output signal O2 will be the first signal S1 and the ground signal GND, respectively, and a ternary modulation can be formed based on the target pulse width modulation signals generated from the first output signal O1 and the second output signal O2.

[0078] Referring again to Table 1, in cases (c) and (d), the polarity of the input signal IN1 is negative, and the polarity signal P1 is "1". Therefore, the third multiplexer 115 can select the output of the second multiplexer 114 as the first output signal O1, and the sixth multiplexer 125 can select the output of the fifth multiplexer 124 as the second output signal O2. The outputs of the second multiplexer 114 and the fifth multiplexer 124 can be determined based on the comparison signal CP2 instead of the comparison signal CP1. When the comparison signal CP2 is "0" (i.e., the inverse of the input signal IN1 is not greater than the load signal D1, corresponding to case (c) above), the output of the second multiplexer 114 can be the second signal S2, and the output of the fifth multiplexer 124 can be the third signal S3. Therefore, the first output signal O1 and the second output signal O2 will be the second signal S2 and the third signal S3, respectively. Similar to case (a), since both the first output signal O1 and the second output signal O2 are signals representing a specific number rather than the ground signal GND, a quaternary modulation can be formed based on the corresponding target pulse width modulation signals generated by the first output signal O1 and the second output signal O2. On the other hand, when CP1 is "1" (i.e., the inverse of the input signal IN1 is greater than the load signal D1, corresponding to case (d) above), the output of the second multiplexer 114 can be the ground signal GND, and the output of the fifth multiplexer 124 can be the fourth signal S4. Therefore, the first output signal O1 and the second output signal O2 will be the ground signal GND and the fourth signal S4, respectively, and a ternary modulation can be formed based on the corresponding target pulse width modulation signals generated by the first output signal O1 and the second output signal O2.

[0079] It should be noted that the slashes in Table 1 are used to indicate signals that do not need to be considered in the corresponding cases. That is, regardless of whether the signal is "0" or "1", the first output signal O1 and the second output signal O2 will produce the same result.

[0080] Figure 3A is a schematic diagram of quaternary modulation according to one or more embodiments of the present invention. Figure 3B is a schematic diagram of ternary modulation according to one or more embodiments of the present invention. The contents shown in Figures 3A and 3B are only for illustrating embodiments of the present invention and are not intended to limit the present invention.

[0081] Referring also to Figures 2 and 3A, at the start of modulation, a set of target pulse width modulation signals 201 and 202, each initially having a load period of 20%, can be applied to the target device by a pulse width modulation signal source (e.g., the aforementioned pulse width modulation signal generation circuit). Assuming the target load period corresponding to the modulation formed by the target pulse width modulation signals 201 and 202 is 20%, the input signal IN1 can be set to represent half of the target load period, thus representing a decimal number "0.1" in binary form. As previously mentioned, the load signal D1 can be set to represent the initial load period of the modulation, and therefore can be represented, for example, as a decimal number "0.2" in binary form. This combination of input signal IN1 and load signal D1 corresponds to case (a) mentioned in the description of Table 1.

[0082] Next, switching circuit 1 adds load signal D1 to input signal IN1 to obtain a first output signal O1 (equivalent to the second signal S2) representing a decimal number "0.3", and subtracts input signal IN1 from load signal D1 to obtain a second output signal O2 (equivalent to the third signal S3) representing a decimal number "0.1". Subsequently, a target pulse width modulation signal 201 with a load period of 30% and a target pulse width modulation signal 202 with a load period of 10% can be generated accordingly. When the target device is driven, the set of target pulse width modulation signals 201 and 202 can result in a 20% load period difference between the target pulse width modulation signal 201 and the target pulse width modulation signal 202, thereby forming a quaternary modulation corresponding to a target load of 20%.

[0083] Referring also to Figures 2 and 3B, as another example, at the start of modulation, the target pulse width modulation signals 201 and 202, each initially having a load period of 20%, can be similarly applied to the target device by a pulse width modulation signal source. Therefore, the load signal D1 can be set to represent a decimal number "0.2" in binary form. Assume the input signal IN1 is set to represent a decimal number "0.21" in binary form (i.e., the target load period is 42%). This combination of input signal IN1 and load signal D1 corresponds to case (b) mentioned in the description of Table 1.

[0084] Next, switching circuit 1 performs a left shift operation on input signal IN1 to obtain a first output signal O1 (equivalent to the first signal S1) representing a decimal number "0.42", and uses ground signal GND as a second output signal O2 representing a decimal number "0". Subsequently, a target pulse width modulation signal 201 with a load period of 42% and a target pulse width modulation signal 202 with a load period of 0% can be generated accordingly. When the target device is driven, these target pulse width modulation signals 201 and 202 can result in a 42% load period difference between target pulse width modulation signal 201 and target pulse width modulation signal 202, thereby forming a ternary modulation corresponding to a target load of 42%.

[0085] Based on the above description, the switching circuit 1 can provide a set of signals indicating the corresponding load period of the target pulse width modulation signal according to the input signal IN1 and the load signal D1. A pulse width modulation signal source (e.g., a pulse width modulation signal generation circuit) can generate this set of target pulse width modulation signals to form a ternary modulation or quaternary modulation corresponding to a specific target load, thereby driving a target device. The switching circuit 1 of the present invention not only allows the initial load period to be less than 50%, but also provides a more flexible switching mechanism to ternary modulation because the target load period required to switch to ternary modulation can be less than 100%.

[0086] Figure 4 is a schematic diagram of a switching circuit including a power-saving mode control circuit according to one or more embodiments of the present invention. The content shown in Figure 4 is only for illustrating embodiments of the present invention and is not intended to limit the present invention.

[0087] Referring to Figure 4, in some embodiments, the switching circuit 1 may further include a power-saving mode control circuit electrically connected to the target device and the third multiplexer 115 and the sixth multiplexer 125 (not shown). The power-saving mode control circuit can be used to generate a first power-saving output signal OP1 and a second power-saving output signal OP2, and may include a ternary modulation setting circuit 31 and a ternary modulation switching circuit 32. The ternary modulation setting circuit 31 can be used to generate a set of ternary modulation setting signals including a ternary modulation setting signal TS1 and a ternary modulation setting signal TS2, and the ternary modulation switching circuit 32 can be used to allow either the set of ternary modulation setting signals or both the first output signal O1 and the second output signal O2 to pass according to a power-saving mode control signal P2.

[0088] The ternary modulation setting circuit 31 may substantially include a shifter 311, a two's complement shifter 313, and multiplexers 312 and 314. Multiplexer 312 is electrically connected to shifter 311 and a ground signal source, and multiplexer 314 is electrically connected to two's complement shifter 313 and a ground signal source. Shifter 311 performs a one-bit left shift operation on the input signal IN1 to generate a fifth signal S5. Multiplexer 312 selects either the fifth signal S5 or the ground signal GND according to the polarity signal P1 to generate the ternary modulation signal TS1. Two's complement shifter 313 performs a two's complement transformation and the one-bit left shift operation on the input signal IN1 to generate a sixth signal S6. Similarly, multiplexer 314 selects either the sixth signal S6 or the ground signal GND according to the polarity signal P1 to generate the ternary modulation signal TS2.

[0089] The ternary modulation switching circuit 32 may substantially include multiplexers 321 and 322, wherein multiplexer 321 is electrically connected to multiplexer 312 and the third multiplexer 115 (not shown) of the first calculation circuit 11, and multiplexer 322 is electrically connected to multiplexer 314 and the sixth multiplexer 125 (not shown) of the second calculation circuit 12. According to the power-saving mode control signal P2, multiplexer 321 may allow the ternary modulation setting signal TS1 or the first output signal O1 to pass through to generate a first power-saving output signal OP1, and multiplexer 322 may allow the ternary modulation setting signal TS2 or the second output signal O2 to pass through to generate a second power-saving output signal OP2. When the power-saving mode control signal P2 indicates "0", both the first output signal O1 and the second output signal O2 are allowed to pass through. On the other hand, when the power saving mode control signal P2 indicates "1", the ternary modulation setting signal TS1 and the ternary modulation setting signal TS2 are allowed to pass.

[0090] In some embodiments, when the input signal IN1 is greater than a first threshold, the power-saving mode control signal P2 may represent "1", and when the input signal IN1 is less than a second threshold, the power-saving mode control signal P2 may represent "0". In some embodiments, the first threshold is less than the load signal D1, and the second threshold is less than the first threshold.

[0091] In other words, since ternary modulation can provide lower power consumption than quaternary modulation when a pulse width modulation signal corresponding to a “large” target load cycle is provided, the power-saving mode control circuit can replace the first output signal O1 and the second output signal O2 with the set of ternary modulation signals TS1 and TS2 when the input signal IN1 (indicating the target load cycle) is determined to be higher than a first threshold.

[0092] In some embodiments, when the input signal IN1 is greater than a first threshold, the power-saving mode control signal P2 represents "1", and when the input signal IN1 is less than a second threshold and the polarity of the input signal IN1 (which can be indicated by the aforementioned polarity signal P1) changes between positive and negative a third threshold number of times within a time period, the power-saving mode control signal P2 represents "0".

[0093] In some embodiments, the power-saving mode control signal may be generated by a signal generation circuit that includes at least one or more comparators (e.g., digital comparators) for comparing the input signal IN1, a first threshold, and a second threshold. In some embodiments, the signal generation circuit may further include a counter to determine whether the polarity of the input signal IN1 has changed between positive and negative a third threshold a certain number of times.

[0094] It should be understood that terms such as "first," "second," "third," "fourth," "fifth," and "sixth" used in the specification and claims of this invention are used only to distinguish different elements and not to limit the order of the elements.

[0095] Figure 5 illustrates a method for switching between ternary modulation and quaternary modulation according to one or more embodiments of the present invention. The content shown in Figure 5 is for illustrative purposes only and is not intended to limit the invention.

[0096] Referring to Figure 5, a method 4 for switching between a ternary modulation and a quaternary modulation in a target device can be executed by an electronic computing device. Method 4 may include the following steps: providing a first output signal from one of a first signal, a second signal, and a ground signal based on an input signal and a load signal, wherein the first signal is generated by performing a left shift operation of one bit on the input signal, and the second signal is generated by adding the input signal to the load signal (labeled step 401); and providing a second output signal from one of a third signal, a fourth signal, and the ground signal based on the input signal and the load signal, wherein the third signal is generated by subtracting the input signal from the load signal, and the fourth signal is generated by performing a two's complement transformation and the left shift operation of one bit on the input signal (labeled step 402). The first output signal may be the first signal when the polarity of the input signal is positive and the number represented by the input signal is greater than the number represented by the load signal, and the second output signal may be a ground signal. When the polarity of the input signal is positive and the number represented by the input signal is not higher than the number represented by the load signal, or when the polarity of the input signal is negative and the number represented by an inverted signal of the input signal is not greater than the number represented by the load signal, the first output signal can be the second signal, and the second output signal can be the third signal. When the polarity of the input signal is negative and the number represented by the inverted signal is greater than the number represented by the load signal, the first output signal can be the ground signal, and the second output signal can be the fourth signal.

[0097] In some embodiments, regarding method 4, the first output signal and the second output signal may be provided to a pulse width modulation signal generation circuit, such that the pulse width modulation signal generation circuit generates a set of pulse width modulation signals based on the first output signal and the second output signal. This set of pulse width modulation signals may form the ternary modulation or the quaternary modulation.

[0098] In some embodiments, regarding method 4, the load cycle of the ternary modulation or quaternary modulation caused by the first output signal and the second output signal can be up to twice the number represented by the input signal.

[0099] In some embodiments, method 4 may further include the following steps:

[0100] A set of ternary modulation setting signals is generated based on the input signal and the polarity of the input signal; and

[0101] The passage of either the set of ternary modulation setting signals or both the first output signal and the second output signal is determined based on a power-saving mode control signal. When the power-saving mode control signal represents zero, the first output signal and the second output signal are allowed to pass; when the power-saving mode control signal represents one, the set of ternary modulation setting signals are allowed to pass. In some embodiments, the power-saving mode control signal may represent one when the number represented by the input signal is greater than a first threshold. Furthermore, the power-saving mode control signal represents zero when the number represented by the input signal is less than a second threshold. In some other embodiments, the power-saving mode control signal may represent one when the number represented by the input signal is greater than a first threshold, and zero when the number represented by the input signal is less than a second threshold and the polarity of the input signal changes continuously between positive and negative a third threshold number of times within a time period. In some other embodiments, the first threshold may be less than the number represented by the load signal, and the second threshold may be less than the first threshold.

[0102] Each embodiment of method 4 substantially corresponds to a specific embodiment of switching circuit 1. Therefore, those skilled in the art to which this invention pertains can fully understand and implement all corresponding embodiments of modulation method 4 by referring only to the above description of switching circuit 1, even though all embodiments of modulation method 4 have not been described in detail above.

[0103] The above disclosure pertains to the detailed technical content and inventive features. Those skilled in the art can make various modifications and substitutions based on the described disclosure and suggestions without departing from the invention's characteristics. However, although such modifications and substitutions are not fully disclosed in the above description, they are substantially covered by the appended claims.

Claims

1. A switching circuit for switching between a ternary modulation and a quaternary modulation of a target device, comprising: A first computing circuit for providing a first output signal, and comprising a shifter, an adder, a first multiplexer, a second multiplexer, and a third multiplexer, wherein the first multiplexer is electrically connected to the shifter and the adder, the second multiplexer is electrically connected to the adder and a ground signal source, and the third multiplexer is electrically connected to the first and second multiplexers, wherein the shifter is configured to perform a one-bit left shift operation on an input signal to generate a first signal, and the adder is configured to add the input signal to a load signal to generate a second signal; and A second computing circuit is provided to provide a second output signal and includes a subtractor, a two's complement shifter, a fourth multiplexer, a fifth multiplexer, and a sixth multiplexer. The fourth multiplexer is electrically connected to the ground signal source and the subtractor. The fifth multiplexer is electrically connected to the subtractor and the two's complement shifter. The sixth multiplexer is electrically connected to the fourth and fifth multiplexers. The subtractor is used to subtract the input signal from the load signal to generate a third signal, and the two's complement shifter is used to perform a two's complement transformation and a left shift operation of one bit on the input signal to generate a fourth signal. in: When one polarity of the input signal is positive and the number represented by the input signal is greater than the number represented by the load signal, the first output signal output by the third multiplexer is the first signal, and the second output signal output by the sixth multiplexer is a ground signal. When the polarity of the input signal is positive and the number represented by the input signal is not greater than the number represented by the load signal, or when the polarity of the input signal is negative and the number represented by an inverse signal of the input signal is not greater than the number represented by the load signal, the first output signal is the second signal, and the second output signal is the third signal; and When the polarity of the input signal is negative and the number represented by the inverted signal is higher than the number represented by the load signal, the first output signal is the ground signal, and the second output signal is the fourth signal.

2. The switching circuit as claimed in claim 1, wherein the first calculation circuit and the second calculation circuit are electrically connected to a pulse width modulation signal generation circuit, the pulse width modulation signal generation circuit being used to generate a set of pulse width modulation signals according to the first output signal and the second output signal, the set of pulse width modulation signals forming the ternary modulation or the quaternary modulation.

3. The switching circuit of claim 1, wherein a load period of the ternary modulation or quaternary modulation caused by the first output signal and the second output signal is longer than twice the number represented by the input signal.

4. The switching circuit as described in claim 1, further comprising a power-saving mode control circuit electrically connected to the third multiplexer and the sixth multiplexer, wherein the power-saving mode control circuit comprises: A ternary modulation setting circuit is used to generate a set of ternary modulation setting signals based on the input signal and the polarity of the input signal; and A ternary modulation switching circuit is electrically connected to the ternary modulation setting circuit, the third multiplexer, and the sixth multiplexer, and is used to allow either the set of ternary modulation setting signals or both the first output signal and the second output signal to pass according to a power-saving mode control signal. The ternary modulation switching circuit allows the first output signal and the second output signal to pass when the power-saving mode control signal indicates zero, and allows the set of ternary modulation setting signals to pass when the power-saving mode control signal indicates one.

5. The switching circuit as claimed in claim 4, wherein when the number represented by the input signal is greater than a first threshold, the power-saving mode control signal represents one, and when the number represented by the input signal is less than a second threshold, the power-saving mode control signal represents zero.

6. The switching circuit of claim 4, wherein when the number represented by the input signal is greater than a first threshold, the power-saving mode control signal represents 1, and when the number represented by the input signal is less than a second threshold and the polarity of the input signal changes continuously between positive and negative a third threshold number of times within a time period, the power-saving mode control signal represents zero.

7. The switching circuit of claim 5, wherein the first threshold is less than the number represented by the load signal, and the second threshold is less than the first threshold.

8. A method for switching between a ternary modulation and a quaternary modulation in a target device, the method being performed by an electronic computing device, and comprising the following steps: Based on an input signal and a load signal, a first output signal is provided from one of a first signal, a second signal, and a ground signal, wherein the first signal is generated by performing a left shift operation of one bit on the input signal, and the second signal is generated by adding the input signal to the load signal; and Based on the input signal and the load signal, a second output signal is provided from one of a third signal, a fourth signal and the ground signal, wherein the third signal is generated by subtracting the input signal from the load signal, and the fourth signal is generated by performing a two's complement transformation and a left shift operation of one bit on the input signal; in: When one polarity of the input signal is positive and the number represented by the input signal is greater than the number represented by the load signal, the first output signal is the first signal, and the second output signal is a ground signal; When the polarity of the input signal is positive and the number represented by the input signal is not greater than the number represented by the load signal, or when the polarity of the input signal is negative and the number represented by an inverse signal of the input signal is not greater than the number represented by the load signal, the first output signal is the second signal, and the second output signal is the third signal; and When the polarity of the input signal is negative and the number represented by the inverted signal is higher than the number represented by the load signal, the first output signal is the ground signal, and the second output signal is the fourth signal.

9. The method of claim 8, wherein the first output signal and the second output signal are provided to a pulse width modulation signal generation circuit, such that the pulse width modulation signal generation circuit generates a set of pulse width modulation signals according to the first output signal and the second output signal, the set of pulse width modulation signals forming the ternary modulation or the quaternary modulation.

10. The method of claim 8, wherein a load period of the ternary modulation or the quaternary modulation caused by the first output signal and the second output signal is longer than twice the number represented by the input signal.

11. The method of claim 8, further comprising the step of: A set of ternary modulation setting signals is generated based on the input signal and the polarity of the input signal; and The passage is determined based on a power-saving mode control signal, specifically either the set of ternary modulation setting signals or both the first output signal and the second output signal. When the power-saving mode control signal indicates zero, the first output signal and the second output signal are allowed to pass, while when the power-saving mode control signal indicates one, the set of ternary modulation setting signals are allowed to pass.

12. The method of claim 11, wherein the power-saving mode control signal represents one when the number represented by the input signal is greater than a first threshold, and the power-saving mode control signal represents zero when the number represented by the input signal is less than a second threshold.

13. The method of claim 11, wherein when the number represented by the input signal is greater than a first threshold, the power-saving mode control signal represents one, and when the number represented by the input signal is less than a second threshold and the polarity of the input signal changes continuously between positive and negative a third threshold number of times within a time period, the power-saving mode control signal represents zero.

14. The method of claim 12, wherein the first threshold is less than the number represented by the load signal, and the second threshold is less than the first threshold.

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